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sh: sh7785lcr: Remove the board
Last change to this board was done in 2016, it uses non-DM USB with no prospects of ever being converted to DM USB, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
d13a6144ff
commit
06480665aa
13 changed files with 0 additions and 1308 deletions
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@ -107,10 +107,6 @@ config TARGET_SH7763RDP
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bool "SH7763RDP"
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select CPU_SH4
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config TARGET_SH7785LCR
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bool "SH7785LCR"
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select CPU_SH4A
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endchoice
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config SYS_ARCH
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@ -141,7 +137,6 @@ source "board/renesas/sh7752evb/Kconfig"
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source "board/renesas/sh7753evb/Kconfig"
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source "board/renesas/sh7757lcr/Kconfig"
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source "board/renesas/sh7763rdp/Kconfig"
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source "board/renesas/sh7785lcr/Kconfig"
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source "board/shmin/Kconfig"
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endmenu
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@ -1,12 +0,0 @@
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if TARGET_SH7785LCR
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config SYS_BOARD
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default "sh7785lcr"
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config SYS_VENDOR
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default "renesas"
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config SYS_CONFIG_NAME
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default "sh7785lcr"
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endif
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@ -1,7 +0,0 @@
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SH7785LCR BOARD
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#M: -
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S: Maintained
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F: board/renesas/sh7785lcr/
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F: include/configs/sh7785lcr.h
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F: configs/sh7785lcr_defconfig
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F: configs/sh7785lcr_32bit_defconfig
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@ -1,7 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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#
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obj-y := sh7785lcr.o selfcheck.o rtl8169_mac.o
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extra-y += lowlevel_init.o
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@ -1,123 +0,0 @@
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========================================
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Renesas Technology R0P7785LC0011RL board
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========================================
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This board specification:
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=========================
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The R0P7785LC0011RL(board config name:sh7785lcr) has the following device:
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- SH7785 (SH-4A)
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- DDR2-SDRAM 512MB
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- NOR Flash 64MB
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- 2D Graphic controller
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- SATA controller
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- Ethernet controller
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- USB host/peripheral controller
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- SD controller
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- I2C controller
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- RTC
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This board has 2 physical memory maps. It can be changed with DIP switch(S2-5).
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phys address | S2-5 = OFF | S2-5 = ON
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-------------------------------+---------------+---------------
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0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
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0x04000000 - 0x05ffffff(CS1) | PLD | PLD
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0x06000000 - 0x07ffffff(CS1) | reserved | I2C
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0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
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0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
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0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
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0x14000000 - 0x17ffffff(CS5) | I2C | USB
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0x18000000 - 0x1bffffff(CS6) | reserved | SD
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0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
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configuration for This board:
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=============================
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You can choose configuration as follows:
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- make sh7785lcr_config
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- make sh7785lcr_32bit_config
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When you use "make sh7785lcr_config", there is build U-Boot for 29-bit
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address mode. This mode can use 128MB DDR-SDRAM.
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When you use "make sh7785lcr_32bit_config", there is build U-Boot for 32-bit
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extended address mode. This mode can use 384MB DDR-SDRAM. And if you run
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"pmb" command, this mode can use 512MB DDR-SDRAM.
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* 32-bit extended address mode PMB mapping *
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a) on start-up
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virt | phys | size | device
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-------------+---------------+---------------+---------------
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0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
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0xa0000000 | 0x00000000 | 64MB | NOR Flash
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0xa4000000 | 0x04000000 | 16MB | PLD
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0xa6000000 | 0x08000000 | 16MB | USB
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0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)
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b) after "pmb" command
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virt | phys | size | device
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-------------+---------------+---------------+---------------
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0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable)
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0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable)
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This board specific command:
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============================
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This board has the following its specific command:
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- hwtest
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- printmac
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- setmac
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- pmb (sh7785lcr_32bit_config only)
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1. hwtest
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This is self-check command. This command has the following options:
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- all : test all hardware
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- pld : output PLD version
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- led : turn on LEDs
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- dipsw : test DIP switch
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- sm107 : output SM107 version
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- net : check RTL8110 ID
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- sata : check SiI3512 ID
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- net : output PCI slot device ID
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i.e)
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=> hwtest led
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turn on LEDs 3, 5, 7, 9
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turn on LEDs 4, 6, 8, 10
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=> hwtest net
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Ethernet OK
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2. printmac
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This command outputs MAC address of this board.
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i.e)
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=> printmac
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MAC = 00:00:87:**:**:**
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3. setmac
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This command writes MAC address of this board.
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i.e)
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=> setmac 00:00:87:**:**:**
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4. pmb
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This command change PMB for DDR-SDRAM all mapping. However you cannot use
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NOR Flash and USB Host on U-Boot when you run this command.
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i.e)
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=> pmb
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@ -1,361 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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#include <asm/processor.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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wait_timer WAIT_200US
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wait_timer WAIT_200US
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/*------- LBSC -------*/
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write32 MMSELR_A, MMSELR_D
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/*------- DBSC2 -------*/
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write32 DBSC2_DBCONF_A, DBSC2_DBCONF_D
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write32 DBSC2_DBTR0_A, DBSC2_DBTR0_D
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write32 DBSC2_DBTR1_A, DBSC2_DBTR1_D
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write32 DBSC2_DBTR2_A, DBSC2_DBTR2_D
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write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D1
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write32 DBSC2_DBFREQ_A, DBSC2_DBFREQ_D2
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wait_timer WAIT_200US
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write32 DBSC2_DBDICODTOCD_A, DBSC2_DBDICODTOCD_D
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write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_CKE_H
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wait_timer WAIT_200US
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write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS2
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS3
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_1
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write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_PALL
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write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
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write32 DBSC2_DBCMDCNT_A, DBSC2_DBCMDCNT_D_REF
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_MRS_2
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wait_timer WAIT_200US
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_2
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write32 DBSC2_DBMRCNT_A, DBSC2_DBMRCNT_D_EMRS1_1
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write32 DBSC2_DBEN_A, DBSC2_DBEN_D
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write32 DBSC2_DBRFCNT1_A, DBSC2_DBRFCNT1_D
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write32 DBSC2_DBRFCNT2_A, DBSC2_DBRFCNT2_D
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write32 DBSC2_DBRFCNT0_A, DBSC2_DBRFCNT0_D
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wait_timer WAIT_200US
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/*------- GPIO -------*/
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write16 PACR_A, PXCR_D
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write16 PBCR_A, PXCR_D
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write16 PCCR_A, PXCR_D
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write16 PDCR_A, PXCR_D
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write16 PECR_A, PXCR_D
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write16 PFCR_A, PXCR_D
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write16 PGCR_A, PXCR_D
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write16 PHCR_A, PHCR_D
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write16 PJCR_A, PJCR_D
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write16 PKCR_A, PKCR_D
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write16 PLCR_A, PXCR_D
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write16 PMCR_A, PMCR_D
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write16 PNCR_A, PNCR_D
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write16 PPCR_A, PXCR_D
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write16 PQCR_A, PXCR_D
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write16 PRCR_A, PXCR_D
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write8 PEPUPR_A, PEPUPR_D
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write8 PHPUPR_A, PHPUPR_D
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write8 PJPUPR_A, PJPUPR_D
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write8 PKPUPR_A, PKPUPR_D
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write8 PLPUPR_A, PLPUPR_D
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write8 PMPUPR_A, PMPUPR_D
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write8 PNPUPR_A, PNPUPR_D
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write16 PPUPR1_A, PPUPR1_D
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write16 PPUPR2_A, PPUPR2_D
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write16 P1MSELR_A, P1MSELR_D
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write16 P2MSELR_A, P2MSELR_D
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/*------- LBSC -------*/
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write32 BCR_A, BCR_D
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write32 CS0BCR_A, CS0BCR_D
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write32 CS0WCR_A, CS0WCR_D
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write32 CS1BCR_A, CS1BCR_D
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write32 CS1WCR_A, CS1WCR_D
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write32 CS4BCR_A, CS4BCR_D
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write32 CS4WCR_A, CS4WCR_D
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mov.l PASCR_A, r0
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mov.l @r0, r2
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mov.l PASCR_32BIT_MODE, r1
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tst r1, r2
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bt lbsc_29bit
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write32 CS2BCR_A, CS_USB_BCR_D
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write32 CS2WCR_A, CS_USB_WCR_D
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write32 CS3BCR_A, CS_SD_BCR_D
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write32 CS3WCR_A, CS_SD_WCR_D
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write32 CS5BCR_A, CS_I2C_BCR_D
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write32 CS5WCR_A, CS_I2C_WCR_D
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write32 CS6BCR_A, CS0BCR_D
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write32 CS6WCR_A, CS0WCR_D
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bra lbsc_end
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nop
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lbsc_29bit:
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write32 CS5BCR_A, CS_USB_BCR_D
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write32 CS5WCR_A, CS_USB_WCR_D
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write32 CS6BCR_A, CS_SD_BCR_D
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write32 CS6WCR_A, CS_SD_WCR_D
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lbsc_end:
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#if defined(CONFIG_SH_32BIT)
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/*------- set PMB -------*/
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write32 PASCR_A, PASCR_29BIT_D
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write32 MMUCR_A, MMUCR_D
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/*****************************************************************
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* ent virt phys v sz c wt
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* 0 0xa0000000 0x00000000 1 64M 0 0
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* 1 0xa4000000 0x04000000 1 16M 0 0
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* 2 0xa6000000 0x08000000 1 16M 0 0
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* 9 0x88000000 0x48000000 1 128M 1 1
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* 10 0x90000000 0x50000000 1 128M 1 1
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* 11 0x98000000 0x58000000 1 128M 1 1
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* 13 0xa8000000 0x48000000 1 128M 0 0
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* 14 0xb0000000 0x50000000 1 128M 0 0
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* 15 0xb8000000 0x58000000 1 128M 0 0
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*/
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write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D
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write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D
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write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D
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write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D
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write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D
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write32 PMB_DATA_USB_A, PMB_DATA_USB_D
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write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
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write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
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write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D
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write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D
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write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D
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write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D
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write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
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write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
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write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D
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write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D
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write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D
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write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D
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write32 PASCR_A, PASCR_INIT
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mov.l DUMMY_ADDR, r0
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icbi @r0
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#endif
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write32 CCR_A, CCR_D
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rts
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nop
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.align 4
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/*------- GPIO -------*/
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/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */
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PXCR_D: .word 0x0000
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PHCR_D: .word 0x00c0
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PJCR_D: .word 0xc3fc
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PKCR_D: .word 0x03ff
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PMCR_D: .word 0xffff
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PNCR_D: .word 0xf0c3
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PEPUPR_D: .long 0xff
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PHPUPR_D: .long 0x00
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PJPUPR_D: .long 0x00
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PKPUPR_D: .long 0x00
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PLPUPR_D: .long 0x00
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PMPUPR_D: .long 0xfc
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PNPUPR_D: .long 0x00
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PPUPR1_D: .word 0xffbf
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PPUPR2_D: .word 0xff00
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P1MSELR_D: .word 0x3780
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P2MSELR_D: .word 0x0000
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#define GPIO_BASE 0xffe70000
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PACR_A: .long GPIO_BASE + 0x00
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PBCR_A: .long GPIO_BASE + 0x02
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PCCR_A: .long GPIO_BASE + 0x04
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PDCR_A: .long GPIO_BASE + 0x06
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PECR_A: .long GPIO_BASE + 0x08
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PFCR_A: .long GPIO_BASE + 0x0a
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PGCR_A: .long GPIO_BASE + 0x0c
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PHCR_A: .long GPIO_BASE + 0x0e
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PJCR_A: .long GPIO_BASE + 0x10
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PKCR_A: .long GPIO_BASE + 0x12
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PLCR_A: .long GPIO_BASE + 0x14
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PMCR_A: .long GPIO_BASE + 0x16
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PNCR_A: .long GPIO_BASE + 0x18
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PPCR_A: .long GPIO_BASE + 0x1a
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PQCR_A: .long GPIO_BASE + 0x1c
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PRCR_A: .long GPIO_BASE + 0x1e
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PEPUPR_A: .long GPIO_BASE + 0x48
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PHPUPR_A: .long GPIO_BASE + 0x4e
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PJPUPR_A: .long GPIO_BASE + 0x50
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PKPUPR_A: .long GPIO_BASE + 0x52
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PLPUPR_A: .long GPIO_BASE + 0x54
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PMPUPR_A: .long GPIO_BASE + 0x56
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PNPUPR_A: .long GPIO_BASE + 0x58
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PPUPR1_A: .long GPIO_BASE + 0x60
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PPUPR2_A: .long GPIO_BASE + 0x62
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P1MSELR_A: .long GPIO_BASE + 0x80
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P2MSELR_A: .long GPIO_BASE + 0x82
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MMSELR_A: .long 0xfc400020
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#if defined(CONFIG_SH_32BIT)
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MMSELR_D: .long 0xa5a50005
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#else
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MMSELR_D: .long 0xa5a50002
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#endif
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/*------- DBSC2 -------*/
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#define DBSC2_BASE 0xfe800000
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DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
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DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
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DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
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DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
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DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
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DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
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DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
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DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
|
||||
DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
|
||||
DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
|
||||
DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
|
||||
DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
|
||||
DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54
|
||||
DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
|
||||
DDR_DUMMY_ACCESS_A: .long 0x40000000
|
||||
|
||||
DBSC2_DBCONF_D: .long 0x00630002
|
||||
DBSC2_DBTR0_D: .long 0x050b1f04
|
||||
DBSC2_DBTR1_D: .long 0x00040204
|
||||
DBSC2_DBTR2_D: .long 0x02100308
|
||||
DBSC2_DBFREQ_D1: .long 0x00000000
|
||||
DBSC2_DBFREQ_D2: .long 0x00000100
|
||||
DBSC2_DBDICODTOCD_D:.long 0x000f0907
|
||||
|
||||
DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
|
||||
DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
|
||||
DBSC2_DBCMDCNT_D_REF: .long 0x00000004
|
||||
|
||||
DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
|
||||
DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
|
||||
DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
|
||||
DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
|
||||
DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
|
||||
DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
|
||||
|
||||
DBSC2_DBEN_D: .long 0x00000001
|
||||
|
||||
DBSC2_DBPDCNT0_D3: .long 0x00000080
|
||||
DBSC2_DBRFCNT1_D: .long 0x00000926
|
||||
DBSC2_DBRFCNT2_D: .long 0x00fe00fe
|
||||
DBSC2_DBRFCNT0_D: .long 0x00010000
|
||||
|
||||
WAIT_200US: .long 33333
|
||||
|
||||
/*------- LBSC -------*/
|
||||
PASCR_A: .long 0xff000070
|
||||
PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
|
||||
|
||||
BCR_A: .long BCR
|
||||
CS0BCR_A: .long CS0BCR
|
||||
CS0WCR_A: .long CS0WCR
|
||||
CS1BCR_A: .long CS1BCR
|
||||
CS1WCR_A: .long CS1WCR
|
||||
CS2BCR_A: .long CS2BCR
|
||||
CS2WCR_A: .long CS2WCR
|
||||
CS3BCR_A: .long CS3BCR
|
||||
CS3WCR_A: .long CS3WCR
|
||||
CS4BCR_A: .long CS4BCR
|
||||
CS4WCR_A: .long CS4WCR
|
||||
CS5BCR_A: .long CS5BCR
|
||||
CS5WCR_A: .long CS5WCR
|
||||
CS6BCR_A: .long CS6BCR
|
||||
CS6WCR_A: .long CS6WCR
|
||||
|
||||
BCR_D: .long 0x80000003
|
||||
CS0BCR_D: .long 0x22222340
|
||||
CS0WCR_D: .long 0x00111118
|
||||
CS1BCR_D: .long 0x11111100
|
||||
CS1WCR_D: .long 0x33333303
|
||||
CS4BCR_D: .long 0x11111300
|
||||
CS4WCR_D: .long 0x00101012
|
||||
|
||||
/* USB setting : 32bit mode = CS2, 29bit mode = CS5 */
|
||||
CS_USB_BCR_D: .long 0x11111200
|
||||
CS_USB_WCR_D: .long 0x00020005
|
||||
|
||||
/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
|
||||
CS_SD_BCR_D: .long 0x00000300
|
||||
CS_SD_WCR_D: .long 0x00030108
|
||||
|
||||
/* I2C setting : 32bit mode = CS5, 29bit mode = CS1(already setting) */
|
||||
CS_I2C_BCR_D: .long 0x11111100
|
||||
CS_I2C_WCR_D: .long 0x00000003
|
||||
|
||||
#if defined(CONFIG_SH_32BIT)
|
||||
/*------- set PMB -------*/
|
||||
PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0)
|
||||
PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1)
|
||||
PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2)
|
||||
PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9)
|
||||
PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10)
|
||||
PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11)
|
||||
PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13)
|
||||
PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14)
|
||||
PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15)
|
||||
|
||||
PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0)
|
||||
PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4)
|
||||
PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6)
|
||||
PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
|
||||
PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90)
|
||||
PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98)
|
||||
PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
|
||||
PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0)
|
||||
PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8)
|
||||
|
||||
PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0)
|
||||
PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1)
|
||||
PMB_DATA_USB_A: .long PMB_DATA_BASE(2)
|
||||
PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9)
|
||||
PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10)
|
||||
PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11)
|
||||
PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13)
|
||||
PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14)
|
||||
PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15)
|
||||
|
||||
/* ppn ub v s1 s0 c wt */
|
||||
PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
|
||||
PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
|
||||
PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
|
||||
PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
|
||||
PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
|
||||
PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
|
||||
PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
|
||||
PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
|
||||
PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
|
||||
|
||||
DUMMY_ADDR: .long 0xa0000000
|
||||
PASCR_29BIT_D: .long 0x00000000
|
||||
PASCR_INIT: .long 0x80000080 /* check booting mode */
|
||||
MMUCR_A: .long 0xff000010
|
||||
MMUCR_D: .long 0x00000004 /* clear ITLB */
|
||||
#endif /* CONFIG_SH_32BIT */
|
||||
|
||||
CCR_A: .long 0xff00001c
|
||||
CCR_D: .long 0x0000090b
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*/
|
||||
|
||||
#define PCIREG_8(_adr) (*(volatile unsigned char *)(_adr))
|
||||
#define PCIREG_32(_adr) (*(volatile unsigned long *)(_adr))
|
||||
#define PCI_PAR PCIREG_32(0xfe0401c0)
|
||||
#define PCI_PDR PCIREG_32(0xfe040220)
|
||||
#define PCI_CR PCIREG_32(0xfe040100)
|
||||
#define PCI_CONF1 PCIREG_32(0xfe040004)
|
||||
|
||||
#define HIGH 1
|
||||
#define LOW 0
|
||||
|
||||
#define PCI_PROG 0x80
|
||||
#define PCI_EEP_ADDRESS (unsigned short)0x0007
|
||||
#define PCI_MAC_ADDRESS_SIZE 3
|
||||
|
||||
#define TIME1 100
|
||||
#define TIME2 20000
|
||||
|
||||
#define BIT_DUMMY 0
|
||||
#define MAC_EEP_READ 1
|
||||
#define MAC_EEP_WRITE 2
|
||||
#define MAC_EEP_ERACE 3
|
||||
#define MAC_EEP_EWEN 4
|
||||
#define MAC_EEP_EWDS 5
|
||||
|
||||
/* RTL8169 */
|
||||
const unsigned short EEPROM_W_Data_8169_A[] = {
|
||||
0x8129, 0x10ec, 0x8169, 0x1154, 0x032b,
|
||||
0x4020, 0xa101
|
||||
};
|
||||
const unsigned short EEPROM_W_Data_8169_B[] = {
|
||||
0x4d15, 0xf7c2, 0x8000, 0x0000, 0x0000, 0x1300,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x2000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
|
||||
};
|
||||
|
|
@ -1,330 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "rtl8169.h"
|
||||
|
||||
static unsigned char *PCI_MEMR;
|
||||
|
||||
static void mac_delay(unsigned int cnt)
|
||||
{
|
||||
udelay(cnt);
|
||||
}
|
||||
|
||||
static void mac_pci_setup(void)
|
||||
{
|
||||
unsigned long pci_data;
|
||||
|
||||
PCI_PAR = 0x00000010;
|
||||
PCI_PDR = 0x00001000;
|
||||
PCI_PAR = 0x00000004;
|
||||
pci_data = PCI_PDR;
|
||||
PCI_PDR = pci_data | 0x00000007;
|
||||
PCI_PAR = 0x00000010;
|
||||
|
||||
PCI_MEMR = (unsigned char *)((PCI_PDR | 0xFE240050) & 0xFFFFFFF0);
|
||||
}
|
||||
|
||||
static void EECS(int level)
|
||||
{
|
||||
unsigned char data = *PCI_MEMR;
|
||||
|
||||
if (level)
|
||||
*PCI_MEMR = data | 0x08;
|
||||
else
|
||||
*PCI_MEMR = data & 0xf7;
|
||||
}
|
||||
|
||||
static void EECLK(int level)
|
||||
{
|
||||
unsigned char data = *PCI_MEMR;
|
||||
|
||||
if (level)
|
||||
*PCI_MEMR = data | 0x04;
|
||||
else
|
||||
*PCI_MEMR = data & 0xfb;
|
||||
}
|
||||
|
||||
static void EEDI(int level)
|
||||
{
|
||||
unsigned char data = *PCI_MEMR;
|
||||
|
||||
if (level)
|
||||
*PCI_MEMR = data | 0x02;
|
||||
else
|
||||
*PCI_MEMR = data & 0xfd;
|
||||
}
|
||||
|
||||
static inline void sh7785lcr_bitset(unsigned short bit)
|
||||
{
|
||||
if (bit)
|
||||
EEDI(HIGH);
|
||||
else
|
||||
EEDI(LOW);
|
||||
|
||||
EECLK(LOW);
|
||||
mac_delay(TIME1);
|
||||
EECLK(HIGH);
|
||||
mac_delay(TIME1);
|
||||
EEDI(LOW);
|
||||
}
|
||||
|
||||
static inline unsigned char sh7785lcr_bitget(void)
|
||||
{
|
||||
unsigned char bit;
|
||||
|
||||
EECLK(LOW);
|
||||
mac_delay(TIME1);
|
||||
bit = *PCI_MEMR & 0x01;
|
||||
EECLK(HIGH);
|
||||
mac_delay(TIME1);
|
||||
|
||||
return bit;
|
||||
}
|
||||
|
||||
static inline void sh7785lcr_setcmd(unsigned char command)
|
||||
{
|
||||
sh7785lcr_bitset(BIT_DUMMY);
|
||||
switch (command) {
|
||||
case MAC_EEP_READ:
|
||||
sh7785lcr_bitset(1);
|
||||
sh7785lcr_bitset(1);
|
||||
sh7785lcr_bitset(0);
|
||||
break;
|
||||
case MAC_EEP_WRITE:
|
||||
sh7785lcr_bitset(1);
|
||||
sh7785lcr_bitset(0);
|
||||
sh7785lcr_bitset(1);
|
||||
break;
|
||||
case MAC_EEP_ERACE:
|
||||
sh7785lcr_bitset(1);
|
||||
sh7785lcr_bitset(1);
|
||||
sh7785lcr_bitset(1);
|
||||
break;
|
||||
case MAC_EEP_EWEN:
|
||||
sh7785lcr_bitset(1);
|
||||
sh7785lcr_bitset(0);
|
||||
sh7785lcr_bitset(0);
|
||||
break;
|
||||
case MAC_EEP_EWDS:
|
||||
sh7785lcr_bitset(1);
|
||||
sh7785lcr_bitset(0);
|
||||
sh7785lcr_bitset(0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static inline unsigned short sh7785lcr_getdt(void)
|
||||
{
|
||||
unsigned short data = 0;
|
||||
int i;
|
||||
|
||||
sh7785lcr_bitget(); /* DUMMY */
|
||||
for (i = 0 ; i < 16 ; i++) {
|
||||
data <<= 1;
|
||||
data |= sh7785lcr_bitget();
|
||||
}
|
||||
return data;
|
||||
}
|
||||
|
||||
static inline void sh7785lcr_setadd(unsigned short address)
|
||||
{
|
||||
sh7785lcr_bitset(address & 0x0020); /* A5 */
|
||||
sh7785lcr_bitset(address & 0x0010); /* A4 */
|
||||
sh7785lcr_bitset(address & 0x0008); /* A3 */
|
||||
sh7785lcr_bitset(address & 0x0004); /* A2 */
|
||||
sh7785lcr_bitset(address & 0x0002); /* A1 */
|
||||
sh7785lcr_bitset(address & 0x0001); /* A0 */
|
||||
}
|
||||
|
||||
static inline void sh7785lcr_setdata(unsigned short data)
|
||||
{
|
||||
sh7785lcr_bitset(data & 0x8000);
|
||||
sh7785lcr_bitset(data & 0x4000);
|
||||
sh7785lcr_bitset(data & 0x2000);
|
||||
sh7785lcr_bitset(data & 0x1000);
|
||||
sh7785lcr_bitset(data & 0x0800);
|
||||
sh7785lcr_bitset(data & 0x0400);
|
||||
sh7785lcr_bitset(data & 0x0200);
|
||||
sh7785lcr_bitset(data & 0x0100);
|
||||
sh7785lcr_bitset(data & 0x0080);
|
||||
sh7785lcr_bitset(data & 0x0040);
|
||||
sh7785lcr_bitset(data & 0x0020);
|
||||
sh7785lcr_bitset(data & 0x0010);
|
||||
sh7785lcr_bitset(data & 0x0008);
|
||||
sh7785lcr_bitset(data & 0x0004);
|
||||
sh7785lcr_bitset(data & 0x0002);
|
||||
sh7785lcr_bitset(data & 0x0001);
|
||||
}
|
||||
|
||||
static void sh7785lcr_datawrite(const unsigned short *data, unsigned short address,
|
||||
unsigned int count)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
EECS(HIGH);
|
||||
EEDI(LOW);
|
||||
mac_delay(TIME1);
|
||||
|
||||
sh7785lcr_setcmd(MAC_EEP_WRITE);
|
||||
sh7785lcr_setadd(address++);
|
||||
sh7785lcr_setdata(*(data + i));
|
||||
|
||||
EECLK(LOW);
|
||||
EEDI(LOW);
|
||||
EECS(LOW);
|
||||
mac_delay(TIME2);
|
||||
}
|
||||
}
|
||||
|
||||
static void sh7785lcr_macerase(void)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned short pci_address = 7;
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
EECS(HIGH);
|
||||
EEDI(LOW);
|
||||
mac_delay(TIME1);
|
||||
sh7785lcr_setcmd(MAC_EEP_ERACE);
|
||||
sh7785lcr_setadd(pci_address++);
|
||||
mac_delay(TIME1);
|
||||
EECLK(LOW);
|
||||
EEDI(LOW);
|
||||
EECS(LOW);
|
||||
}
|
||||
|
||||
mac_delay(TIME2);
|
||||
|
||||
printf("\n\nErace End\n");
|
||||
for (i = 0; i < 10; i++)
|
||||
mac_delay(TIME2);
|
||||
}
|
||||
|
||||
static void sh7785lcr_macwrite(unsigned short *data)
|
||||
{
|
||||
sh7785lcr_macerase();
|
||||
|
||||
sh7785lcr_datawrite(EEPROM_W_Data_8169_A, 0x0000, 7);
|
||||
sh7785lcr_datawrite(data, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE);
|
||||
sh7785lcr_datawrite(EEPROM_W_Data_8169_B, 0x000a, 54);
|
||||
}
|
||||
|
||||
void sh7785lcr_macdtrd(unsigned char *buf, unsigned short address, unsigned int count)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned short wk;
|
||||
|
||||
for (i = 0 ; i < count; i++) {
|
||||
EECS(HIGH);
|
||||
EEDI(LOW);
|
||||
mac_delay(TIME1);
|
||||
sh7785lcr_setcmd(MAC_EEP_READ);
|
||||
sh7785lcr_setadd(address++);
|
||||
wk = sh7785lcr_getdt();
|
||||
|
||||
*buf++ = (unsigned char)(wk & 0xff);
|
||||
*buf++ = (unsigned char)((wk >> 8) & 0xff);
|
||||
EECLK(LOW);
|
||||
EEDI(LOW);
|
||||
EECS(LOW);
|
||||
}
|
||||
}
|
||||
|
||||
static void sh7785lcr_macadrd(unsigned char *buf)
|
||||
{
|
||||
*PCI_MEMR = PCI_PROG;
|
||||
|
||||
sh7785lcr_macdtrd(buf, PCI_EEP_ADDRESS, PCI_MAC_ADDRESS_SIZE);
|
||||
}
|
||||
|
||||
static void sh7785lcr_eepewen(void)
|
||||
{
|
||||
*PCI_MEMR = PCI_PROG;
|
||||
mac_delay(TIME1);
|
||||
EECS(LOW);
|
||||
EECLK(LOW);
|
||||
EEDI(LOW);
|
||||
EECS(HIGH);
|
||||
mac_delay(TIME1);
|
||||
|
||||
sh7785lcr_setcmd(MAC_EEP_EWEN);
|
||||
sh7785lcr_bitset(1);
|
||||
sh7785lcr_bitset(1);
|
||||
sh7785lcr_bitset(BIT_DUMMY);
|
||||
sh7785lcr_bitset(BIT_DUMMY);
|
||||
sh7785lcr_bitset(BIT_DUMMY);
|
||||
sh7785lcr_bitset(BIT_DUMMY);
|
||||
|
||||
EECLK(LOW);
|
||||
EEDI(LOW);
|
||||
EECS(LOW);
|
||||
mac_delay(TIME1);
|
||||
}
|
||||
|
||||
void mac_write(unsigned short *data)
|
||||
{
|
||||
mac_pci_setup();
|
||||
sh7785lcr_eepewen();
|
||||
sh7785lcr_macwrite(data);
|
||||
}
|
||||
|
||||
void mac_read(void)
|
||||
{
|
||||
unsigned char data[6];
|
||||
|
||||
mac_pci_setup();
|
||||
sh7785lcr_macadrd(data);
|
||||
printf("Mac = %02x:%02x:%02x:%02x:%02x:%02x\n",
|
||||
data[0], data[1], data[2], data[3], data[4], data[5]);
|
||||
}
|
||||
|
||||
int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
int i;
|
||||
unsigned char mac[6];
|
||||
char *s, *e;
|
||||
|
||||
if (argc != 2)
|
||||
return cmd_usage(cmdtp);
|
||||
|
||||
s = argv[1];
|
||||
|
||||
for (i = 0; i < 6; i++) {
|
||||
mac[i] = s ? simple_strtoul(s, &e, 16) : 0;
|
||||
if (s)
|
||||
s = (*e) ? e + 1 : e;
|
||||
}
|
||||
mac_write((unsigned short *)mac);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
setmac, 2, 1, do_set_mac,
|
||||
"write MAC address for RTL8110SCL",
|
||||
"\n"
|
||||
"setmac <mac address> - write MAC address for RTL8110SCL"
|
||||
);
|
||||
|
||||
int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
if (argc != 1)
|
||||
return cmd_usage(cmdtp);
|
||||
|
||||
mac_read();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
printmac, 1, 1, do_print_mac,
|
||||
"print MAC address for RTL8110",
|
||||
"\n"
|
||||
" - print MAC address for RTL8110"
|
||||
);
|
||||
|
|
@ -1,150 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <console.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/pci.h>
|
||||
|
||||
#if defined(CONFIG_CPU_32BIT)
|
||||
#define NOCACHE_OFFSET 0x00000000
|
||||
#else
|
||||
#define NOCACHE_OFFSET 0xa0000000
|
||||
#endif
|
||||
#define PLD_LEDCR (0x04000008 + NOCACHE_OFFSET)
|
||||
#define PLD_SWSR (0x0400000a + NOCACHE_OFFSET)
|
||||
#define PLD_VERSR (0x0400000c + NOCACHE_OFFSET)
|
||||
|
||||
#define SM107_DEVICEID (0x13e00060 + NOCACHE_OFFSET)
|
||||
|
||||
static void test_pld(void)
|
||||
{
|
||||
printf("PLD version = %04x\n", readb(PLD_VERSR));
|
||||
}
|
||||
|
||||
static void test_sm107(void)
|
||||
{
|
||||
printf("SM107 device ID = %04x\n", readl(SM107_DEVICEID));
|
||||
}
|
||||
|
||||
static void test_led(void)
|
||||
{
|
||||
printf("turn on LEDs 3, 5, 7, 9\n");
|
||||
writeb(0x55, PLD_LEDCR);
|
||||
mdelay(2000);
|
||||
printf("turn on LEDs 4, 6, 8, 10\n");
|
||||
writeb(0xaa, PLD_LEDCR);
|
||||
mdelay(2000);
|
||||
writeb(0x00, PLD_LEDCR);
|
||||
}
|
||||
|
||||
static void test_dipsw(void)
|
||||
{
|
||||
printf("Please DIPSW set = B'0101\n");
|
||||
while (readb(PLD_SWSR) != 0x05) {
|
||||
if (ctrlc())
|
||||
return;
|
||||
}
|
||||
printf("Please DIPSW set = B'1010\n");
|
||||
while (readb(PLD_SWSR) != 0x0A) {
|
||||
if (ctrlc())
|
||||
return;
|
||||
}
|
||||
printf("DIPSW OK\n");
|
||||
}
|
||||
|
||||
static void test_net(void)
|
||||
{
|
||||
unsigned long data;
|
||||
|
||||
writel(0x80000000, 0xfe0401c0);
|
||||
data = readl(0xfe040220);
|
||||
if (data == 0x816910ec)
|
||||
printf("Ethernet OK\n");
|
||||
else
|
||||
printf("Ethernet NG, data = %08x\n", (unsigned int)data);
|
||||
}
|
||||
|
||||
static void test_sata(void)
|
||||
{
|
||||
unsigned long data;
|
||||
|
||||
writel(0x80000800, 0xfe0401c0);
|
||||
data = readl(0xfe040220);
|
||||
if (data == 0x35121095)
|
||||
printf("SATA OK\n");
|
||||
else
|
||||
printf("SATA NG, data = %08x\n", (unsigned int)data);
|
||||
}
|
||||
|
||||
static void test_pci(void)
|
||||
{
|
||||
writel(0x80001800, 0xfe0401c0);
|
||||
printf("PCI CN1 ID = %08x\n", readl(0xfe040220));
|
||||
|
||||
writel(0x80001000, 0xfe0401c0);
|
||||
printf("PCI CN2 ID = %08x\n", readl(0xfe040220));
|
||||
}
|
||||
|
||||
int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
char *cmd;
|
||||
|
||||
if (argc != 2)
|
||||
return cmd_usage(cmdtp);
|
||||
|
||||
cmd = argv[1];
|
||||
switch (cmd[0]) {
|
||||
case 'a': /* all */
|
||||
test_pld();
|
||||
test_led();
|
||||
test_dipsw();
|
||||
test_sm107();
|
||||
test_net();
|
||||
test_sata();
|
||||
test_pci();
|
||||
break;
|
||||
case 'p': /* pld or pci */
|
||||
if (cmd[1] == 'l')
|
||||
test_pld();
|
||||
else
|
||||
test_pci();
|
||||
break;
|
||||
case 'l': /* led */
|
||||
test_led();
|
||||
break;
|
||||
case 'd': /* dipsw */
|
||||
test_dipsw();
|
||||
break;
|
||||
case 's': /* sm107 or sata */
|
||||
if (cmd[1] == 'm')
|
||||
test_sm107();
|
||||
else
|
||||
test_sata();
|
||||
break;
|
||||
case 'n': /* net */
|
||||
test_net();
|
||||
break;
|
||||
default:
|
||||
return cmd_usage(cmdtp);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
hwtest, 2, 1, do_hw_test,
|
||||
"hardware test for R0P7785LC0011RL board",
|
||||
"\n"
|
||||
"hwtest all - test all hardware\n"
|
||||
"hwtest pld - output PLD version\n"
|
||||
"hwtest led - turn on LEDs\n"
|
||||
"hwtest dipsw - test DIP switch\n"
|
||||
"hwtest sm107 - output SM107 version\n"
|
||||
"hwtest net - check RTL8110 ID\n"
|
||||
"hwtest sata - check SiI3512 ID\n"
|
||||
"hwtest pci - output PCI slot device ID"
|
||||
);
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/pci.h>
|
||||
#include <netdev.h>
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pci_controller hose;
|
||||
void pci_init_board(void)
|
||||
{
|
||||
pci_sh7780_init(&hose);
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SH_32BIT)
|
||||
int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
/* clear ITLB */
|
||||
writel(0x00000004, 0xff000010);
|
||||
|
||||
/* delete PMB for peripheral */
|
||||
writel(0, PMB_ADDR_BASE(0));
|
||||
writel(0, PMB_DATA_BASE(0));
|
||||
writel(0, PMB_ADDR_BASE(1));
|
||||
writel(0, PMB_DATA_BASE(1));
|
||||
writel(0, PMB_ADDR_BASE(2));
|
||||
writel(0, PMB_DATA_BASE(2));
|
||||
|
||||
/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
|
||||
writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8));
|
||||
writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8));
|
||||
writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12));
|
||||
writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
pmb, 1, 1, do_pmb,
|
||||
"pmb - PMB setting\n",
|
||||
"\n"
|
||||
" - PMB setting for all SDRAM mapping"
|
||||
);
|
||||
#endif
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
CONFIG_SH=y
|
||||
CONFIG_SYS_TEXT_BASE=0x8FF80000
|
||||
CONFIG_SH_32BIT=y
|
||||
CONFIG_TARGET_SH7785LCR=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttySC1,115200 root=/dev/nfs ip=dhcp"
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
# CONFIG_CMDLINE_EDITING is not set
|
||||
# CONFIG_AUTO_COMPLETE is not set
|
||||
# CONFIG_CMD_BDI is not set
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_ENV_EXISTS is not set
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_ECHO is not set
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SOURCE is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_PING=y
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USE_PRIVATE_LIBGCC=y
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
CONFIG_SH=y
|
||||
CONFIG_SYS_TEXT_BASE=0x0FF80000
|
||||
CONFIG_TARGET_SH7785LCR=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttySC1,115200 root=/dev/nfs ip=dhcp"
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
# CONFIG_CMDLINE_EDITING is not set
|
||||
# CONFIG_AUTO_COMPLETE is not set
|
||||
# CONFIG_CMD_BDI is not set
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_EDITENV is not set
|
||||
# CONFIG_CMD_ENV_EXISTS is not set
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SDRAM=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_ECHO is not set
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SOURCE is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_PING=y
|
||||
# CONFIG_CMD_MISC is not set
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USE_PRIVATE_LIBGCC=y
|
||||
|
|
@ -1,128 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Configuation settings for the Renesas Technology R0P7785LC0011RL board
|
||||
*
|
||||
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*/
|
||||
|
||||
#ifndef __SH7785LCR_H
|
||||
#define __SH7785LCR_H
|
||||
|
||||
#define CONFIG_CPU_SH7785 1
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootdevice=0:1\0" \
|
||||
"usbload=usb reset;usbboot;usb stop;bootm\0"
|
||||
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
/* MEMORY */
|
||||
#if defined(CONFIG_SH_32BIT)
|
||||
/* 0x40000000 - 0x47FFFFFF does not use */
|
||||
#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
|
||||
#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
|
||||
#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
|
||||
#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
|
||||
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
|
||||
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
|
||||
#define SH7785LCR_USB_BASE (0xa6000000)
|
||||
#else
|
||||
#define SH7785LCR_SDRAM_BASE (0x08000000)
|
||||
#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
|
||||
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
|
||||
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
|
||||
#define SH7785LCR_USB_BASE (0xb4000000)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_PBSIZE 256
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
|
||||
|
||||
/* SCIF */
|
||||
#define CONFIG_CONS_SCIF1 1
|
||||
#define CONFIG_SCIF_EXT_CLOCK 1
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
|
||||
(SH7785LCR_SDRAM_SIZE) - \
|
||||
4 * 1024 * 1024)
|
||||
#undef CONFIG_SYS_MEMTEST_SCRATCH
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
|
||||
#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
/* FLASH */
|
||||
#undef CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \
|
||||
(0 * SH7785LCR_FLASH_BANK_SIZE) }
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
|
||||
#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
|
||||
#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
|
||||
|
||||
#undef CONFIG_SYS_DIRECT_FLASH_TFTP
|
||||
|
||||
/* R8A66597 */
|
||||
#define CONFIG_USB_R8A66597_HCD
|
||||
#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
|
||||
#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
|
||||
#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
|
||||
#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
|
||||
|
||||
/* PCI Controller */
|
||||
#define CONFIG_SH4_PCI
|
||||
#define CONFIG_SH7780_PCI
|
||||
#if defined(CONFIG_SH_32BIT)
|
||||
#define CONFIG_SH7780_PCI_LSR 0x1ff00001
|
||||
#define CONFIG_SH7780_PCI_LAR 0x5f000000
|
||||
#define CONFIG_SH7780_PCI_BAR 0x5f000000
|
||||
#else
|
||||
#define CONFIG_SH7780_PCI_LSR 0x07f00001
|
||||
#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
|
||||
#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
|
||||
#endif
|
||||
#define CONFIG_PCI_SCAN_SHOW 1
|
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
|
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
|
||||
#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
|
||||
|
||||
#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
|
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
|
||||
#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
|
||||
|
||||
#if defined(CONFIG_SH_32BIT)
|
||||
#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
|
||||
#else
|
||||
#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
|
||||
#endif
|
||||
#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
|
||||
|
||||
/* ENV setting */
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
|
||||
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
|
||||
|
||||
/* Board Clock */
|
||||
/* The SCIF used external clock. system clock only used timer. */
|
||||
#define CONFIG_SYS_CLK_FREQ 50000000
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
|
||||
|
||||
#endif /* __SH7785LCR_H */
|
||||
Loading…
Add table
Reference in a new issue