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pinctrl: at91: add slewrate support for SAM9X60

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Add slew rate support for SAM9X60 pin controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
This commit is contained in:
Claudiu Beznea 2019-03-25 10:34:00 +00:00 • committed by Eugen Hristev
parent be6e24054d
commit 068d4c0a11
2 changed files with 38 additions and 0 deletions
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34
drivers/pinctrl/pinctrl-at91.c
View file

@ -37,6 +37,9 @@ struct at91_pinctrl_priv {
#define OUTPUT BIT(7) #define OUTPUT BIT(7)
#define OUTPUT_VAL_SHIFT 8 #define OUTPUT_VAL_SHIFT 8
#define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT) #define OUTPUT_VAL (0x1 << OUTPUT_VAL_SHIFT)
#define SLEWRATE_SHIFT 9
#define SLEWRATE_MASK 0x1
#define SLEWRATE (SLEWRATE_MASK << SLEWRATE_SHIFT)
#define DEBOUNCE BIT(16) #define DEBOUNCE BIT(16)
#define DEBOUNCE_VAL_SHIFT 17 #define DEBOUNCE_VAL_SHIFT 17
#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
@ -60,6 +63,13 @@ enum drive_strength_bit {
#define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \ #define DRIVE_STRENGTH_BIT_MSK(name) (DRIVE_STRENGTH_BIT_##name << \
DRIVE_STRENGTH_SHIFT) DRIVE_STRENGTH_SHIFT)
enum slewrate_bit {
SLEWRATE_BIT_DIS,
SLEWRATE_BIT_ENA,
};
#define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
enum at91_mux { enum at91_mux {
AT91_MUX_GPIO = 0, AT91_MUX_GPIO = 0,
AT91_MUX_PERIPH_A = 1, AT91_MUX_PERIPH_A = 1,
@ -95,6 +105,7 @@ struct at91_pinctrl_mux_ops {
void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask); void (*disable_schmitt_trig)(struct at91_port *pio, u32 mask);
void (*set_drivestrength)(struct at91_port *pio, u32 pin, void (*set_drivestrength)(struct at91_port *pio, u32 pin,
u32 strength); u32 strength);
void (*set_slewrate)(struct at91_port *pio, u32 pin, u32 slewrate);
}; };
static u32 two_bit_pin_value_shift_amount(u32 pin) static u32 two_bit_pin_value_shift_amount(u32 pin)
@ -270,6 +281,25 @@ static void at91_mux_sam9x60_set_drivestrength(struct at91_port *pio, u32 pin,
writel(tmp, reg); writel(tmp, reg);
} }
static void at91_mux_sam9x60_set_slewrate(struct at91_port *pio, u32 pin,
u32 setting)
{
void *reg = &pio->reserved12[3];
u32 tmp;
if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA)
return;
tmp = readl(reg);
if (setting == SLEWRATE_BIT_DIS)
tmp &= ~BIT(pin);
else
tmp |= BIT(pin);
writel(tmp, reg);
}
static struct at91_pinctrl_mux_ops at91rm9200_ops = { static struct at91_pinctrl_mux_ops at91rm9200_ops = {
.mux_A_periph = at91_mux_set_A_periph, .mux_A_periph = at91_mux_set_A_periph,
.mux_B_periph = at91_mux_set_B_periph, .mux_B_periph = at91_mux_set_B_periph,
@ -310,6 +340,7 @@ static struct at91_pinctrl_mux_ops sam9x60_ops = {
.set_pulldown = at91_mux_pio3_set_pulldown, .set_pulldown = at91_mux_pio3_set_pulldown,
.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
.set_drivestrength = at91_mux_sam9x60_set_drivestrength, .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
.set_slewrate = at91_mux_sam9x60_set_slewrate,
}; };
static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask) static void at91_mux_gpio_disable(struct at91_port *pio, u32 mask)
@ -378,6 +409,9 @@ static int at91_pinconf_set(struct at91_pinctrl_mux_ops *ops,
if (ops->set_drivestrength) if (ops->set_drivestrength)
ops->set_drivestrength(pio, pin, ops->set_drivestrength(pio, pin,
(config & DRIVE_STRENGTH) >> DRIVE_STRENGTH_SHIFT); (config & DRIVE_STRENGTH) >> DRIVE_STRENGTH_SHIFT);
if (ops->set_slewrate)
ops->set_slewrate(pio, pin,
(config & SLEWRATE) >> SLEWRATE_SHIFT);
return 0; return 0;
} }

4
include/dt-bindings/pinctrl/at91.h
View file

@ -17,6 +17,7 @@
#define AT91_PINCTRL_DIS_SCHMIT (1 << 4) #define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
#define AT91_PINCTRL_OUTPUT (1 << 7) #define AT91_PINCTRL_OUTPUT (1 << 7)
#define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8) #define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
#define AT91_PINCTRL_SLEWRATE (1 << 9)
#define AT91_PINCTRL_DEBOUNCE (1 << 16) #define AT91_PINCTRL_DEBOUNCE (1 << 16)
#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17) #define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
@ -27,6 +28,9 @@
#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5) #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5) #define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9)
#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9)
#define AT91_PIOA 0 #define AT91_PIOA 0
#define AT91_PIOB 1 #define AT91_PIOB 1
#define AT91_PIOC 2 #define AT91_PIOC 2