Merge git://git.denx.de/u-boot-x86

arch/Kconfig

@@ -87,15 +87,26 @@ config X86
 	bool "x86 architecture"
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC
+	select USE_PRIVATE_LIBGCC
 	select SUPPORT_OF_CONTROL
+	select OF_CONTROL
 	select DM
-	select DM_KEYBOARD
+	select DM_PCI
-	select DM_SERIAL
+	select PCI
-	select DM_GPIO
+	select TIMER
-	select DM_SPI
+	select X86_TSC_TIMER
-	select DM_SPI_FLASH
+	imply BLK
-	select USB
+	imply DM_ETH
-	select USB_EHCI_HCD
+	imply DM_GPIO
+	imply DM_KEYBOARD
+	imply DM_MMC
+	imply DM_RTC
+	imply DM_SERIAL
+	imply DM_SCSI
+	imply DM_SPI
+	imply DM_SPI_FLASH
+	imply DM_USB
+	imply DM_VIDEO
 	imply CMD_FPGA_LOADMK
 	imply CMD_GETTIME
 	imply CMD_IO

arch/x86/Kconfig

@@ -542,6 +542,19 @@ config VGA_BIOS_ADDR
 	  address of 0xfff90000 indicates that the image will be put at offset
 	  0x90000 from the beginning of a 1MB flash device.
 
+config ROM_TABLE_ADDR
+	hex
+	default 0xf0000
+	help
+	  All x86 tables happen to like the address range from 0x0f0000
+	  to 0x100000. We use 0xf0000 as the starting address to store
+	  those tables, including PIRQ routing table, Multi-Processor
+	  table and ACPI table.
+
+config ROM_TABLE_SIZE
+	hex
+	default 0x10000
+
 menu "System tables"
 	depends on !EFI && !SYS_COREBOOT
 

arch/x86/config.mk

@@ -10,8 +10,7 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
 PLATFORM_CPPFLAGS += -fno-strict-aliasing
 PLATFORM_CPPFLAGS += -fomit-frame-pointer
 PF_CPPFLAGS_X86   := $(call cc-option, -fno-toplevel-reorder, \
-		       $(call cc-option, -fno-unit-at-a-time)) \
+		     $(call cc-option, -fno-unit-at-a-time))
-		     $(call cc-option, -mpreferred-stack-boundary=2)
 
 PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86)
 PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
@@ -27,7 +26,7 @@ endif
 ifeq ($(IS_32BIT),y)
 PLATFORM_CPPFLAGS += -march=i386 -m32
 else
-PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common
+PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common -m64
 endif
 
 PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden

arch/x86/cpu/baytrail/Kconfig

@@ -7,7 +7,24 @@
 config INTEL_BAYTRAIL
 	bool
 	select HAVE_FSP if !EFI
+	select ARCH_MISC_INIT if !EFI
+	imply HAVE_INTEL_ME if !EFI
+	imply ENABLE_MRC_CACHE
 	imply ENV_IS_IN_SPI_FLASH
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply INTEL_ICH6_GPIO
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply SCSI
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
+	imply USB_XHCI_HCD
+	imply VIDEO_VESA
 
 if INTEL_BAYTRAIL
 config INTERNAL_UART

arch/x86/cpu/baytrail/valleyview.c

@@ -11,18 +11,6 @@
 #include <asm/mrccache.h>
 #include <asm/post.h>
 
-static struct pci_device_id mmc_supported[] = {
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2 },
-	{},
-};
-
-int cpu_mmc_init(bd_t *bis)
-{
-	return pci_mmc_init("ValleyView SDHCI", mmc_supported);
-}
-
 #ifndef CONFIG_EFI_APP
 int arch_cpu_init(void)
 {

arch/x86/cpu/broadwell/Kconfig

@@ -6,6 +6,18 @@
 config INTEL_BROADWELL
 	bool
 	select CACHE_MRC_BIN
+	select ARCH_EARLY_INIT_R
+	imply HAVE_INTEL_ME
+	imply ENABLE_MRC_CACHE
+	imply ENV_IS_IN_SPI_FLASH
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply INTEL_BROADWELL_GPIO
+	imply SCSI
+	imply SPI_FLASH
+	imply USB
+	imply USB_EHCI_HCD
+	imply VIDEO_BROADWELL_IGD
 
 if INTEL_BROADWELL
 

arch/x86/cpu/broadwell/refcode.c

@@ -56,7 +56,17 @@ struct rmodule_header {
 	uint32_t padding[4];
 } __packed;
 
-int cpu_run_reference_code(void)
+/**
+ * cpu_run_reference_code() - Run the platform reference code
+ *
+ * Some platforms require a binary blob to be executed once SDRAM is
+ * available. This is used to set up various platform features, such as the
+ * platform controller hub (PCH). This function should be implemented by the
+ * CPU-specific code.
+ *
+ * @return 0 on success, -ve on failure
+ */
+static int cpu_run_reference_code(void)
 {
 	struct pei_data _pei_data __aligned(8);
 	struct pei_data *pei_data = &_pei_data;
@@ -111,3 +121,8 @@ int cpu_run_reference_code(void)
 
 	return 0;
 }
+
+int arch_early_init_r(void)
+{
+	return cpu_run_reference_code();
+}

arch/x86/cpu/coreboot/Kconfig

@@ -3,6 +3,20 @@ if TARGET_COREBOOT
 config SYS_COREBOOT
 	bool
 	default y
+	imply ENV_IS_NOWHERE
+	imply AHCI_PCI
+	imply E1000
+	imply ICH_SPI
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
+	imply USB_XHCI_HCD
+	imply VIDEO_COREBOOT
 	imply CMD_CBFS
 	imply FS_CBFS
 

arch/x86/cpu/coreboot/coreboot.c

@@ -29,11 +29,6 @@ int arch_cpu_init(void)
 	return x86_cpu_init_f();
 }
 
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int checkcpu(void)
 {
 	return 0;
@@ -90,8 +85,3 @@ int misc_init_r(void)
 {
 	return 0;
 }
-
-int arch_misc_init(void)
-{
-	return 0;
-}

arch/x86/cpu/efi/efi.c

@@ -13,11 +13,6 @@ int arch_cpu_init(void)
 	return 0;
 }
 
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 int checkcpu(void)
 {
 	return 0;
@@ -36,8 +31,3 @@ int misc_init_r(void)
 {
 	return 0;
 }
-
-int arch_misc_init(void)
-{
-	return 0;
-}

arch/x86/cpu/ivybridge/Kconfig

@@ -8,6 +8,17 @@
 config NORTHBRIDGE_INTEL_IVYBRIDGE
 	bool
 	select CACHE_MRC_BIN if HAVE_MRC
+	imply HAVE_INTEL_ME
+	imply ENABLE_MRC_CACHE
+	imply ENV_IS_IN_SPI_FLASH
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply INTEL_ICH6_GPIO
+	imply SCSI
+	imply SPI_FLASH
+	imply USB
+	imply USB_EHCI_HCD
+	imply VIDEO_VESA
 
 if NORTHBRIDGE_INTEL_IVYBRIDGE
 

arch/x86/cpu/ivybridge/sdram.c

@@ -233,7 +233,6 @@ static int sdram_find(struct udevice *dev)
 	uint32_t tseg_base, uma_size, tolud;
 	uint64_t tom, me_base, touud;
 	uint64_t uma_memory_base = 0;
-	uint64_t uma_memory_size;
 	unsigned long long tomk;
 	uint16_t ggc;
 	u32 val;
@@ -298,7 +297,6 @@ static int sdram_find(struct udevice *dev)
 		tolud += uma_size << 10;
 		/* UMA starts at old TOLUD */
 		uma_memory_base = tomk * 1024ULL;
-		uma_memory_size = uma_size * 1024ULL;
 		debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
 	}
 
@@ -312,13 +310,11 @@ static int sdram_find(struct udevice *dev)
 		debug("%uM UMA", uma_size >> 10);
 		tomk -= uma_size;
 		uma_memory_base = tomk * 1024ULL;
-		uma_memory_size += uma_size * 1024ULL;
 
 		/* GTT Graphics Stolen Memory Size (GGMS) */
 		uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
 		tomk -= uma_size;
 		uma_memory_base = tomk * 1024ULL;
-		uma_memory_size += uma_size * 1024ULL;
 		debug(" and %uM GTT\n", uma_size >> 10);
 	}
 
@@ -327,7 +323,6 @@ static int sdram_find(struct udevice *dev)
 	uma_size = (uma_memory_base - tseg_base) >> 10;
 	tomk -= uma_size;
 	uma_memory_base = tomk * 1024ULL;
-	uma_memory_size += uma_size * 1024ULL;
 	debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
 
 	debug("Available memory below 4GB: %lluM\n", tomk >> 10);

arch/x86/cpu/qemu/Kconfig

@@ -6,6 +6,14 @@
 
 config QEMU
 	bool
+	select ARCH_EARLY_INIT_R
+	imply ENV_IS_NOWHERE
+	imply AHCI_PCI
+	imply E1000
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
+	imply VIDEO_VESA
 
 if QEMU
 

arch/x86/cpu/quark/Kconfig

@@ -7,6 +7,21 @@
 config INTEL_QUARK
 	bool
 	select HAVE_RMU
+	select ARCH_EARLY_INIT_R
+	select ARCH_MISC_INIT
+	imply ENABLE_MRC_CACHE
+	imply ENV_IS_IN_SPI_FLASH
+	imply ETH_DESIGNWARE
+	imply ICH_SPI
+	imply INTEL_ICH6_GPIO
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
 
 if INTEL_QUARK
 

arch/x86/cpu/quark/quark.c

@@ -16,11 +16,6 @@
 #include <asm/arch/msg_port.h>
 #include <asm/arch/quark.h>
 
-static struct pci_device_id mmc_supported[] = {
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
-	{},
-};
-
 static void quark_setup_mtrr(void)
 {
 	u32 base, mask;
@@ -328,11 +323,6 @@ int arch_early_init_r(void)
 	return 0;
 }
 
-int cpu_mmc_init(bd_t *bis)
-{
-	return pci_mmc_init("Quark SDHCI", mmc_supported);
-}
-
 int arch_misc_init(void)
 {
 #ifdef CONFIG_ENABLE_MRC_CACHE

arch/x86/cpu/queensbay/Kconfig

@@ -8,6 +8,22 @@ config INTEL_QUEENSBAY
 	bool
 	select HAVE_FSP
 	select HAVE_CMC
+	select ARCH_EARLY_INIT_R
+	imply ENV_IS_IN_SPI_FLASH
+	imply AHCI_PCI
+	imply ICH_SPI
+	imply INTEL_ICH6_GPIO
+	imply MMC
+	imply MMC_PCI
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply PCH_GBE
+	imply SCSI
+	imply SPI_FLASH
+	imply SYS_NS16550
+	imply USB
+	imply USB_EHCI_HCD
+	imply VIDEO_VESA
 
 if INTEL_QUEENSBAY
 

arch/x86/cpu/queensbay/Makefile

@@ -5,4 +5,4 @@
 #
 
 obj-y += fsp_configs.o irq.o
-obj-y += tnc.o topcliff.o
+obj-y += tnc.o

arch/x86/cpu/queensbay/topcliff.c

@@ -1,20 +0,0 @@
-/*
- * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mmc.h>
-#include <pci_ids.h>
-
-static struct pci_device_id mmc_supported[] = {
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
-	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
-	{},
-};
-
-int cpu_mmc_init(bd_t *bis)
-{
-	return pci_mmc_init("Topcliff SDHCI", mmc_supported);
-}

arch/x86/cpu/tangier/Kconfig

@@ -7,6 +7,14 @@
 config INTEL_TANGIER
 	bool
 	depends on INTEL_MID
+	imply INTEL_MID_SERIAL
+	imply MMC
+	imply MMC_SDHCI
+	imply MMC_SDHCI_SDMA
+	imply MMC_SDHCI_TANGIER
+	imply TANGIER_WATCHDOG
+	imply USB
+	imply USB_DWC3
 
 config SYS_CAR_ADDR
 	hex

arch/x86/include/asm/cpu.h

@@ -288,16 +288,4 @@ u32 cpu_get_family_model(void);
  */
 u32 cpu_get_stepping(void);
 
-/**
- * cpu_run_reference_code() - Run the platform reference code
- *
- * Some platforms require a binary blob to be executed once SDRAM is
- * available. This is used to set up various platform features, such as the
- * platform controller hub (PCH). This function should be implemented by the
- * CPU-specific code.
- *
- * @return 0 on success, -ve on failure
- */
-int cpu_run_reference_code(void);
-
 #endif

arch/x86/include/asm/tables.h

@@ -9,13 +9,8 @@
 
 #include <tables_csum.h>
 
-/*
+#define ROM_TABLE_ADDR	CONFIG_ROM_TABLE_ADDR
- * All x86 tables happen to like the address range from 0xf0000 to 0x100000.
+#define ROM_TABLE_END	(CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1)
- * We use 0xf0000 as the starting address to store those tables, including
- * PIRQ routing table, Multi-Processor table and ACPI table.
- */
-#define ROM_TABLE_ADDR	0xf0000
-#define ROM_TABLE_END	0xfffff
 
 #define ROM_TABLE_ALIGN	1024
 

board/advantech/som-db5800-som-6867/Kconfig

@@ -21,6 +21,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
+	select SPI_FLASH_MACRONIX
 
 config PCIE_ECAM_BASE
 	default 0xe0000000

board/advantech/som-db5800-som-6867/som-db5800-som-6867.c

@@ -17,8 +17,3 @@ int board_early_init_f(void)
 
 	return 0;
 }
-
-int arch_early_init_r(void)
-{
-	return 0;
-}

board/congatec/conga-qeval20-qa3-e3845/Kconfig

@@ -21,7 +21,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
+	select SPI_FLASH_STMICRO
 
 config PCIE_ECAM_BASE
 	default 0xe0000000

board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c

@@ -28,11 +28,6 @@ int board_early_init_f(void)
 	return 0;
 }
 
-int arch_early_init_r(void)
-{
-	return 0;
-}
-
 int board_late_init(void)
 {
 	struct udevice *dev;

board/coreboot/coreboot/Kconfig

@@ -12,6 +12,17 @@ config SYS_SOC
 config SYS_TEXT_BASE
 	default 0x01110000
 
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	imply SPI_FLASH_ATMEL
+	imply SPI_FLASH_EON
+	imply SPI_FLASH_GIGADEVICE
+	imply SPI_FLASH_MACRONIX
+	imply SPI_FLASH_SPANSION
+	imply SPI_FLASH_STMICRO
+	imply SPI_FLASH_SST
+	imply SPI_FLASH_WINBOND
+
 comment "coreboot-specific options"
 
 config SYS_CONFIG_NAME

board/coreboot/coreboot/Makefile

@@ -12,4 +12,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	+= coreboot_start.o coreboot.o
+obj-y	+= coreboot_start.o

board/coreboot/coreboot/coreboot.c

@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2013 Google, Inc
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <cros_ec.h>
-#include <asm/gpio.h>
-
-int arch_early_init_r(void)
-{
-	return 0;
-}

board/dfi/dfi-bt700/Kconfig

@@ -21,7 +21,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
+	select SPI_FLASH_STMICRO
 
 config PCIE_ECAM_BASE
 	default 0xe0000000

board/efi/efi-x86/efi.c

@@ -5,9 +5,3 @@
  */
 
 #include <common.h>
-#include <asm/gpio.h>
-
-int arch_early_init_r(void)
-{
-	return 0;
-}

board/google/chromebook_link/Kconfig

@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select HAVE_INTEL_ME
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
 
 config PCIE_ECAM_BASE
 	default 0xf0000000

board/google/chromebook_link/link.c

@@ -5,19 +5,3 @@
  */
 
 #include <common.h>
-#include <cros_ec.h>
-#include <dm.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <asm/arch/pch.h>
-
-int arch_early_init_r(void)
-{
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	return 0;
-}

board/google/chromebook_samus/Kconfig

@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select INTEL_BROADWELL
 	select HAVE_INTEL_ME
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
 
 config PCIE_ECAM_BASE
 	default 0xf0000000

board/google/chromebook_samus/samus.c

@@ -5,14 +5,3 @@
  */
 
 #include <common.h>
-#include <asm/cpu.h>
-
-int arch_early_init_r(void)
-{
-	return cpu_run_reference_code();
-}
-
-int board_early_init_f(void)
-{
-	return 0;
-}

board/google/chromebox_panther/Kconfig

@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select HAVE_INTEL_ME
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
 
 config SYS_CAR_ADDR
 	hex

board/google/chromebox_panther/panther.c

@@ -5,14 +5,3 @@
  */
 
 #include <common.h>
-#include <asm/arch/pch.h>
-
-int arch_early_init_r(void)
-{
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	return 0;
-}

board/intel/bayleybay/Kconfig

@@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
 
 config PCIE_ECAM_BASE
 	default 0xe0000000

board/intel/cougarcanyon2/Kconfig

@@ -21,5 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select HAVE_FSP
 	select BOARD_ROMSIZE_KB_2048
+	select BOARD_EARLY_INIT_F
+	select SPI_FLASH_WINBOND
 
 endif

board/intel/crownbay/Kconfig

@@ -20,5 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR
 	select INTEL_QUEENSBAY
 	select BOARD_ROMSIZE_KB_1024
+	select BOARD_EARLY_INIT_F
+	select SPI_FLASH_SST
 
 endif

board/intel/galileo/Kconfig

@@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR
 	select INTEL_QUARK
 	select BOARD_ROMSIZE_KB_1024
+	select SPI_FLASH_WINBOND
 
 config SMBIOS_PRODUCT_NAME
 	default "GalileoGen2"

board/intel/galileo/galileo.c

@@ -9,11 +9,6 @@
 #include <asm/arch/device.h>
 #include <asm/arch/quark.h>
 
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 /*
  * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin.
  *

board/intel/minnowmax/Kconfig

@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_STMICRO
 
 config PCIE_ECAM_BASE
 	default 0xe0000000

board/intel/minnowmax/minnowmax.c

@@ -12,11 +12,6 @@
 
 #define GPIO_BANKE_NAME		"gpioe"
 
-int arch_early_init_r(void)
-{
-	return 0;
-}
-
 int misc_init_r(void)
 {
 	struct udevice *dev;

common/Kconfig

@@ -871,7 +871,6 @@ menu "Start-up hooks"
 
 config ARCH_EARLY_INIT_R
 	bool "Call arch-specific init soon after relocation"
-	default y if X86
 	help
 	  With this option U-Boot will call arch_early_init_r() soon after
 	  relocation. Driver model is running by this point, and the cache
@@ -888,7 +887,6 @@ config ARCH_MISC_INIT
 
 config BOARD_EARLY_INIT_F
 	bool "Call board-specific init before relocation"
-	default y if X86
 	help
 	  Some boards need to perform initialisation as soon as possible
 	  after boot. With this option, U-Boot calls board_early_init_f()

configs/bayleybay_defconfig

@@ -3,8 +3,6 @@ CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="bayleybay"
 CONFIG_TARGET_BAYLEYBAY=y
 CONFIG_INTERNAL_UART=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_VGA_BIOS_ADDR=0xfffa0000
@@ -16,9 +14,6 @@ CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_ARCH_EARLY_INIT_R is not set
-CONFIG_ARCH_MISC_INIT=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -43,32 +38,12 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
-CONFIG_SCSI=y
 CONFIG_CPU=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
 CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y

configs/chromebook_link64_defconfig

@@ -11,7 +11,6 @@ CONFIG_VENDOR_GOOGLE=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
 CONFIG_TARGET_CHROMEBOOK_LINK64=y
 CONFIG_DEBUG_UART=y
-CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_HAVE_MRC=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
@@ -19,10 +18,10 @@ CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_CPU_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_NET_SUPPORT=y
 CONFIG_SPL_PCI_SUPPORT=y
@@ -51,43 +50,27 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SPL_DM=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_BLK=y
 CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
 CONFIG_TPM_TIS_LPC=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_VIDEO_IVYBRIDGE_IGD=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_TPM=y

configs/chromebook_link_defconfig

@@ -4,14 +4,12 @@ CONFIG_VENDOR_GOOGLE=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
 CONFIG_TARGET_CHROMEBOOK_LINK=y
 CONFIG_DEBUG_UART=y
-CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_HAVE_MRC=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
@@ -38,39 +36,23 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_BLK=y
 CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
 CONFIG_TPM_TIS_LPC=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_VIDEO_IVYBRIDGE_IGD=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_TPM=y

configs/chromebook_samus_defconfig

@@ -4,14 +4,12 @@ CONFIG_VENDOR_GOOGLE=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
 CONFIG_TARGET_CHROMEBOOK_SAMUS=y
 CONFIG_DEBUG_UART=y
-CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_HAVE_MRC=y
 CONFIG_HAVE_REFCODE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
@@ -38,34 +36,19 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
-CONFIG_SCSI=y
 CONFIG_CPU=y
-CONFIG_INTEL_BROADWELL_GPIO=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
 CONFIG_TPM_TIS_LPC=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
-CONFIG_VIDEO_BROADWELL_IGD=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_TPM=y

configs/chromebox_panther_defconfig

@@ -2,13 +2,11 @@ CONFIG_X86=y
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther"
 CONFIG_TARGET_CHROMEBOX_PANTHER=y
-CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_HAVE_MRC=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
@@ -34,33 +32,16 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
-CONFIG_SCSI=y
-CONFIG_DM_SCSI=y
-CONFIG_BLK=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
 CONFIG_RTL8169=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
 CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
 CONFIG_TPM_TIS_LPC=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_TPM=y

configs/conga-qeval20-qa3-e3845-internal-uart_defconfig

@@ -4,8 +4,6 @@ CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
 CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
 CONFIG_INTERNAL_UART=y
 CONFIG_DEBUG_UART=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
@@ -17,7 +15,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_ARCH_MISC_INIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -43,37 +40,17 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_WINBOND_W83627=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
 CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_114=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y

configs/conga-qeval20-qa3-e3845_defconfig

@@ -3,8 +3,6 @@ CONFIG_VENDOR_CONGATEC=y
 CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
 CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
 CONFIG_DEBUG_UART=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
@@ -16,7 +14,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_ARCH_MISC_INIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -42,37 +39,17 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_INTEL=y
 CONFIG_WINBOND_W83627=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
 CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_114=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y

configs/coreboot-x86_defconfig

@@ -4,9 +4,7 @@ CONFIG_TARGET_COREBOOT=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_NOWHERE=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_IDE=y
@@ -31,25 +29,10 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
 CONFIG_TPM_TIS_LPC=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_COREBOOT=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_TPM=y

configs/cougarcanyon2_defconfig

@@ -2,10 +2,8 @@ CONFIG_X86=y
 CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
 CONFIG_TARGET_COUGARCANYON2=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_ENABLE_MRC_CACHE is not set
-CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_ARCH_EARLY_INIT_R is not set
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -27,18 +25,9 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
-CONFIG_SCSI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
 CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+# CONFIG_VIDEO_VESA is not set

configs/crownbay_defconfig

@@ -8,7 +8,6 @@ CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_FIT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
@@ -33,33 +32,11 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
-CONFIG_SCSI=y
 CONFIG_CPU=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
 CONFIG_E1000=y
-CONFIG_PCH_GBE=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y

configs/dfi-bt700-q7x-151_defconfig

@@ -3,8 +3,6 @@ CONFIG_VENDOR_DFI=y
 CONFIG_DEFAULT_DEVICE_TREE="dfi-bt700-q7x-151"
 CONFIG_TARGET_DFI_BT700=y
 CONFIG_DEBUG_UART=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
@@ -16,7 +14,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_ARCH_EARLY_INIT_R is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -41,36 +38,16 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_NUVOTON_NCT6102D=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
 CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_114=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y

configs/edison_defconfig

@@ -3,8 +3,6 @@ CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="edison"
 CONFIG_TARGET_EDISON=y
 CONFIG_SMP=y
-# CONFIG_ARCH_EARLY_INIT_R is not set
-# CONFIG_BOARD_EARLY_INIT_F is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -25,29 +23,16 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_CPU=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
-CONFIG_MMC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_MMC_SDHCI_TANGIER=y
-CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
-CONFIG_DM_RTC=y
-CONFIG_INTEL_MID_SERIAL=y
-CONFIG_TIMER=y
-CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Intel"
 CONFIG_G_DNL_VENDOR_NUM=0x8087
 CONFIG_G_DNL_PRODUCT_NUM=0x0a99
-CONFIG_TANGIER_WATCHDOG=y
 CONFIG_FAT_WRITE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_SHA1=y

configs/efi-x86_defconfig

@@ -5,10 +5,7 @@ CONFIG_TARGET_EFI=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_ENV_IS_NOWHERE=y
-CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_ARCH_EARLY_INIT_R is not set
-# CONFIG_BOARD_EARLY_INIT_F is not set
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BOOTM is not set
 # CONFIG_CMD_IMLS is not set
@@ -20,7 +17,6 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_NET is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
@@ -30,15 +26,11 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_OF_EMBED=y
-CONFIG_DM_PCI=y
+# CONFIG_DM_ETH is not set
 CONFIG_DEBUG_EFI_CONSOLE=y
 CONFIG_DEBUG_UART_BASE=0
 CONFIG_DEBUG_UART_CLOCK=0
 CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
 CONFIG_EFI=y
 # CONFIG_EFI_LOADER is not set

configs/galileo_defconfig

@@ -2,17 +2,13 @@ CONFIG_X86=y
 CONFIG_VENDOR_INTEL=y
 CONFIG_DEFAULT_DEVICE_TREE="galileo"
 CONFIG_TARGET_GALILEO=y
-CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_CONSOLE_MUX=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_ARCH_MISC_INIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -37,27 +33,9 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_USE_PRIVATE_LIBGCC=y

configs/minnowmax_defconfig

@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
 CONFIG_TARGET_MINNOWMAX=y
 CONFIG_INTERNAL_UART=y
 CONFIG_DEBUG_UART=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
@@ -18,8 +16,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_ARCH_MISC_INIT=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -44,36 +40,14 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
-CONFIG_SCSI=y
 CONFIG_CPU=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
 CONFIG_RTL8169=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
-CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y

configs/qemu-x86_64_defconfig

@@ -5,7 +5,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x1000
 CONFIG_MAX_CPUS=2
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_X86_RUN_64BIT=y
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
@@ -19,9 +18,7 @@ CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_NOWHERE=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_CPU_SUPPORT=y
 CONFIG_SPL_ENV_SUPPORT=y
@@ -51,7 +48,6 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_SPL_DM=y
 CONFIG_REGMAP=y
@@ -59,24 +55,10 @@ CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 CONFIG_CPU=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_111=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y

configs/qemu-x86_defconfig

@@ -8,9 +8,7 @@ CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_NOWHERE=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -35,26 +33,11 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_111=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y

configs/qemu-x86_efi_payload32_defconfig

@@ -5,9 +5,7 @@ CONFIG_SMP=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_NOWHERE=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -32,28 +30,13 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_111=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_EFI=y
 CONFIG_EFI_STUB=y

configs/qemu-x86_efi_payload64_defconfig

@@ -5,9 +5,7 @@ CONFIG_SMP=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_ENV_IS_NOWHERE=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
@@ -33,29 +31,14 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_111=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_EFI=y
 CONFIG_EFI_STUB=y
 CONFIG_EFI_STUB_64BIT=y

configs/som-db5800-som-6867_defconfig

@@ -3,8 +3,6 @@ CONFIG_VENDOR_ADVANTECH=y
 CONFIG_TARGET_SOM_DB5800_SOM_6867=y
 CONFIG_DEFAULT_DEVICE_TREE="baytrail_som-db5800-som-6867"
 CONFIG_DEBUG_UART=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
@@ -16,7 +14,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_ARCH_MISC_INIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -40,31 +37,14 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
-CONFIG_SCSI=y
 CONFIG_CPU=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
 CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
 CONFIG_DEBUG_UART_BASE=0x3f8
 CONFIG_DEBUG_UART_CLOCK=1843200
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y

configs/theadorable-x86-dfi-bt700_defconfig

@@ -2,8 +2,6 @@ CONFIG_X86=y
 CONFIG_VENDOR_DFI=y
 CONFIG_DEFAULT_DEVICE_TREE="theadorable-x86-dfi-bt700"
 CONFIG_TARGET_DFI_BT700=y
-CONFIG_HAVE_INTEL_ME=y
-CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_VGA_BIOS_ADDR=0xfffa0000
@@ -16,7 +14,6 @@ CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
-# CONFIG_ARCH_EARLY_INIT_R is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -41,35 +38,14 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_MAC_PARTITION=y
 CONFIG_ISO_PARTITION=y
 CONFIG_EFI_PARTITION=y
-CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_DM_I2C=y
 CONFIG_NUVOTON_NCT6102D=y
-CONFIG_MMC=y
-CONFIG_MMC_PCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_SDMA=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
 CONFIG_E1000=y
-CONFIG_DM_PCI=y
-CONFIG_DM_RTC=y
-CONFIG_SYS_NS16550=y
-CONFIG_ICH_SPI=y
-CONFIG_TIMER=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_114=y
 CONFIG_CONSOLE_SCROLL_LINES=5
-CONFIG_USE_PRIVATE_LIBGCC=y

drivers/ata/Kconfig

@@ -22,6 +22,12 @@ config SATA
 
 menu "SATA/SCSI device support"
 
+config AHCI_PCI
+	bool "Support for PCI-based AHCI controller"
+	depends on DM_SCSI
+	help
+	  Enables support for the PCI-based AHCI controller.
+
 config SATA_CEVA
 	bool "Ceva Sata controller"
 	depends on AHCI

drivers/ata/Makefile

@@ -7,6 +7,7 @@
 
 obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o
 obj-$(CONFIG_AHCI) += ahci-uclass.o
+obj-$(CONFIG_AHCI_PCI) += ahci-pci.o
 obj-$(CONFIG_SCSI_AHCI) += ahci.o
 obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
 obj-$(CONFIG_FSL_SATA) += fsl_sata.o

drivers/ata/ahci-pci.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <dm.h>
+#include <pci.h>
+
+static int ahci_pci_bind(struct udevice *dev)
+{
+	struct udevice *scsi_dev;
+
+	return ahci_bind_scsi(dev, &scsi_dev);
+}
+
+static int ahci_pci_probe(struct udevice *dev)
+{
+	return ahci_probe_scsi(dev);
+}
+
+static const struct udevice_id ahci_pci_ids[] = {
+	{ .compatible = "ahci-pci" },
+	{ }
+};
+
+U_BOOT_DRIVER(ahci_pci) = {
+	.name	= "ahci_pci",
+	.id	= UCLASS_AHCI,
+	.of_match = ahci_pci_ids,
+	.bind	= ahci_pci_bind,
+	.probe = ahci_pci_probe,
+};
+
+static struct pci_device_id ahci_pci_supported[] = {
+	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) },
+	{},
+};
+
+U_BOOT_PCI_DEVICE(ahci_pci, ahci_pci_supported);

drivers/block/ide.c

@@ -469,7 +469,9 @@ static void atapi_inquiry(struct blk_desc *dev_desc)
 
 	device = dev_desc->devnum;
 	dev_desc->type = DEV_TYPE_UNKNOWN;	/* not yet valid */
+#ifndef CONFIG_BLK
 	dev_desc->block_read = atapi_read;
+#endif
 
 	memset(ccb, 0, sizeof(ccb));
 	memset(iobuf, 0, sizeof(iobuf));

drivers/gpio/Kconfig

@@ -67,6 +67,12 @@ config INTEL_BROADWELL_GPIO
 	  driver from the common Intel ICH6 driver. It supports a total of
 	  95 GPIOs which can be configured from the device tree.
 
+config INTEL_ICH6_GPIO
+	bool "Intel ICH6 compatible legacy GPIO driver"
+	depends on DM_GPIO
+	help
+	  Say yes here to select Intel ICH6 compatible legacy GPIO driver.
+
 config IMX_RGPIO2P
 	bool "i.MX7ULP RGPIO2P driver"
 	depends on DM

drivers/mmc/pci_mmc.c

@@ -6,37 +6,71 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <malloc.h>
+#include <mapmem.h>
 #include <sdhci.h>
 #include <asm/pci.h>
 
-int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported)
+struct pci_mmc_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
+struct pci_mmc_priv {
+	struct sdhci_host host;
+	void *base;
+};
+
+static int pci_mmc_probe(struct udevice *dev)
 {
-	struct sdhci_host *mmc_host;
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
-	u32 iobase;
+	struct pci_mmc_plat *plat = dev_get_platdata(dev);
+	struct pci_mmc_priv *priv = dev_get_priv(dev);
+	struct sdhci_host *host = &priv->host;
+	u32 ioaddr;
 	int ret;
-	int i;
 
-	for (i = 0; ; i++) {
+	dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &ioaddr);
-		struct udevice *dev;
+	host->ioaddr = map_sysmem(ioaddr, 0);
+	host->name = dev->name;
+	ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
+	if (ret)
+		return ret;
+	host->mmc = &plat->mmc;
+	host->mmc->priv = &priv->host;
+	host->mmc->dev = dev;
+	upriv->mmc = host->mmc;
 
-		ret = pci_find_device_id(mmc_supported, i, &dev);
+	return sdhci_probe(dev);
-		if (ret)
-			return ret;
-		mmc_host = malloc(sizeof(struct sdhci_host));
-		if (!mmc_host)
-			return -ENOMEM;
-
-		mmc_host->name = name;
-		dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
-		mmc_host->ioaddr = (void *)(ulong)iobase;
-		mmc_host->quirks = 0;
-		mmc_host->max_clk = 0;
-		ret = add_sdhci(mmc_host, 0, 0);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
 }
+
+static int pci_mmc_bind(struct udevice *dev)
+{
+	struct pci_mmc_plat *plat = dev_get_platdata(dev);
+
+	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
+}
+
+U_BOOT_DRIVER(pci_mmc) = {
+	.name	= "pci_mmc",
+	.id	= UCLASS_MMC,
+	.bind	= pci_mmc_bind,
+	.probe	= pci_mmc_probe,
+	.ops	= &sdhci_ops,
+	.priv_auto_alloc_size = sizeof(struct pci_mmc_priv),
+	.platdata_auto_alloc_size = sizeof(struct pci_mmc_plat),
+};
+
+static struct pci_device_id mmc_supported[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1) },
+	{},
+};
+
+U_BOOT_PCI_DEVICE(pci_mmc, mmc_supported);

drivers/pci/Kconfig

@@ -1,6 +1,6 @@
 menuconfig PCI
 	bool "PCI support"
-	default y if PPC || X86
+	default y if PPC
 	help
 	  Enable support for PCI (Peripheral Interconnect Bus), a type of bus
 	  used on some devices to allow the CPU to communicate with its

drivers/timer/Kconfig

@@ -36,7 +36,6 @@ config SANDBOX_TIMER
 config X86_TSC_TIMER
 	bool "x86 Time-Stamp Counter (TSC) timer support"
 	depends on TIMER && X86
-	default y if X86
 	help
 	  Select this to enable Time-Stamp Counter (TSC) timer for x86.
 

drivers/timer/tsc_timer.c

@@ -11,18 +11,13 @@
 #include <dm.h>
 #include <malloc.h>
 #include <timer.h>
+#include <asm/cpu.h>
 #include <asm/io.h>
 #include <asm/i8254.h>
 #include <asm/ibmpc.h>
 #include <asm/msr.h>
 #include <asm/u-boot-x86.h>
 
-/* CPU reference clock frequency: in KHz */
-#define FREQ_83		83200
-#define FREQ_100	99840
-#define FREQ_133	133200
-#define FREQ_166	166400
-
 #define MAX_NUM_FREQS	8
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -45,17 +40,17 @@ struct freq_desc {
 
 static struct freq_desc freq_desc_tables[] = {
 	/* PNW */
-	{ 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+	{ 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } },
 	/* CLV+ */
-	{ 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
+	{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
-	/* TNG */
+	/* TNG - Intel Atom processor Z3400 series */
-	{ 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
+	{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },
-	/* VLV2 */
+	/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
-	{ 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
+	{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
+	/* ANN - Intel Atom processor Z3500 series */
+	{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
 	/* Ivybridge */
 	{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
-	/* ANN */
-	{ 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
 };
 
 static int match_cpu(u8 family, u8 model)
@@ -76,35 +71,40 @@ static int match_cpu(u8 family, u8 model)
 	(freq_desc_tables[cpu_index].freqs[freq_id])
 
 /*
- * Do MSR calibration only for known/supported CPUs.
+ * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
+ * reliable and the frequency is known (provided by HW).
  *
- * Returns the calibration value or 0 if MSR calibration failed.
+ * On these platforms PIT/HPET is generally not available so calibration won't
+ * work at all and there is no other clocksource to act as a watchdog for the
+ * TSC, so we have no other choice than to trust it.
+ *
+ * Returns the TSC frequency in MHz or 0 if HW does not provide it.
  */
-static unsigned long __maybe_unused try_msr_calibrate_tsc(void)
+static unsigned long __maybe_unused cpu_mhz_from_msr(void)
 {
 	u32 lo, hi, ratio, freq_id, freq;
 	unsigned long res;
 	int cpu_index;
 
+	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
+		return 0;
+
 	cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
 	if (cpu_index < 0)
 		return 0;
 
 	if (freq_desc_tables[cpu_index].msr_plat) {
 		rdmsr(MSR_PLATFORM_INFO, lo, hi);
-		ratio = (lo >> 8) & 0x1f;
+		ratio = (lo >> 8) & 0xff;
 	} else {
 		rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
 		ratio = (hi >> 8) & 0x1f;
 	}
 	debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
 
-	if (!ratio)
-		goto fail;
-
 	if (freq_desc_tables[cpu_index].msr_plat == 2) {
 		/* TODO: Figure out how best to deal with this */
-		freq = FREQ_100;
+		freq = 100000;
 		debug("Using frequency: %u KHz\n", freq);
 	} else {
 		/* Get FSB FREQ ID */
@@ -114,18 +114,12 @@ static unsigned long __maybe_unused try_msr_calibrate_tsc(void)
 		debug("Resolved frequency ID: %u, frequency: %u KHz\n",
 		      freq_id, freq);
 	}
-	if (!freq)
-		goto fail;
 
 	/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
 	res = freq * ratio / 1000;
 	debug("TSC runs at %lu MHz\n", res);
 
 	return res;
-
-fail:
-	debug("Fast TSC calibration using MSR failed\n");
-	return 0;
 }
 
 /*
@@ -347,7 +341,7 @@ static int tsc_timer_probe(struct udevice *dev)
 	if (!uc_priv->clock_rate) {
 		unsigned long fast_calibrate;
 
-		fast_calibrate = try_msr_calibrate_tsc();
+		fast_calibrate = cpu_mhz_from_msr();
 		if (!fast_calibrate) {
 			fast_calibrate = quick_pit_calibrate();
 			if (!fast_calibrate)

include/configs/bayleybay.h

@@ -19,10 +19,6 @@
 					"stdout=serial,vidconsole\0" \
 					"stderr=serial,vidconsole\0"
 
-#define CONFIG_SCSI_DEV_LIST		\
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
 /* Environment configuration */
 #define CONFIG_ENV_SECT_SIZE		0x1000
 #define CONFIG_ENV_OFFSET		0x006ff000

include/configs/conga-qeval20-qa3-e3845.h

@@ -19,10 +19,6 @@
 					"stdout=serial\0" \
 					"stderr=serial\0"
 
-#define CONFIG_SCSI_DEV_LIST		\
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
 #define VIDEO_IO_OFFSET				0
 #define CONFIG_X86EMU_RAW_IO
 

include/configs/cougarcanyon2.h

@@ -17,9 +17,6 @@
 					"stdout=serial,vga\0" \
 					"stderr=serial,vga\0"
 
-#define CONFIG_SCSI_DEV_LIST		\
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-
 /* Environment configuration */
 #define CONFIG_ENV_SECT_SIZE		0x1000
 #define CONFIG_ENV_OFFSET		0x5ff000

include/configs/crownbay.h

@@ -21,9 +21,6 @@
 					"stdout=serial,vidconsole\0" \
 					"stderr=serial,vidconsole\0"
 
-#define CONFIG_SCSI_DEV_LIST		\
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
-
 /* Environment configuration */
 #define CONFIG_ENV_SECT_SIZE		0x1000
 #define CONFIG_ENV_OFFSET		0

include/configs/dfi-bt700.h

@@ -24,10 +24,6 @@
 					"stdout=serial\0" \
 					"stderr=serial\0"
 
-#define CONFIG_SCSI_DEV_LIST		\
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 #define CONFIG_USB_ETHER_SMSC95XX

include/configs/efi-x86.h

@@ -14,7 +14,6 @@
 #undef CONFIG_TPM_TIS_BASE_ADDRESS
 
 #undef CONFIG_SCSI_AHCI
-#undef CONFIG_INTEL_ICH6_GPIO
 #undef CONFIG_USB_EHCI_PCI
 
 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \

include/configs/minnowmax.h

@@ -22,10 +22,6 @@
 					"stderr=vidconsole,serial\0" \
 					"usb_pgood_delay=40\0"
 
-#define CONFIG_SCSI_DEV_LIST		\
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
 #define VIDEO_IO_OFFSET				0
 #define CONFIG_X86EMU_RAW_IO
 

include/configs/qemu-x86.h

@@ -23,11 +23,7 @@
  * ATA/SATA support for QEMU x86 targets
  *   - Only legacy IDE controller is supported for QEMU '-M pc' target
  *   - AHCI controller is supported for QEMU '-M q35' target
- *
- * Default configuraion is to support the QEMU default x86 target
- * Undefine CONFIG_IDE to support q35 target
  */
-#ifdef CONFIG_IDE
 #define CONFIG_SYS_IDE_MAXBUS		2
 #define CONFIG_SYS_IDE_MAXDEVICE	4
 #define CONFIG_SYS_ATA_BASE_ADDR	0
@@ -38,15 +34,6 @@
 #define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
 #define CONFIG_ATAPI
 
-#undef CONFIG_SCSI_AHCI
-#else
-#define CONFIG_SCSI_DEV_LIST		\
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI}
-#endif
-
-/* GPIO is not supported */
-#undef CONFIG_INTEL_ICH6_GPIO
-
 /* SPI is not supported */
 
 #define CONFIG_SPL_FRAMEWORK

include/configs/som-6896.h

@@ -16,9 +16,6 @@
 
 #define CONFIG_MISC_INIT_R
 
-#define CONFIG_SCSI_DEV_LIST	\
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
-
 #define VIDEO_IO_OFFSET			0
 #define CONFIG_X86EMU_RAW_IO
 

include/configs/som-db5800-som-6867.h

@@ -19,10 +19,6 @@
 					"stdout=serial,vidconsole\0" \
 					"stderr=serial,vidconsole\0"
 
-#define CONFIG_SCSI_DEV_LIST		\
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
 #define VIDEO_IO_OFFSET				0
 #define CONFIG_X86EMU_RAW_IO
 

include/configs/x86-chromebook.h

@@ -15,14 +15,6 @@
 #define CONFIG_X86_REFCODE_ADDR			0xffea0000
 #define CONFIG_X86_REFCODE_RUN_ADDR		0
 
-#define CONFIG_SCSI_DEV_LIST	\
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}, \
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
-
 #define CONFIG_PCI_MEM_BUS	0xe0000000
 #define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
 #define CONFIG_PCI_MEM_SIZE	0x10000000

include/configs/x86-common.h

@@ -63,9 +63,6 @@
 
 #define CONFIG_SUPPORT_VFAT
 
-/* x86 GPIOs are accessed through a PCI device */
-#define CONFIG_INTEL_ICH6_GPIO
-
 /*-----------------------------------------------------------------------
  * Command line configuration.
  */

include/mmc.h

@@ -585,18 +585,6 @@ int cpu_mmc_init(bd_t *bis);
 int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
 int mmc_get_env_dev(void);
 
-struct pci_device_id;
-
-/**
- * pci_mmc_init() - set up PCI MMC devices
- *
- * This finds all the matching PCI IDs and sets them up as MMC devices.
- *
- * @name:		Name to use for devices
- * @mmc_supported:	PCI IDs to search for, terminated by {0, 0}
- */
-int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported);
-
 /* Set block count limit because of 16 bit register limit on some hardware*/
 #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535

scripts/config_whitelist.txt

@@ -1154,7 +1154,6 @@ CONFIG_INI_MAX_LINE
 CONFIG_INI_MAX_NAME
 CONFIG_INI_MAX_SECTION
 CONFIG_INTEGRITY
-CONFIG_INTEL_ICH6_GPIO
 CONFIG_INTERRUPTS
 CONFIG_IO
 CONFIG_IO64