mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 21:21:37 +00:00
rockchip: add early uart driver
add early uart driver so we can print debug message in SPL stage Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
2863724831
commit
07d8d35a61
3 changed files with 108 additions and 0 deletions
44
arch/arm/include/asm/arch-rockchip/uart.h
Normal file
44
arch/arm/include/asm/arch-rockchip/uart.h
Normal file
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* (C) Copyright 2015 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_UART_H
|
||||
#define __ASM_ARCH_UART_H
|
||||
struct rk_uart {
|
||||
unsigned int rbr; /* Receive buffer register. */
|
||||
unsigned int ier; /* Interrupt enable register. */
|
||||
unsigned int fcr; /* FIFO control register. */
|
||||
unsigned int lcr; /* Line control register. */
|
||||
unsigned int mcr; /* Modem control register. */
|
||||
unsigned int lsr; /* Line status register. */
|
||||
unsigned int msr; /* Modem status register. */
|
||||
unsigned int scr;
|
||||
unsigned int reserved1[(0x30 - 0x20) / 4];
|
||||
unsigned int srbr[(0x70 - 0x30) / 4];
|
||||
unsigned int far;
|
||||
unsigned int tfr;
|
||||
unsigned int rfw;
|
||||
unsigned int usr;
|
||||
unsigned int tfl;
|
||||
unsigned int rfl;
|
||||
unsigned int srr;
|
||||
unsigned int srts;
|
||||
unsigned int sbcr;
|
||||
unsigned int sdmam;
|
||||
unsigned int sfe;
|
||||
unsigned int srt;
|
||||
unsigned int stet;
|
||||
unsigned int htx;
|
||||
unsigned int dmasa;
|
||||
unsigned int reserver2[(0xf4 - 0xac) / 4];
|
||||
unsigned int cpr;
|
||||
unsigned int ucv;
|
||||
unsigned int ctr;
|
||||
};
|
||||
|
||||
void rk_uart_init(void *base);
|
||||
void print_hex(unsigned int n);
|
||||
void print(char *s);
|
||||
#endif
|
|
@ -10,5 +10,6 @@ else
|
|||
obj-y += board.o
|
||||
endif
|
||||
obj-y += rk_timer.o
|
||||
obj-y += rk_early_print.o
|
||||
obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
|
||||
|
|
63
arch/arm/mach-rockchip/rk_early_print.c
Normal file
63
arch/arm/mach-rockchip/rk_early_print.c
Normal file
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* (C) Copyright 2015 Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/uart.h>
|
||||
#include <common.h>
|
||||
|
||||
static struct rk_uart *uart_ptr;
|
||||
|
||||
static void uart_wrtie_byte(char byte)
|
||||
{
|
||||
writel(byte, &uart_ptr->rbr);
|
||||
while (!(readl(&uart_ptr->lsr) & 0x40))
|
||||
;
|
||||
}
|
||||
|
||||
void print(char *s)
|
||||
{
|
||||
while (*s) {
|
||||
if (*s == '\n')
|
||||
uart_wrtie_byte('\r');
|
||||
uart_wrtie_byte(*s);
|
||||
s++;
|
||||
}
|
||||
}
|
||||
|
||||
void print_hex(unsigned int n)
|
||||
{
|
||||
int i;
|
||||
int temp;
|
||||
|
||||
uart_wrtie_byte('0');
|
||||
uart_wrtie_byte('x');
|
||||
|
||||
for (i = 8; i > 0; i--) {
|
||||
temp = (n >> (i - 1) * 4) & 0x0f;
|
||||
if (temp < 10)
|
||||
uart_wrtie_byte((char)(temp + '0'));
|
||||
else
|
||||
uart_wrtie_byte((char)(temp - 10 + 'a'));
|
||||
}
|
||||
uart_wrtie_byte('\n');
|
||||
uart_wrtie_byte('\r');
|
||||
}
|
||||
|
||||
/*
|
||||
* TODO: since rk3036 only 4K sram to use in SPL, for saving space,
|
||||
* we implement uart driver this way, we should convert this to use
|
||||
* ns16550 driver in future, which support DEBUG_UART in the standard way
|
||||
*/
|
||||
void rk_uart_init(void *base)
|
||||
{
|
||||
uart_ptr = (struct rk_uart *)base;
|
||||
writel(0x83, &uart_ptr->lcr);
|
||||
writel(0x0d, &uart_ptr->rbr);
|
||||
writel(0x03, &uart_ptr->lcr);
|
||||
|
||||
/* fifo enable, sfe is shadow register of FCR[0] */
|
||||
writel(0x01, &uart_ptr->sfe);
|
||||
}
|
Loading…
Add table
Reference in a new issue