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Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
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commit
0aa88c8266
3 changed files with 34 additions and 3 deletions
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@ -52,7 +52,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
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if (*reg == id) {
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fdt_setprop_string(blob, off, "status", "okay");
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} else {
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u32 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
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u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
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val = cpu_to_fdt32(val);
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fdt_setprop_string(blob, off, "status",
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"disabled");
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@ -65,6 +65,9 @@ void get_sys_info (sys_info_t * sysInfo)
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int get_clocks (void)
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{
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sys_info_t sys_info;
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#ifdef CONFIG_MPC8544
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volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR;
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#endif
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#if defined(CONFIG_CPM2)
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volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR;
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uint sccr, dfbrg;
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@ -78,8 +81,34 @@ int get_clocks (void)
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gd->cpu_clk = sys_info.freqProcessor;
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gd->bus_clk = sys_info.freqSystemBus;
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gd->mem_clk = sys_info.freqDDRBus;
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/*
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* The base clock for I2C depends on the actual SOC. Unfortunately,
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* there is no pattern that can be used to determine the frequency, so
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* the only choice is to look up the actual SOC number and use the value
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* for that SOC. This information is taken from application note
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* AN2919.
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*/
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#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
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defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
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gd->i2c1_clk = sys_info.freqSystemBus;
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gd->i2c2_clk = sys_info.freqSystemBus;
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#elif defined(CONFIG_MPC8544)
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/*
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* On the 8544, the I2C clock is the same as the SEC clock. This can be
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* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
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* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
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* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
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* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
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*/
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if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
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gd->i2c1_clk = sys_info.freqSystemBus / 3;
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else
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gd->i2c1_clk = sys_info.freqSystemBus / 2;
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#else
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/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
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gd->i2c1_clk = sys_info.freqSystemBus / 2;
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#endif
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gd->i2c2_clk = gd->i2c1_clk;
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#if defined(CONFIG_CPM2)
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gd->vco_out = 2*sys_info.freqSystemBus;
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@ -1570,7 +1570,9 @@ typedef struct ccsr_gur {
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#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
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#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
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uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
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char res1[12];
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uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */
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#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020
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char res1[8];
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uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
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char res2[12];
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uint gpiocr; /* 0xe0030 - GPIO control register */
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