mirror of
https://github.com/Fishwaldo/u-boot.git
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powerpc: mpc8xx: remove stxxtc board support
This board has been orphaned for a while and old enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
62d636aa2a
commit
0ace4d9d8f
13 changed files with 2 additions and 1383 deletions
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@ -74,9 +74,6 @@ config TARGET_ELPT860
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config TARGET_UC100
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config TARGET_UC100
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bool "Support uc100"
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bool "Support uc100"
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config TARGET_STXXTC
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bool "Support stxxtc"
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config TARGET_FPS850L
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config TARGET_FPS850L
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bool "Support FPS850L"
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bool "Support FPS850L"
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@ -153,7 +150,6 @@ source "board/netvia/Kconfig"
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source "board/r360mpi/Kconfig"
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source "board/r360mpi/Kconfig"
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source "board/sixnet/Kconfig"
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source "board/sixnet/Kconfig"
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source "board/spd8xx/Kconfig"
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source "board/spd8xx/Kconfig"
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source "board/stx/stxxtc/Kconfig"
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source "board/svm_sc8xx/Kconfig"
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source "board/svm_sc8xx/Kconfig"
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source "board/tqc/tqm8xx/Kconfig"
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source "board/tqc/tqm8xx/Kconfig"
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@ -1,15 +0,0 @@
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if TARGET_STXXTC
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config SYS_BOARD
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string
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default "stxxtc"
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config SYS_VENDOR
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string
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default "stx"
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config SYS_CONFIG_NAME
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string
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default "stxxtc"
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endif
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@ -1,6 +0,0 @@
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STXXTC BOARD
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M: Dan Malek <dan@embeddedalley.com>
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S: Orphan (since 2014-06)
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F: board/stx/stxxtc/
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F: include/configs/stxxtc.h
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F: configs/stxxtc_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = stxxtc.o
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@ -1,59 +0,0 @@
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First, some build notes on the Silicon Turnkey eXpress XTc.
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This board has both 87x/88x procesor options at various
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frequencies. The configuration file has some macros for setting
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the clock speed, not all have been tested. They all have
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a 10MHz input clock. Please do not check in a configuration
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file that selects a high speed not available on all processors.
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We chose the 66MHz core and bus speed, which should be OK on
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all boards. If you have a processor, lucky you! :-)
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Just build a new configuration with that speed, check
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the macro configuration to ensure it's correct. If the
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macro is updated, please check that in, but keep default
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processor speed.
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The board is likely to have more than 1Mbyte of NOR boot flash.
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It was also configured with a high boot vector (Dan's fault)
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so the standard 8xx mapping doesn't work well. We had to move
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the addresses around a little bit so one copy would work. The
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flash got fragmented, and we are working on a better solution.
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There is an "xtc.cfg" floating around for the BDI2000, use
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that for programming a new version of U-Boot. You can probably
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find it on the Silicon Turnkey eXpress (www.silicontkx.com),
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Embedded Alley Solutions (embeddedalley.com), or Denx (denx.de)
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servers.
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The board will also have various SDRAM sizes, but the code
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should automatically determine the amount of memory.
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There are a couple of different board versions, visually
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they use different BGA or surface mount memory parts. However,
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they are logically the same board.
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Now, some operational notes.
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The board has the option of sporting two FEC Ethernet ports.
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The second port isn't configured to be automatically available
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because it would cause U-Boot to generate a board data structure
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(the bd_t) with multiple MAC addresses and be incompatible with
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standard 8xx kernel builds. You can use/test the second FEC
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in U-Boot by assigning an 'eth1addr' and selecting the second
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FEC as the port to use.
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Since this is just a development board and not a product, STx
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does not assign unique MAC addresses. We just pilfer the
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"default" ones used by Wolfgang on some other boards. Please
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ensure you assign unique MAC addresses when using these boards.
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The serial port baud rate is 38400, because that's the way
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I like it :-)
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Thanks to Pantelis for lots of the work on this board port.
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Have Fun!
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-- Dan
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15 August 2005
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@ -1,592 +0,0 @@
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/*
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* (C) Copyright 2000-2004
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* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* (C) Copyright 2005
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* Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* U-Boot port on STx XTc board
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* Mostly copied from Netta
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*/
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#include <common.h>
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#include <miiphy.h>
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#include "mpc8xx.h"
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#ifdef CONFIG_HW_WATCHDOG
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#include <watchdog.h>
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#endif
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/****************************************************************/
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/* some sane bit macros */
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#define _BD(_b) (1U << (31-(_b)))
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#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
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#define _BW(_b) (1U << (15-(_b)))
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#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
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#define _BB(_b) (1U << (7-(_b)))
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#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
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#define _B(_b) _BD(_b)
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#define _BR(_l, _h) _BDR(_l, _h)
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/****************************************************************/
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/*
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* Check Board Identity:
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*
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* Return 1 always.
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*/
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int checkboard(void)
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{
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printf ("Silicon Turnkey eXpress XTc\n");
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return (0);
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}
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/****************************************************************/
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#define _NOT_USED_ 0xFFFFFFFF
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/****************************************************************/
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#define CS_0000 0x00000000
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#define CS_0001 0x10000000
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#define CS_0010 0x20000000
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#define CS_0011 0x30000000
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#define CS_0100 0x40000000
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#define CS_0101 0x50000000
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#define CS_0110 0x60000000
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#define CS_0111 0x70000000
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#define CS_1000 0x80000000
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#define CS_1001 0x90000000
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#define CS_1010 0xA0000000
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#define CS_1011 0xB0000000
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#define CS_1100 0xC0000000
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#define CS_1101 0xD0000000
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#define CS_1110 0xE0000000
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#define CS_1111 0xF0000000
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#define BS_0000 0x00000000
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#define BS_0001 0x01000000
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#define BS_0010 0x02000000
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#define BS_0011 0x03000000
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#define BS_0100 0x04000000
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#define BS_0101 0x05000000
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#define BS_0110 0x06000000
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#define BS_0111 0x07000000
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#define BS_1000 0x08000000
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#define BS_1001 0x09000000
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#define BS_1010 0x0A000000
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#define BS_1011 0x0B000000
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#define BS_1100 0x0C000000
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#define BS_1101 0x0D000000
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#define BS_1110 0x0E000000
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#define BS_1111 0x0F000000
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#define GPL0_AAAA 0x00000000
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#define GPL0_AAA0 0x00200000
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#define GPL0_AAA1 0x00300000
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#define GPL0_000A 0x00800000
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#define GPL0_0000 0x00A00000
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#define GPL0_0001 0x00B00000
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#define GPL0_111A 0x00C00000
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#define GPL0_1110 0x00E00000
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#define GPL0_1111 0x00F00000
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#define GPL1_0000 0x00000000
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#define GPL1_0001 0x00040000
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#define GPL1_1110 0x00080000
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#define GPL1_1111 0x000C0000
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#define GPL2_0000 0x00000000
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#define GPL2_0001 0x00010000
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#define GPL2_1110 0x00020000
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#define GPL2_1111 0x00030000
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#define GPL3_0000 0x00000000
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#define GPL3_0001 0x00004000
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#define GPL3_1110 0x00008000
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#define GPL3_1111 0x0000C000
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#define GPL4_0000 0x00000000
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#define GPL4_0001 0x00001000
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#define GPL4_1110 0x00002000
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#define GPL4_1111 0x00003000
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#define GPL5_0000 0x00000000
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#define GPL5_0001 0x00000400
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#define GPL5_1110 0x00000800
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#define GPL5_1111 0x00000C00
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#define LOOP 0x00000080
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#define EXEN 0x00000040
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#define AMX_COL 0x00000000
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#define AMX_ROW 0x00000020
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#define AMX_MAR 0x00000030
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#define NA 0x00000008
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#define UTA 0x00000004
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#define TODT 0x00000002
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#define LAST 0x00000001
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#define A10_AAAA GPL0_AAAA
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#define A10_AAA0 GPL0_AAA0
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#define A10_AAA1 GPL0_AAA1
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#define A10_000A GPL0_000A
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#define A10_0000 GPL0_0000
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#define A10_0001 GPL0_0001
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#define A10_111A GPL0_111A
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#define A10_1110 GPL0_1110
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#define A10_1111 GPL0_1111
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#define RAS_0000 GPL1_0000
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#define RAS_0001 GPL1_0001
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#define RAS_1110 GPL1_1110
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#define RAS_1111 GPL1_1111
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#define CAS_0000 GPL2_0000
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#define CAS_0001 GPL2_0001
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#define CAS_1110 GPL2_1110
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#define CAS_1111 GPL2_1111
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#define WE_0000 GPL3_0000
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#define WE_0001 GPL3_0001
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#define WE_1110 GPL3_1110
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#define WE_1111 GPL3_1111
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/* #define CAS_LATENCY 3 */
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#define CAS_LATENCY 2
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const uint sdram_table[0x40] = {
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#if CAS_LATENCY == 3
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/* RSS */
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CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
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CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
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CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
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_NOT_USED_, _NOT_USED_,
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/* RBS */
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CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
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CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
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CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* WSS */
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CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
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CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
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CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/* WBS */
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CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
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CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
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CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
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CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
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CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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#endif
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#if CAS_LATENCY == 2
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/* RSS */
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CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
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CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
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CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
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CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
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CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
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_NOT_USED_,
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|
||||||
_NOT_USED_, _NOT_USED_,
|
|
||||||
|
|
||||||
/* RBS */
|
|
||||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
|
|
||||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
|
|
||||||
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
|
|
||||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
|
|
||||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
|
|
||||||
CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
|
|
||||||
CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
|
|
||||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
|
|
||||||
_NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
|
|
||||||
/* WSS */
|
|
||||||
CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
|
|
||||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
|
|
||||||
CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
|
|
||||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
|
|
||||||
_NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_,
|
|
||||||
|
|
||||||
/* WBS */
|
|
||||||
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
|
|
||||||
CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
|
|
||||||
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
|
|
||||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
|
|
||||||
CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
|
|
||||||
CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
|
|
||||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
|
|
||||||
_NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_,
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* UPT */
|
|
||||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
|
|
||||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
|
|
||||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
|
|
||||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
|
|
||||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
|
|
||||||
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_,
|
|
||||||
|
|
||||||
/* EXC */
|
|
||||||
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
|
|
||||||
_NOT_USED_,
|
|
||||||
|
|
||||||
/* REG */
|
|
||||||
CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
|
|
||||||
CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
|
|
||||||
};
|
|
||||||
|
|
||||||
static const uint nandcs_table[0x40] = {
|
|
||||||
/* RSS */
|
|
||||||
CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
|
|
||||||
CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
|
|
||||||
CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
|
|
||||||
CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
|
|
||||||
CS_0000 | GPL4_0000 | GPL5_1111,
|
|
||||||
CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
|
|
||||||
CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
|
|
||||||
CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
|
|
||||||
|
|
||||||
/* RBS */
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
|
|
||||||
/* WSS */
|
|
||||||
CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
|
|
||||||
CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
|
|
||||||
CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
|
|
||||||
CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
|
|
||||||
CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
|
|
||||||
CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
|
|
||||||
CS_0000 | GPL4_1111 | GPL5_1111,
|
|
||||||
CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
|
|
||||||
|
|
||||||
/* WBS */
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
|
|
||||||
/* UPT */
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
|
|
||||||
/* EXC */
|
|
||||||
CS_0001 | LAST,
|
|
||||||
_NOT_USED_,
|
|
||||||
|
|
||||||
/* REG */
|
|
||||||
CS_1110 ,
|
|
||||||
CS_0001 | LAST,
|
|
||||||
};
|
|
||||||
|
|
||||||
/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
|
|
||||||
/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
|
|
||||||
#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
|
|
||||||
|
|
||||||
/* 9 */
|
|
||||||
#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
|
||||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
|
||||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
|
||||||
|
|
||||||
void check_ram(unsigned int addr, unsigned int size)
|
|
||||||
{
|
|
||||||
unsigned int i, j, v, vv;
|
|
||||||
volatile unsigned int *p;
|
|
||||||
unsigned int pv;
|
|
||||||
|
|
||||||
p = (unsigned int *)addr;
|
|
||||||
pv = (unsigned int)p;
|
|
||||||
for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
|
|
||||||
*p++ = pv;
|
|
||||||
|
|
||||||
p = (unsigned int *)addr;
|
|
||||||
for (i = 0; i < size / sizeof(unsigned int); i++) {
|
|
||||||
v = (unsigned int)p;
|
|
||||||
vv = *p;
|
|
||||||
if (vv != v) {
|
|
||||||
printf("%p: read %08x instead of %08x\n", p, vv, v);
|
|
||||||
hang();
|
|
||||||
}
|
|
||||||
p++;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (j = 0; j < 5; j++) {
|
|
||||||
switch (j) {
|
|
||||||
case 0: v = 0x00000000; break;
|
|
||||||
case 1: v = 0xffffffff; break;
|
|
||||||
case 2: v = 0x55555555; break;
|
|
||||||
case 3: v = 0xaaaaaaaa; break;
|
|
||||||
default:v = 0xdeadbeef; break;
|
|
||||||
}
|
|
||||||
p = (unsigned int *)addr;
|
|
||||||
for (i = 0; i < size / sizeof(unsigned int); i++) {
|
|
||||||
*p = v;
|
|
||||||
vv = *p;
|
|
||||||
if (vv != v) {
|
|
||||||
printf("%p: read %08x instead of %08x\n", p, vv, v);
|
|
||||||
hang();
|
|
||||||
}
|
|
||||||
*p = ~v;
|
|
||||||
p++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0)
|
|
||||||
|
|
||||||
phys_size_t initdram(int board_type)
|
|
||||||
{
|
|
||||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
|
||||||
long int size;
|
|
||||||
u32 d1, d2;
|
|
||||||
|
|
||||||
upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Preliminary prescaler for refresh
|
|
||||||
*/
|
|
||||||
memctl->memc_mptpr = MPTPR_PTP_DIV8;
|
|
||||||
|
|
||||||
memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Map controller bank 3 to the SDRAM bank at preliminary address.
|
|
||||||
*/
|
|
||||||
memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
|
|
||||||
memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
|
|
||||||
|
|
||||||
memctl->memc_mamr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */
|
|
||||||
|
|
||||||
udelay(200);
|
|
||||||
|
|
||||||
/* perform SDRAM initialisation sequence */
|
|
||||||
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
|
|
||||||
udelay(1);
|
|
||||||
|
|
||||||
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
|
|
||||||
udelay(1);
|
|
||||||
|
|
||||||
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
|
|
||||||
udelay(1);
|
|
||||||
|
|
||||||
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
|
|
||||||
|
|
||||||
udelay(10000);
|
|
||||||
|
|
||||||
|
|
||||||
d1 = 0xAA55AA55;
|
|
||||||
*(volatile u32 *)0 = d1;
|
|
||||||
d2 = *(volatile u32 *)0;
|
|
||||||
if (d1 != d2) {
|
|
||||||
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
|
|
||||||
DO_LOOP;
|
|
||||||
}
|
|
||||||
|
|
||||||
d1 = 0x55AA55AA;
|
|
||||||
*(volatile u32 *)0 = d1;
|
|
||||||
d2 = *(volatile u32 *)0;
|
|
||||||
if (d1 != d2) {
|
|
||||||
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
|
|
||||||
DO_LOOP;
|
|
||||||
}
|
|
||||||
|
|
||||||
d1 = 0x12345678;
|
|
||||||
*(volatile u32 *)0 = d1;
|
|
||||||
d2 = *(volatile u32 *)0;
|
|
||||||
if (d1 != d2) {
|
|
||||||
printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
|
|
||||||
DO_LOOP;
|
|
||||||
}
|
|
||||||
|
|
||||||
size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
|
|
||||||
|
|
||||||
return size;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
void reset_phys(void)
|
|
||||||
{
|
|
||||||
int phyno;
|
|
||||||
unsigned short v;
|
|
||||||
|
|
||||||
udelay(10000);
|
|
||||||
/* reset the damn phys */
|
|
||||||
mii_init();
|
|
||||||
|
|
||||||
for (phyno = 0; phyno < 32; ++phyno) {
|
|
||||||
miiphy_read("FEC", phyno, MII_PHYSID1, &v);
|
|
||||||
if (v == 0xFFFF)
|
|
||||||
continue;
|
|
||||||
miiphy_write("FEC", phyno, MII_BMCR, BMCR_PDOWN);
|
|
||||||
udelay(10000);
|
|
||||||
miiphy_write("FEC", phyno, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
|
|
||||||
udelay(10000);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
/* GP = general purpose, SP = special purpose (on chip peripheral) */
|
|
||||||
|
|
||||||
/* bits that can have a special purpose or can be configured as inputs/outputs */
|
|
||||||
#define PA_GP_INMASK _BW(6)
|
|
||||||
#define PA_GP_OUTMASK (_BW(7))
|
|
||||||
#define PA_SP_MASK 0
|
|
||||||
#define PA_ODR_VAL 0
|
|
||||||
#define PA_GP_OUTVAL (_BW(7))
|
|
||||||
#define PA_SP_DIRVAL 0
|
|
||||||
|
|
||||||
#define PB_GP_INMASK 0
|
|
||||||
#define PB_GP_OUTMASK (_B(23))
|
|
||||||
#define PB_SP_MASK 0
|
|
||||||
#define PB_ODR_VAL 0
|
|
||||||
#define PB_GP_OUTVAL (_B(23))
|
|
||||||
#define PB_SP_DIRVAL 0
|
|
||||||
|
|
||||||
#define PC_GP_INMASK 0
|
|
||||||
#define PC_GP_OUTMASK (_BW(15))
|
|
||||||
|
|
||||||
#define PC_SP_MASK 0
|
|
||||||
#define PC_SOVAL 0
|
|
||||||
#define PC_INTVAL 0
|
|
||||||
#define PC_GP_OUTVAL 0
|
|
||||||
#define PC_SP_DIRVAL 0
|
|
||||||
|
|
||||||
#define PE_GP_INMASK 0
|
|
||||||
#define PE_GP_OUTMASK 0
|
|
||||||
#define PE_GP_OUTVAL 0
|
|
||||||
|
|
||||||
#define PE_SP_MASK 0
|
|
||||||
#define PE_ODR_VAL 0
|
|
||||||
#define PE_SP_DIRVAL 0
|
|
||||||
|
|
||||||
int board_early_init_f(void)
|
|
||||||
{
|
|
||||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
|
||||||
volatile iop8xx_t *ioport = &immap->im_ioport;
|
|
||||||
volatile cpm8xx_t *cpm = &immap->im_cpm;
|
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
|
||||||
|
|
||||||
(void)ioport;
|
|
||||||
(void)cpm;
|
|
||||||
#if 1
|
|
||||||
/* NAND chip select */
|
|
||||||
upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
|
|
||||||
memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
|
|
||||||
memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB);
|
|
||||||
memctl->memc_mbmr = 0; /* all clear */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
memctl->memc_br5 &= ~BR_V;
|
|
||||||
memctl->memc_br6 &= ~BR_V;
|
|
||||||
memctl->memc_br7 &= ~BR_V;
|
|
||||||
|
|
||||||
#if 1
|
|
||||||
ioport->iop_padat = PA_GP_OUTVAL;
|
|
||||||
ioport->iop_paodr = PA_ODR_VAL;
|
|
||||||
ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
|
|
||||||
ioport->iop_papar = PA_SP_MASK;
|
|
||||||
|
|
||||||
cpm->cp_pbdat = PB_GP_OUTVAL;
|
|
||||||
cpm->cp_pbodr = PB_ODR_VAL;
|
|
||||||
cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
|
|
||||||
cpm->cp_pbpar = PB_SP_MASK;
|
|
||||||
|
|
||||||
ioport->iop_pcdat = PC_GP_OUTVAL;
|
|
||||||
ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
|
|
||||||
ioport->iop_pcso = PC_SOVAL;
|
|
||||||
ioport->iop_pcint = PC_INTVAL;
|
|
||||||
ioport->iop_pcpar = PC_SP_MASK;
|
|
||||||
|
|
||||||
cpm->cp_pedat = PE_GP_OUTVAL;
|
|
||||||
cpm->cp_peodr = PE_ODR_VAL;
|
|
||||||
cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
|
|
||||||
cpm->cp_pepar = PE_SP_MASK;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
void hw_watchdog_reset(void)
|
|
||||||
{
|
|
||||||
/* XXX add here the really funky stuff */
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
|
|
||||||
int overwrite_console(void)
|
|
||||||
{
|
|
||||||
/* printf("overwrite_console called\n"); */
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
extern int drv_phone_init(void);
|
|
||||||
extern int drv_phone_use_me(void);
|
|
||||||
extern int drv_phone_is_idle(void);
|
|
||||||
|
|
||||||
int misc_init_r(void)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int last_stage_init(void)
|
|
||||||
{
|
|
||||||
reset_phys();
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
@ -1,82 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2000-2010
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
OUTPUT_ARCH(powerpc)
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
/* Read-only sections, merged into text segment: */
|
|
||||||
. = + SIZEOF_HEADERS;
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
arch/powerpc/cpu/mpc8xx/start.o (.text*)
|
|
||||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
|
|
||||||
|
|
||||||
*(.text*)
|
|
||||||
}
|
|
||||||
_etext = .;
|
|
||||||
PROVIDE (etext = .);
|
|
||||||
.rodata :
|
|
||||||
{
|
|
||||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */
|
|
||||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
|
||||||
_erotext = .;
|
|
||||||
PROVIDE (erotext = .);
|
|
||||||
.reloc :
|
|
||||||
{
|
|
||||||
_GOT2_TABLE_ = .;
|
|
||||||
KEEP(*(.got2))
|
|
||||||
KEEP(*(.got))
|
|
||||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
|
|
||||||
_FIXUP_TABLE_ = .;
|
|
||||||
KEEP(*(.fixup))
|
|
||||||
}
|
|
||||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
|
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
|
||||||
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(.data*)
|
|
||||||
*(.sdata*)
|
|
||||||
}
|
|
||||||
_edata = .;
|
|
||||||
PROVIDE (edata = .);
|
|
||||||
|
|
||||||
. = .;
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
.u_boot_list : {
|
|
||||||
KEEP(*(SORT(.u_boot_list*)));
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
. = .;
|
|
||||||
__start___ex_table = .;
|
|
||||||
__ex_table : { *(__ex_table) }
|
|
||||||
__stop___ex_table = .;
|
|
||||||
|
|
||||||
. = ALIGN(256);
|
|
||||||
__init_begin = .;
|
|
||||||
.text.init : { *(.text.init) }
|
|
||||||
.data.init : { *(.data.init) }
|
|
||||||
. = ALIGN(256);
|
|
||||||
__init_end = .;
|
|
||||||
|
|
||||||
__bss_start = .;
|
|
||||||
.bss (NOLOAD) :
|
|
||||||
{
|
|
||||||
*(.bss*)
|
|
||||||
*(.sbss*)
|
|
||||||
*(COMMON)
|
|
||||||
. = ALIGN(4);
|
|
||||||
}
|
|
||||||
__bss_end = . ;
|
|
||||||
PROVIDE (end = .);
|
|
||||||
}
|
|
||||||
|
|
@ -1,121 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2000-2004
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
OUTPUT_ARCH(powerpc)
|
|
||||||
/* Do we need any of these for elf?
|
|
||||||
__DYNAMIC = 0; */
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
/* Read-only sections, merged into text segment: */
|
|
||||||
. = + SIZEOF_HEADERS;
|
|
||||||
.interp : { *(.interp) }
|
|
||||||
.hash : { *(.hash) }
|
|
||||||
.dynsym : { *(.dynsym) }
|
|
||||||
.dynstr : { *(.dynstr) }
|
|
||||||
.rel.text : { *(.rel.text) }
|
|
||||||
.rela.text : { *(.rela.text) }
|
|
||||||
.rel.data : { *(.rel.data) }
|
|
||||||
.rela.data : { *(.rela.data) }
|
|
||||||
.rel.rodata : { *(.rel.rodata) }
|
|
||||||
.rela.rodata : { *(.rela.rodata) }
|
|
||||||
.rel.got : { *(.rel.got) }
|
|
||||||
.rela.got : { *(.rela.got) }
|
|
||||||
.rel.ctors : { *(.rel.ctors) }
|
|
||||||
.rela.ctors : { *(.rela.ctors) }
|
|
||||||
.rel.dtors : { *(.rel.dtors) }
|
|
||||||
.rela.dtors : { *(.rela.dtors) }
|
|
||||||
.rel.bss : { *(.rel.bss) }
|
|
||||||
.rela.bss : { *(.rela.bss) }
|
|
||||||
.rel.plt : { *(.rel.plt) }
|
|
||||||
.rela.plt : { *(.rela.plt) }
|
|
||||||
.init : { *(.init) }
|
|
||||||
.plt : { *(.plt) }
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
/* WARNING - the following is hand-optimized to fit within */
|
|
||||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
|
||||||
|
|
||||||
arch/powerpc/cpu/mpc8xx/start.o (.text)
|
|
||||||
common/dlmalloc.o (.text)
|
|
||||||
lib/vsprintf.o (.text)
|
|
||||||
lib/crc32.o (.text)
|
|
||||||
|
|
||||||
. = env_offset;
|
|
||||||
common/env_embedded.o(.text)
|
|
||||||
|
|
||||||
*(.text)
|
|
||||||
*(.got1)
|
|
||||||
}
|
|
||||||
_etext = .;
|
|
||||||
PROVIDE (etext = .);
|
|
||||||
.rodata :
|
|
||||||
{
|
|
||||||
*(.rodata)
|
|
||||||
*(.rodata1)
|
|
||||||
*(.rodata.str1.4)
|
|
||||||
*(.eh_frame)
|
|
||||||
}
|
|
||||||
.fini : { *(.fini) } =0
|
|
||||||
.ctors : { *(.ctors) }
|
|
||||||
.dtors : { *(.dtors) }
|
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */
|
|
||||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
|
||||||
_erotext = .;
|
|
||||||
PROVIDE (erotext = .);
|
|
||||||
.reloc :
|
|
||||||
{
|
|
||||||
*(.got)
|
|
||||||
_GOT2_TABLE_ = .;
|
|
||||||
*(.got2)
|
|
||||||
_FIXUP_TABLE_ = .;
|
|
||||||
*(.fixup)
|
|
||||||
}
|
|
||||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
|
||||||
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(.data)
|
|
||||||
*(.data1)
|
|
||||||
*(.sdata)
|
|
||||||
*(.sdata2)
|
|
||||||
*(.dynamic)
|
|
||||||
CONSTRUCTORS
|
|
||||||
}
|
|
||||||
_edata = .;
|
|
||||||
PROVIDE (edata = .);
|
|
||||||
|
|
||||||
|
|
||||||
. = ALIGN(4);
|
|
||||||
.u_boot_list : {
|
|
||||||
KEEP(*(SORT(.u_boot_list*)));
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
__start___ex_table = .;
|
|
||||||
__ex_table : { *(__ex_table) }
|
|
||||||
__stop___ex_table = .;
|
|
||||||
|
|
||||||
. = ALIGN(4096);
|
|
||||||
__init_begin = .;
|
|
||||||
.text.init : { *(.text.init) }
|
|
||||||
.data.init : { *(.data.init) }
|
|
||||||
. = ALIGN(4096);
|
|
||||||
__init_end = .;
|
|
||||||
|
|
||||||
__bss_start = .;
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
*(.sbss) *(.scommon)
|
|
||||||
*(.dynbss)
|
|
||||||
*(.bss)
|
|
||||||
*(COMMON)
|
|
||||||
}
|
|
||||||
__bss_end = . ;
|
|
||||||
PROVIDE (end = .);
|
|
||||||
}
|
|
||||||
|
|
@ -1,3 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_8xx=y
|
|
||||||
CONFIG_TARGET_STXXTC=y
|
|
||||||
|
|
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
||||||
|
|
||||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||||
=================================================================================================
|
=================================================================================================
|
||||||
|
stxxtc powerpc mpc8xx - - Dan Malek <dan@embeddedalley.com>
|
||||||
omap5912osk arm arm926ejs - - Rishi Bhattacharya <rishi@ti.com>
|
omap5912osk arm arm926ejs - - Rishi Bhattacharya <rishi@ti.com>
|
||||||
p1023rds powerpc mpc85xx d0bc5140 2014-07-22 Roy Zang <tie-fei.zang@freescale.com>
|
p1023rds powerpc mpc85xx d0bc5140 2014-07-22 Roy Zang <tie-fei.zang@freescale.com>
|
||||||
spc1920 powerpc mpc8xx 98ad54be 2014-07-07
|
spc1920 powerpc mpc8xx 98ad54be 2014-07-07
|
||||||
|
|
|
||||||
|
|
@ -32,10 +32,7 @@ typedef volatile unsigned char vu_char;
|
||||||
defined(CONFIG_MPC866) || \
|
defined(CONFIG_MPC866) || \
|
||||||
defined(CONFIG_MPC866P)
|
defined(CONFIG_MPC866P)
|
||||||
# define CONFIG_MPC866_FAMILY 1
|
# define CONFIG_MPC866_FAMILY 1
|
||||||
#elif defined(CONFIG_MPC870) \
|
#elif defined(CONFIG_MPC885)
|
||||||
|| defined(CONFIG_MPC875) \
|
|
||||||
|| defined(CONFIG_MPC880) \
|
|
||||||
|| defined(CONFIG_MPC885)
|
|
||||||
# define CONFIG_MPC885_FAMILY 1
|
# define CONFIG_MPC885_FAMILY 1
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_MPC860) \
|
#if defined(CONFIG_MPC860) \
|
||||||
|
|
|
||||||
|
|
@ -1,485 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2000-2004
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
|
|
||||||
* U-Boot port on STx XTc 8xx board
|
|
||||||
* Mostly copied from Panto's NETTA2 board.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options
|
|
||||||
* (easy to change)
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_MPC875 1 /* This is a MPC875 CPU */
|
|
||||||
#define CONFIG_STXXTC 1 /* ...on a STx XTc board */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x40F00000
|
|
||||||
|
|
||||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
|
||||||
#undef CONFIG_8xx_CONS_SMC2
|
|
||||||
#undef CONFIG_8xx_CONS_NONE
|
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */
|
|
||||||
|
|
||||||
#define CONFIG_XIN 10000000 /* 10 MHz input xtal */
|
|
||||||
|
|
||||||
/* Select one of few clock rates defined later in this file.
|
|
||||||
*/
|
|
||||||
/* #define MPC8XX_HZ 50000000 */
|
|
||||||
#define MPC8XX_HZ 66666666
|
|
||||||
|
|
||||||
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
|
||||||
#else
|
|
||||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
|
|
||||||
|
|
||||||
#undef CONFIG_BOOTARGS
|
|
||||||
#define CONFIG_BOOTCOMMAND \
|
|
||||||
"tftpboot; " \
|
|
||||||
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
|
|
||||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
|
|
||||||
"bootm"
|
|
||||||
|
|
||||||
#define CONFIG_SOURCE
|
|
||||||
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
|
|
||||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
|
||||||
|
|
||||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
|
||||||
|
|
||||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
|
|
||||||
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options
|
|
||||||
*/
|
|
||||||
#define CONFIG_BOOTP_SUBNETMASK
|
|
||||||
#define CONFIG_BOOTP_GATEWAY
|
|
||||||
#define CONFIG_BOOTP_HOSTNAME
|
|
||||||
#define CONFIG_BOOTP_BOOTPATH
|
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
||||||
#define CONFIG_BOOTP_NISDOMAIN
|
|
||||||
|
|
||||||
|
|
||||||
#undef CONFIG_MAC_PARTITION
|
|
||||||
#undef CONFIG_DOS_PARTITION
|
|
||||||
|
|
||||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
|
|
||||||
|
|
||||||
#define FEC_ENET 1 /* eth.c needs it that way... */
|
|
||||||
#undef CONFIG_SYS_DISCOVER_PHY
|
|
||||||
#define CONFIG_MII 1
|
|
||||||
#define CONFIG_MII_INIT 1
|
|
||||||
#undef CONFIG_RMII
|
|
||||||
|
|
||||||
#define CONFIG_ETHER_ON_FEC1 1
|
|
||||||
#define CONFIG_FEC1_PHY 1 /* phy address of FEC */
|
|
||||||
#undef CONFIG_FEC1_PHY_NORXERR
|
|
||||||
|
|
||||||
#define CONFIG_ETHER_ON_FEC2 1
|
|
||||||
#define CONFIG_FEC2_PHY 3
|
|
||||||
#undef CONFIG_FEC2_PHY_NORXERR
|
|
||||||
|
|
||||||
#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration.
|
|
||||||
*/
|
|
||||||
#include <config_cmd_default.h>
|
|
||||||
|
|
||||||
#define CONFIG_CMD_DHCP
|
|
||||||
#define CONFIG_CMD_MII
|
|
||||||
#define CONFIG_CMD_NFS
|
|
||||||
#define CONFIG_CMD_PING
|
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_BOARD_EARLY_INIT_F 1
|
|
||||||
#define CONFIG_MISC_INIT_R
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
|
||||||
#define CONFIG_SYS_PROMPT "xtc> " /* Monitor Command Prompt */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_HUSH_PARSER 1
|
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
|
||||||
#endif
|
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
|
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Low Level Configuration Settings
|
|
||||||
* (address mappings, register initial values, etc.)
|
|
||||||
* You should know what you are doing if you make changes here.
|
|
||||||
*/
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Internal Memory Mapped Register
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_IMMR 0xFF000000
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Start addresses for the final memory configuration
|
|
||||||
* (Set up by the startup code)
|
|
||||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0x40000000
|
|
||||||
#if defined(DEBUG)
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* yes this is weird, I know :) */
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE | 0x00F00000)
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_RESET_ADDRESS 0x80000000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data
|
|
||||||
* have to be in the first 8 MB of memory, since this is
|
|
||||||
* the maximum mapped by the Linux kernel during initialization.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* FLASH organization
|
|
||||||
*/
|
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
|
||||||
|
|
||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
|
|
||||||
#define CONFIG_ENV_OFFSET 0
|
|
||||||
#define CONFIG_ENV_SIZE 0x4000
|
|
||||||
|
|
||||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x00010000)
|
|
||||||
#define CONFIG_ENV_OFFSET_REDUND 0
|
|
||||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_CFI 1
|
|
||||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
|
||||||
#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 }
|
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_PROTECTION
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Cache Configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SYPCR - System Protection Control 11-9
|
|
||||||
* SYPCR can only be written once after reset!
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_WATCHDOG)
|
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
|
||||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SIUMCR - SIU Module Configuration 11-6
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* PCMCIA config., multi-function pin tri-state
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* TBSCR - Time Base Status and Control 11-26
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
|
||||||
* interrupt status bit
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if CONFIG_XIN == 10000000
|
|
||||||
|
|
||||||
#if MPC8XX_HZ == 50000000
|
|
||||||
#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
|
|
||||||
(1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
|
|
||||||
PLPRCR_TEXPS)
|
|
||||||
#elif MPC8XX_HZ == 66666666
|
|
||||||
#define CONFIG_SYS_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
|
|
||||||
(1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
|
|
||||||
PLPRCR_TEXPS)
|
|
||||||
#else
|
|
||||||
#error unsupported CPU freq for XIN = 10MHz
|
|
||||||
#endif
|
|
||||||
#else
|
|
||||||
#error unsupported freq for XIN (must be 10MHz)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* SCCR - System Clock and reset Control Register 15-27
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* Set clock output, timebase and RTC source and divider,
|
|
||||||
* power management and some other internal clocks
|
|
||||||
*
|
|
||||||
* Note: When TBS == 0 the timebase is independent of current cpu clock.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define SCCR_MASK SCCR_EBDF11
|
|
||||||
#if MPC8XX_HZ > 66666666
|
|
||||||
#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
|
|
||||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
|
||||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
|
||||||
SCCR_DFALCD00 | SCCR_EBDF01)
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
|
|
||||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
|
||||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
|
||||||
SCCR_DFALCD00)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
/*#define CONFIG_SYS_DER 0x2002000F*/
|
|
||||||
#define CONFIG_SYS_DER 0
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Init Memory Controller:
|
|
||||||
*
|
|
||||||
* BR0/1 and OR0/1 (FLASH)
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
|
||||||
#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */
|
|
||||||
|
|
||||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
|
||||||
* restrict access enough to keep SRAM working (if any)
|
|
||||||
* but not too much to meddle with FLASH accesses
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000
|
|
||||||
#define CONFIG_SYS_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
|
|
||||||
|
|
||||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
|
|
||||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
|
||||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
|
||||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
|
||||||
|
|
||||||
#define CONFIG_SYS_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH)
|
|
||||||
#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR4 and OR4 (SDRAM)
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
|
|
||||||
#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
|
|
||||||
|
|
||||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
|
||||||
#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
|
|
||||||
#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory Periodic Timer Prescaler
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory Periodic Timer Prescaler
|
|
||||||
*
|
|
||||||
* The Divider for PTA (refresh timer) configuration is based on an
|
|
||||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to
|
|
||||||
* the number of chip selects (NCS) and the actually needed refresh
|
|
||||||
* rate is done by setting MPTPR.
|
|
||||||
*
|
|
||||||
* PTA is calculated from
|
|
||||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
|
|
||||||
*
|
|
||||||
* gclk CPU clock (not bus clock!)
|
|
||||||
* Trefresh Refresh cycle * 4 (four word bursts used)
|
|
||||||
*
|
|
||||||
* 4096 Rows from SDRAM example configuration
|
|
||||||
* 1000 factor s -> ms
|
|
||||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
|
|
||||||
* 4 Number of refresh cycles per period
|
|
||||||
* 64 Refresh cycle in ms per number of rows
|
|
||||||
* --------------------------------------------
|
|
||||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
|
|
||||||
*
|
|
||||||
* 50 MHz => 50.000.000 / Divider = 98
|
|
||||||
* 66 Mhz => 66.000.000 / Divider = 129
|
|
||||||
* 80 Mhz => 80.000.000 / Divider = 156
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MAMR_PTA 234
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For 16 MBit, refresh rates could be 31.3 us
|
|
||||||
* (= 64 ms / 2K = 125 / quad bursts).
|
|
||||||
* For a simpler initialization, 15.6 us is used instead.
|
|
||||||
*
|
|
||||||
* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
|
|
||||||
* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
|
||||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
|
||||||
|
|
||||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
|
||||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
|
||||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* MAMR settings for SDRAM
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* 8 column SDRAM */
|
|
||||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
|
||||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
|
||||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
|
||||||
|
|
||||||
/* 9 column SDRAM */
|
|
||||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
|
||||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
|
||||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
|
||||||
|
|
||||||
#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
|
|
||||||
|
|
||||||
/****************************************************************/
|
|
||||||
|
|
||||||
#define NAND_SIZE 0x00010000 /* 64K */
|
|
||||||
#define NAND_BASE 0xF1000000
|
|
||||||
|
|
||||||
/*****************************************************************************/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DIRECT_FLASH_TFTP
|
|
||||||
|
|
||||||
/*****************************************************************************/
|
|
||||||
|
|
||||||
/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
|
|
||||||
* CxOE and CxRESET. We use the CxOE.
|
|
||||||
*/
|
|
||||||
#define STATUS_LED_BIT 0x00000080 /* bit 24 */
|
|
||||||
|
|
||||||
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
|
|
||||||
#define STATUS_LED_STATE STATUS_LED_BLINKING
|
|
||||||
|
|
||||||
#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
|
|
||||||
#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
|
||||||
|
|
||||||
/* LEDs */
|
|
||||||
|
|
||||||
/* led_id_t is unsigned int mask */
|
|
||||||
typedef unsigned int led_id_t;
|
|
||||||
|
|
||||||
#define __led_toggle(_msk) \
|
|
||||||
do { \
|
|
||||||
((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
#define __led_set(_msk, _st) \
|
|
||||||
do { \
|
|
||||||
if ((_st)) \
|
|
||||||
((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
|
|
||||||
else \
|
|
||||||
((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
|
|
||||||
} while(0)
|
|
||||||
|
|
||||||
#define __led_init(msk, st) __led_set(msk, st)
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/******************************************************************************/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
|
|
||||||
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
|
|
||||||
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
|
|
||||||
|
|
||||||
/******************************************************************************/
|
|
||||||
|
|
||||||
/* use board specific hardware */
|
|
||||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
|
|
||||||
/*****************************************************************************/
|
|
||||||
|
|
||||||
#define CONFIG_AUTO_COMPLETE 1
|
|
||||||
#define CONFIG_CRC32_VERIFY 1
|
|
||||||
#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
|
|
||||||
|
|
||||||
/*****************************************************************************/
|
|
||||||
|
|
||||||
/* pass open firmware flattened device tree */
|
|
||||||
#define CONFIG_OF_LIBFDT 1
|
|
||||||
|
|
||||||
#define OF_TBCLK (MPC8XX_HZ / 16)
|
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
|
||||||
|
|
@ -231,10 +231,6 @@ void status_led_set (int led, int state);
|
||||||
|
|
||||||
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
||||||
|
|
||||||
/***** STx XTc ********************************************************/
|
|
||||||
#elif defined(CONFIG_STXXTC)
|
|
||||||
/* XXX empty just to avoid the error */
|
|
||||||
/************************************************************************/
|
|
||||||
#elif defined(CONFIG_V38B)
|
#elif defined(CONFIG_V38B)
|
||||||
|
|
||||||
# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */
|
# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue