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drivers: pci: add map_bar support for Enhanced Allocation
Makes dm_pci_map_bar API available for integrated PCI devices that support Enhanced Allocation instead of the original PCI BAR mechanism. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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2 changed files with 59 additions and 0 deletions
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@ -1341,10 +1341,56 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
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return bus_addr;
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}
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static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
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int ea_off)
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{
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int ea_cnt, i, entry_size;
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int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
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u32 ea_entry;
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phys_addr_t addr;
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/* EA capability structure header */
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dm_pci_read_config32(dev, ea_off, &ea_entry);
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ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
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ea_off += PCI_EA_FIRST_ENT;
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for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
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/* Entry header */
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dm_pci_read_config32(dev, ea_off, &ea_entry);
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entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
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if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
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continue;
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/* Base address, 1st DW */
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dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
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addr = ea_entry & PCI_EA_FIELD_MASK;
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if (ea_entry & PCI_EA_IS_64) {
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/* Base address, 2nd DW, skip over 4B MaxOffset */
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dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
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addr |= ((u64)ea_entry) << 32;
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}
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/* size ignored for now */
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return map_physmem(addr, flags, 0);
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}
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return 0;
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}
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void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
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{
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pci_addr_t pci_bus_addr;
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u32 bar_response;
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int ea_off;
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/*
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* if the function supports Enhanced Allocation use that instead of
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* BARs
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*/
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ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
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if (ea_off)
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return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
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/* read BAR address */
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dm_pci_read_config32(dev, bar, &bar_response);
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@ -455,6 +455,17 @@
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#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
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#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
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/* Enhanced Allocation Registers */
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#define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */
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#define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */
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#define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */
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#define PCI_EA_ES 0x00000007 /* Entry Size */
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#define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
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/* Base, MaxOffset registers */
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/* bit 0 is reserved */
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#define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
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#define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
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/* Include the ID list */
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#include <pci_ids.h>
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@ -1312,6 +1323,8 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
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* that corresponds to it.
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* Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
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* type 1 functions.
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* Can also be used on type 0 functions that support Enhanced Allocation for
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* 32b/64b BARs. Note that duplicate BEI entries are not supported.
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*
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* @dev: Device to check
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* @bar: Bar register offset (PCI_BASE_ADDRESS_...)
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