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Merge branch 'master' of http://git.denx.de/u-boot-sunxi
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commit
0b6699ad8e
8 changed files with 111 additions and 15 deletions
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@ -248,6 +248,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
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sun8i-h3-orangepi-lite.dtb \
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sun8i-h3-orangepi-one.dtb \
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sun8i-h3-orangepi-pc.dtb \
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sun8i-h3-orangepi-pc-plus.dtb \
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sun8i-h3-orangepi-plus.dtb
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dtb-$(CONFIG_MACH_SUN50I) += \
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sun50i-a64-pine64-plus.dtb \
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87
arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts
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87
arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts
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@ -0,0 +1,87 @@
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/*
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* Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/* The Orange Pi PC Plus is an extended version of the regular PC */
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#include "sun8i-h3-orangepi-pc.dts"
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/ {
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model = "Xunlong Orange Pi PC / PC Plus";
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aliases {
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/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
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ethernet1 = &rtl8189ftv;
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};
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};
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins_a>;
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vmmc-supply = <®_vcc3v3>;
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bus-width = <4>;
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non-removable;
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status = "okay";
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/*
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* Explicitly define the sdio device, so that we can add an ethernet
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* alias for it (which e.g. makes u-boot set a mac-address).
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*/
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rtl8189ftv: sdio_wifi@1 {
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reg = <1>;
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};
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};
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&mmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc2_8bit_pins>;
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vmmc-supply = <®_vcc3v3>;
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bus-width = <8>;
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non-removable;
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cap-mmc-hw-reset;
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status = "okay";
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};
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&mmc2_8bit_pins {
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/* Increase drive strength for DDR modes */
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allwinner,drive = <SUN4I_PINCTRL_40_MA>;
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/* eMMC is missing pull-ups */
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allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
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};
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@ -48,6 +48,10 @@
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/ {
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interrupt-parent = <&gic>;
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aliases {
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ethernet0 = <&emac>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -59,6 +59,7 @@ F: configs/orangepi_2_defconfig
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F: configs/orangepi_lite_defconfig
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F: configs/orangepi_one_defconfig
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F: configs/orangepi_pc_defconfig
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F: configs/orangepi_pc_plus_defconfig
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F: configs/orangepi_plus_defconfig
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F: configs/polaroid_mid2407pxe03_defconfig
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F: configs/polaroid_mid2809pxe04_defconfig
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@ -5,7 +5,6 @@ CONFIG_DRAM_CLK=624
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CONFIG_DRAM_ZQ=3881979
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CONFIG_DRAM_ODT_EN=y
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CONFIG_MMC0_CD_PIN="PF6"
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CONFIG_MMC_SUNXI_SLOT_EXTRA=2
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# CONFIG_VIDEO is not set
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CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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@ -15,4 +14,3 @@ CONFIG_SPL=y
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# CONFIG_CMD_FPGA is not set
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CONFIG_SY8106A_POWER=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_SUN8I_EMAC=y
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17
configs/orangepi_pc_plus_defconfig
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17
configs/orangepi_pc_plus_defconfig
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@ -0,0 +1,17 @@
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CONFIG_ARM=y
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CONFIG_ARCH_SUNXI=y
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CONFIG_MACH_SUN8I_H3=y
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CONFIG_DRAM_CLK=624
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CONFIG_DRAM_ZQ=3881979
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CONFIG_DRAM_ODT_EN=y
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CONFIG_MMC0_CD_PIN="PF6"
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CONFIG_MMC_SUNXI_SLOT_EXTRA=2
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# CONFIG_VIDEO is not set
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CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc-plus"
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_SPL=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FPGA is not set
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CONFIG_SY8106A_POWER=y
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CONFIG_USB_EHCI_HCD=y
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@ -10,4 +10,3 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FPGA is not set
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CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
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CONFIG_SUN8I_EMAC=y
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@ -22,10 +22,6 @@
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#include <miiphy.h>
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#include <net.h>
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#define SCTL_EMAC_TX_CLK_SRC_MII BIT(0)
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#define SCTL_EMAC_EPIT_MII BIT(2)
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#define SCTL_EMAC_CLK_SEL BIT(18) /* 25 Mhz */
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#define MDIO_CMD_MII_BUSY BIT(0)
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#define MDIO_CMD_MII_WRITE BIT(1)
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@ -589,9 +585,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
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/* Set clock gating for ephy */
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setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
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/* Set Tx clock source as MII with rate 25 MZ */
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setbits_le32(priv->sysctl_reg, SCTL_EMAC_TX_CLK_SRC_MII |
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SCTL_EMAC_EPIT_MII | SCTL_EMAC_CLK_SEL);
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/* Deassert EPHY */
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setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
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}
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@ -599,9 +592,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
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/* Set clock gating for emac */
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setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
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/* Set EMAC clock */
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setbits_le32(&ccm->axi_gate, (BIT(1) | BIT(0)));
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/* De-assert EMAC */
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setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
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}
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@ -696,12 +686,11 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
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priv->mac_reg = (void *)pdata->iobase;
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sun8i_emac_board_setup(priv);
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sun8i_emac_set_syscon(priv);
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sun8i_mdio_init(dev->name, priv);
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priv->bus = miiphy_get_dev_by_name(dev->name);
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sun8i_emac_set_syscon(priv);
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return sun8i_phy_init(priv, dev);
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}
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