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https://github.com/Fishwaldo/u-boot.git
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x86: Add LAPIC setup code
Add code to set up the Local Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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b636dd1079
commit
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4 changed files with 181 additions and 2 deletions
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@ -15,5 +15,6 @@ obj-y += interrupts.o cpu.o call64.o
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obj-$(CONFIG_SYS_COREBOOT) += coreboot/
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obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
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obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
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obj-y += lapic.o
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obj-$(CONFIG_PCI) += pci.o
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obj-y += turbo.o
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57
arch/x86/cpu/lapic.c
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57
arch/x86/cpu/lapic.c
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@ -0,0 +1,57 @@
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/*
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* From coreboot file of same name
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/msr.h>
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#include <asm/io.h>
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#include <asm/lapic.h>
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#include <asm/post.h>
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void lapic_setup(void)
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{
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#if NEED_LAPIC == 1
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/* Only Pentium Pro and later have those MSR stuff */
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debug("Setting up local apic: ");
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/* Enable the local apic */
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enable_lapic();
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/*
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* Set Task Priority to 'accept all'.
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*/
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lapic_write_around(LAPIC_TASKPRI,
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lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
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/* Put the local apic in virtual wire mode */
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lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) &
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~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
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lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_EXTINT));
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lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_NMI));
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debug("apic_id: 0x%02lx, ", lapicid());
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#else /* !NEED_LLAPIC */
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/* Only Pentium Pro and later have those MSR stuff */
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debug("Disabling local apic: ");
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disable_lapic();
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#endif /* !NEED_LAPIC */
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debug("done.\n");
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post_code(POST_LAPIC);
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}
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@ -14,6 +14,13 @@
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#include <asm/msr.h>
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#include <asm/processor.h>
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/* See if I need to initialize the local apic */
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#if CONFIG_SMP || CONFIG_IOAPIC
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# define NEED_LAPIC 1
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#else
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# define NEED_LAPIC 0
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#endif
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static inline __attribute__((always_inline))
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unsigned long lapic_read(unsigned long reg)
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{
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@ -37,8 +44,9 @@ static inline void enable_lapic(void)
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msr = msr_read(LAPIC_BASE_MSR);
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msr.hi &= 0xffffff00;
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msr.lo &= 0x000007ff;
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msr.lo |= LAPIC_DEFAULT_BASE | (1 << 11);
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msr.lo |= LAPIC_BASE_MSR_ENABLE;
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msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
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msr.lo |= LAPIC_DEFAULT_BASE;
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msr_write(LAPIC_BASE_MSR, msr);
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}
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@ -56,4 +64,116 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
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return lapic_read(LAPIC_ID) >> 24;
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}
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#if !CONFIG_AP_IN_SIPI_WAIT
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/* If we need to go back to sipi wait, we use the long non-inlined version of
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* this function in lapic_cpu_init.c
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*/
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static inline __attribute__((always_inline)) void stop_this_cpu(void)
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{
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/* Called by an AP when it is ready to halt and wait for a new task */
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for (;;)
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cpu_hlt();
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}
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#else
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void stop_this_cpu(void);
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#endif
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#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
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sizeof(*(ptr))))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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/*
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument. --ANK
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
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int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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: "=q" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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: "=r" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %0,%1"
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: "=r" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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}
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return x;
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}
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static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
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{
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(void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
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}
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#ifdef X86_GOOD_APIC
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# define FORCE_READ_AROUND_WRITE 0
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# define lapic_read_around(x) lapic_read(x)
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# define lapic_write_around(x, y) lapic_write((x), (y))
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#else
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# define FORCE_READ_AROUND_WRITE 1
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# define lapic_read_around(x) lapic_read(x)
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# define lapic_write_around(x, y) lapic_write_atomic((x), (y))
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#endif
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static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
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{
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int timeout;
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unsigned long status;
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int result;
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lapic_wait_icr_idle();
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lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
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lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
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timeout = 0;
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do {
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status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
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} while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
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result = -1;
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if (status == LAPIC_ICR_RR_VALID) {
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*pvalue = lapic_read(LAPIC_RRR);
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result = 0;
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}
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return result;
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}
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void lapic_setup(void);
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#if CONFIG_SMP
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struct device;
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int start_cpu(struct device *cpu);
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#endif /* CONFIG_SMP */
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int boot_cpu(void);
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/**
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* struct x86_cpu_priv - Information about a single CPU
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*
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* @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
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* just a number representing the CPU core
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*
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* TODO: Move this to driver model once lifecycle is understood
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*/
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struct x86_cpu_priv {
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int apic_id;
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int start_err;
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};
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#endif
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@ -30,6 +30,7 @@
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#define POST_PRE_MRC 0x2e
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#define POST_MRC 0x2f
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#define POST_DRAM 0x2f
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#define POST_LAPIC 0x30
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#define POST_RAM_FAILURE 0xea
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