Merge git://git.denx.de/u-boot-riscv

1. Improve cache implementation.
2. Fix and improve standalone applications
This commit is contained in:
Tom Rini 2019-01-15 22:05:05 -05:00
commit 0cd35f3920
7 changed files with 49 additions and 56 deletions

View file

@ -1,40 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2017 Andes Technology Corporation
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
*/
OUTPUT_ARCH(riscv)
ENTRY(_start)
SECTIONS
{
. = ALIGN(4);
.text :
{
*(.text)
}
. = ALIGN(4);
.data : {
__global_pointer$ = . + 0x800;
*(.data)
}
. = ALIGN(4);
.got : {
__got_start = .;
*(.got)
__got_end = .;
}
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
__bss_end = .;
. = ALIGN(4);
.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
_end = .;
}

View file

@ -174,16 +174,27 @@ gd_t *global_data;
: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "$r16");
#elif defined(CONFIG_RISCV)
/*
* t7 holds the pointer to the global_data. gp is call clobbered.
* gp holds the pointer to the global_data. t0 is call clobbered.
*/
#ifdef CONFIG_ARCH_RV64I
#define EXPORT_FUNC(f, a, x, ...) \
asm volatile ( \
" .globl " #x "\n" \
#x ":\n" \
" lw x19, %0(gp)\n" \
" lw x19, %1(x19)\n" \
" jr x19\n" \
: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "x19");
" ld t0, %0(gp)\n" \
" ld t0, %1(t0)\n" \
" jr t0\n" \
: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t0");
#else
#define EXPORT_FUNC(f, a, x, ...) \
asm volatile ( \
" .globl " #x "\n" \
#x ":\n" \
" lw t0, %0(gp)\n" \
" lw t0, %1(t0)\n" \
" jr t0\n" \
: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t0");
#endif
#elif defined(CONFIG_ARC)
/*
* r25 holds the pointer to the global_data. r10 is call clobbered.