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driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controller

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fsl_pci_init_port can be called from board specific PCI initialization
routines to setup the PCI (or PCIe) controller.  This will reduce code
redundancy in most of the 85xx/86xx FSL board ports that setup PCI.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Poonam Aggrwal 2009-08-21 07:29:42 +05:30 • committed by Kumar Gala
parent 05f6f66474
commit 0d3d68b25a
2 changed files with 70 additions and 0 deletions
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44
drivers/pci/fsl_pci_init.c
View file

@ -412,6 +412,50 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
} }
} }
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
struct pci_controller *hose, int busno)
{
volatile ccsr_fsl_pci_t *pci;
struct pci_region *r;
pci = (ccsr_fsl_pci_t *) pci_info->regs;
/* on non-PCIe controllers we don't have pme_msg_det so this code
* should do nothing since the read will return 0
*/
if (in_be32(&pci->pme_msg_det)) {
out_be32(&pci->pme_msg_det, 0xffffffff);
debug (" with errors. Clearing. Now 0x%08x",
pci->pme_msg_det);
}
r = hose->regions + hose->region_count;
/* outbound memory */
pci_set_region(r++,
pci_info->mem_bus,
pci_info->mem_phys,
pci_info->mem_size,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
pci_info->io_bus,
pci_info->io_phys,
pci_info->io_size,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
printf("\n PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
hose->first_busno, hose->last_busno);
return(hose->last_busno + 1);
}
/* Enable inbound PCI config cycles for agent/endpoint interface */ /* Enable inbound PCI config cycles for agent/endpoint interface */
void fsl_pci_config_unlock(struct pci_controller *hose) void fsl_pci_config_unlock(struct pci_controller *hose)
{ {

26
include/asm-ppc/fsl_pci.h
View file

@ -154,4 +154,30 @@ typedef struct ccsr_pci {
char res24[252]; char res24[252];
} ccsr_fsl_pci_t; } ccsr_fsl_pci_t;
struct fsl_pci_info {
unsigned long regs;
pci_addr_t mem_bus;
phys_size_t mem_phys;
pci_size_t mem_size;
pci_addr_t io_bus;
phys_size_t io_phys;
pci_size_t io_size;
int pci_num;
};
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
struct pci_controller *hose, int busno);
#define SET_STD_PCIE_INFO(x, num) \
{ \
x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
x.pci_num = num; \
}
#endif #endif