mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-06-14 18:51:41 +00:00
- FIP Enable OP-TEE and TZC support in SPL for STM32MP15 SoC
- Add stm32mp15 missing SPI clock support - Manage pull-up on gpio button STM32MP15 boards - Correct STM32MP15 boot when TAMPER registers are invalid - Fix EMMC pinmux on STM32MP15 Avenger96 board -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEE56Yx6b9SnloYCWtD4rK92eCqk3UFAmD/z+kACgkQ4rK92eCq k3XItwgAsxKApUm59qU9kKagLWb6MOpGft7JnM3aSWbKBEIDbyzEs9OiCsLiicPL B660CW3UuihQsenKh0YcjB92QMtvSL3PiAw7c8cipqJmwfj2DsxP1TUptLqX3JWv tiRyOajXczW6jkxbfHnsAjPVo6+aZp0FKDDpf0zCl8eplk9SFZyr2BttofxiFhUP 5koQFTCbDohMFs069tnkH3MyUDeEdkn/e6vpKEr20eIjc2kiwP8J8FHUVEu7wsl9 lEXdaelPQVkFnKcWBlKIrDnmo2VaQYu/D8OjgCNPeT1UuVttvtEmy7S1hS4jDjeE Swr0h25k405/zVLgjmCTvAC7yyKyxw== =KTkX -----END PGP SIGNATURE----- Merge tag 'u-boot-stm32-20210727' of https://source.denx.de/u-boot/custodians/u-boot-stm - FIP Enable OP-TEE and TZC support in SPL for STM32MP15 SoC - Add stm32mp15 missing SPI clock support - Manage pull-up on gpio button STM32MP15 boards - Correct STM32MP15 boot when TAMPER registers are invalid - Fix EMMC pinmux on STM32MP15 Avenger96 board
This commit is contained in:
Tom Rini
commit
0d4823fbeb
14 changed files with 310 additions and 9 deletions
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@ -17,8 +17,8 @@
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u-boot,error-led = "error";
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u-boot,mmc-env-partition = "ssbl";
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st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
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st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
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st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
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st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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};
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firmware {
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@ -29,9 +29,12 @@
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};
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reserved-memory {
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u-boot,dm-spl;
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optee@de000000 {
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reg = <0xde000000 0x02000000>;
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no-map;
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u-boot,dm-spl;
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};
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};
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@ -16,8 +16,8 @@
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u-boot,boot-led = "heartbeat";
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u-boot,error-led = "error";
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u-boot,mmc-env-partition = "ssbl";
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st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
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st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
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st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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};
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firmware {
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@ -57,7 +57,7 @@
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};
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};
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&sdmmc2_d47_pins_b {
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&sdmmc2_d47_pins_c {
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u-boot,dm-spl;
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pins {
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u-boot,dm-spl;
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@ -152,7 +152,7 @@
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&sdmmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
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pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
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non-removable;
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no-sd;
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no-sdio;
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@ -10,6 +10,7 @@ obj-y += bsec.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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obj-y += tzc400.o
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else
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obj-y += cmd_stm32prog/
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obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
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@ -556,7 +556,9 @@ static void setup_boot_mode(void)
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env_set("boot_instance", "0");
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break;
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default:
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log_debug("unexpected boot mode = %x\n", boot_mode);
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env_set("boot_device", "invalid");
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env_set("boot_instance", "");
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log_err("unexpected boot mode = %x\n", boot_mode);
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break;
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}
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33
arch/arm/mach-stm32mp/include/mach/tzc.h
Normal file
33
arch/arm/mach-stm32mp/include/mach/tzc.h
Normal file
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@ -0,0 +1,33 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Simple API for configuring TrustZone memory regions
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*
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* The premise is that the desired TZC layout is known beforehand, and it can
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* be configured in one step. tzc_configure() provides this functionality.
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*/
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#ifndef MACH_TZC_H
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#define MACH_TZC_H
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#include <linux/types.h>
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enum tzc_sec_mode {
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TZC_ATTR_SEC_NONE = 0,
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TZC_ATTR_SEC_R = 1,
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TZC_ATTR_SEC_W = 2,
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TZC_ATTR_SEC_RW = 3
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};
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struct tzc_region {
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uintptr_t base;
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uintptr_t top;
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enum tzc_sec_mode sec_mode;
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uint16_t nsec_id;
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uint16_t filters_mask;
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};
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int tzc_configure(uintptr_t tzc, const struct tzc_region *cfg);
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int tzc_disable_filters(uintptr_t tzc, uint16_t filters_mask);
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int tzc_enable_filters(uintptr_t tzc, uint16_t filters_mask);
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void tzc_dump_config(uintptr_t tzc);
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#endif /* MACH_TZC_H */
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@ -11,11 +11,13 @@
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <ram.h>
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#include <spl.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <mach/tzc.h>
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#include <linux/libfdt.h>
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u32 spl_boot_device(void)
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@ -92,6 +94,96 @@ __weak int board_early_init_f(void)
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return 0;
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}
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uint32_t stm32mp_get_dram_size(void)
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{
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struct ram_info ram;
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struct udevice *dev;
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int ret;
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if (uclass_get_device(UCLASS_RAM, 0, &dev))
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return 0;
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ret = ram_get_info(dev, &ram);
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if (ret)
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return 0;
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return ram.size;
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}
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static int optee_get_reserved_memory(uint32_t *start, uint32_t *size)
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{
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phys_size_t fdt_mem_size;
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fdt_addr_t fdt_start;
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ofnode node;
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node = ofnode_path("/reserved-memory/optee");
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if (!ofnode_valid(node))
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return 0;
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fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size);
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*start = fdt_start;
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*size = fdt_mem_size;
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return (fdt_start < 0) ? fdt_start : 0;
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}
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#define CFG_SHMEM_SIZE 0x200000
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#define STM32_TZC_NSID_ALL 0xffff
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#define STM32_TZC_FILTER_ALL 3
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void stm32_init_tzc_for_optee(void)
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{
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const uint32_t dram_size = stm32mp_get_dram_size();
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const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1);
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uint32_t optee_base, optee_size, tee_shmem_base;
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const uintptr_t tzc = STM32_TZC_BASE;
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int ret;
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if (dram_size == 0)
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panic("Cannot determine DRAM size from devicetree\n");
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ret = optee_get_reserved_memory(&optee_base, &optee_size);
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if (ret < 0 || optee_size <= CFG_SHMEM_SIZE)
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panic("Invalid OPTEE reserved memory in devicetree\n");
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tee_shmem_base = optee_base + optee_size - CFG_SHMEM_SIZE;
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const struct tzc_region optee_config[] = {
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{
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.base = STM32_DDR_BASE,
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.top = optee_base - 1,
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.sec_mode = TZC_ATTR_SEC_NONE,
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.nsec_id = STM32_TZC_NSID_ALL,
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.filters_mask = STM32_TZC_FILTER_ALL,
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}, {
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.base = optee_base,
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.top = tee_shmem_base - 1,
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.sec_mode = TZC_ATTR_SEC_RW,
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.nsec_id = 0,
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.filters_mask = STM32_TZC_FILTER_ALL,
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}, {
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.base = tee_shmem_base,
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.top = dram_top,
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.sec_mode = TZC_ATTR_SEC_NONE,
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.nsec_id = STM32_TZC_NSID_ALL,
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.filters_mask = STM32_TZC_FILTER_ALL,
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}, {
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.top = 0,
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}
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};
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flush_dcache_all();
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tzc_configure(tzc, optee_config);
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tzc_dump_config(tzc);
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dcache_disable();
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}
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void spl_board_prepare_for_optee(void *fdt)
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{
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stm32_init_tzc_for_optee();
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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136
arch/arm/mach-stm32mp/tzc400.c
Normal file
136
arch/arm/mach-stm32mp/tzc400.c
Normal file
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@ -0,0 +1,136 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Simple API for configuring TrustZone memory restrictions for TZC400
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*/
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#define LOG_CATEGORY LOGC_ARCH
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#include <linux/iopoll.h>
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#include <mach/tzc.h>
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#define TZC_TIMEOUT_US 100
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#define TZC_BUILD_CONFIG 0x00
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#define TZC_ACTION 0x04
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#define TZC_ACTION_NONE 0
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#define TZC_ACTION_ERR 1
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#define TZC_ACTION_INT 2
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#define TZC_ACTION_INT_ERR 3
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#define TZC_GATE_KEEPER 0x08
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#define TZC_REGION0_OFFSET 0x100
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#define TZC_REGION_CFG_SIZE 0x20
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#define TZC_REGION1_OFFSET 0x120
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#define TZC_REGION_BASE 0x00
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#define TZC_REGION_TOP 0x08
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#define TZC_REGION_ATTRIBUTE 0x10
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#define TZC_REGION_ACCESS 0x14
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static uint32_t tzc_read(uintptr_t tzc, size_t reg)
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{
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return readl(tzc + reg);
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}
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static void tzc_write(uintptr_t tzc, size_t reg, uint32_t val)
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{
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writel(val, tzc + reg);
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}
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static uint16_t tzc_config_get_active_filters(const struct tzc_region *cfg)
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{
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uint16_t active_filters = 0;
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for ( ; cfg->top != 0; cfg++)
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active_filters |= cfg->filters_mask;
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return active_filters;
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}
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int tzc_configure(uintptr_t tzc, const struct tzc_region *cfg)
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{
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uintptr_t region = tzc + TZC_REGION1_OFFSET;
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uint32_t nsid, attr_reg, active_filters;
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int ret;
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active_filters = tzc_config_get_active_filters(cfg);
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if (active_filters == 0)
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return -EINVAL;
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ret = tzc_disable_filters(tzc, active_filters);
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if (ret < 0)
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return ret;
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for ( ; cfg->top != 0; cfg++, region += TZC_REGION_CFG_SIZE) {
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attr_reg = (cfg->sec_mode & 0x03) << 30;
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attr_reg |= (cfg->filters_mask & 0x03) << 0;
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nsid = cfg->nsec_id & 0xffff;
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nsid |= nsid << 16;
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tzc_write(region, TZC_REGION_BASE, cfg->base);
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tzc_write(region, TZC_REGION_TOP, cfg->top);
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tzc_write(region, TZC_REGION_ACCESS, nsid);
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tzc_write(region, TZC_REGION_ATTRIBUTE, attr_reg);
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}
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tzc_write(tzc, TZC_ACTION, TZC_ACTION_ERR);
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return tzc_enable_filters(tzc, active_filters);
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}
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int tzc_disable_filters(uintptr_t tzc, uint16_t filters_mask)
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{
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uint32_t gate = tzc_read(tzc, TZC_GATE_KEEPER);
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uint32_t filter_status = filters_mask << 16;
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gate &= ~filters_mask;
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tzc_write(tzc, TZC_GATE_KEEPER, gate);
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return readl_poll_timeout(tzc + TZC_GATE_KEEPER, gate,
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(gate & filter_status) == 0, TZC_TIMEOUT_US);
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}
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|
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int tzc_enable_filters(uintptr_t tzc, uint16_t filters_mask)
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{
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uint32_t gate = tzc_read(tzc, TZC_GATE_KEEPER);
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uint32_t filter_status = filters_mask << 16;
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gate |= filters_mask;
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tzc_write(tzc, TZC_GATE_KEEPER, gate);
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return readl_poll_timeout(tzc + TZC_GATE_KEEPER, gate,
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(gate & filter_status) == filter_status,
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TZC_TIMEOUT_US);
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}
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|
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static const char *sec_access_str_from_attr(uint32_t attr)
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{
|
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const char *const sec_mode[] = { "none", "RO ", "WO ", "RW " };
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|
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return sec_mode[(attr >> 30) & 0x03];
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}
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|
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void tzc_dump_config(uintptr_t tzc)
|
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{
|
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uint32_t build_config, base, top, attr, nsaid;
|
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int num_regions, i;
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uintptr_t region;
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|
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build_config = tzc_read(tzc, TZC_BUILD_CONFIG);
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num_regions = ((build_config >> 0) & 0x1f) + 1;
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|
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for (i = 0; i < num_regions; i++) {
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region = tzc + TZC_REGION0_OFFSET + i * TZC_REGION_CFG_SIZE;
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|
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base = tzc_read(region, TZC_REGION_BASE);
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top = tzc_read(region, TZC_REGION_TOP);
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attr = tzc_read(region, TZC_REGION_ATTRIBUTE);
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nsaid = tzc_read(region, TZC_REGION_ACCESS);
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if (attr == 0 && nsaid == 0)
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continue;
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|
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log_info("TZC region %u: %08x->%08x - filters 0x%x\n",
|
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i, base, top, (attr >> 0) & 0xf);
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log_info("\t Secure access %s NSAID %08x\n",
|
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sec_access_str_from_attr(attr), nsaid);
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}
|
||||
}
|
||||
|
|
@ -155,6 +155,7 @@ static void board_key_check(void)
|
|||
&gpio, GPIOD_IS_IN)) {
|
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log_debug("could not find a /config/st,fastboot-gpios\n");
|
||||
} else {
|
||||
udelay(20);
|
||||
if (dm_gpio_get_value(&gpio)) {
|
||||
log_notice("Fastboot key pressed, ");
|
||||
boot_mode = BOOT_FASTBOOT;
|
||||
|
|
@ -168,6 +169,7 @@ static void board_key_check(void)
|
|||
&gpio, GPIOD_IS_IN)) {
|
||||
log_debug("could not find a /config/st,stm32prog-gpios\n");
|
||||
} else {
|
||||
udelay(20);
|
||||
if (dm_gpio_get_value(&gpio)) {
|
||||
log_notice("STM32Programmer key pressed, ");
|
||||
boot_mode = BOOT_STM32PROG;
|
||||
|
|
|
|||
|
|
@ -167,6 +167,10 @@ __weak void spl_board_prepare_for_linux(void)
|
|||
/* Nothing to do! */
|
||||
}
|
||||
|
||||
__weak void spl_board_prepare_for_optee(void *fdt)
|
||||
{
|
||||
}
|
||||
|
||||
__weak void spl_board_prepare_for_boot(void)
|
||||
{
|
||||
/* Nothing to do! */
|
||||
|
|
@ -763,6 +767,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
|
|||
#if CONFIG_IS_ENABLED(OPTEE)
|
||||
case IH_OS_TEE:
|
||||
debug("Jumping to U-Boot via OP-TEE\n");
|
||||
spl_board_prepare_for_optee(spl_image.fdt_addr);
|
||||
spl_optee_entry(NULL, NULL, spl_image.fdt_addr,
|
||||
(void *)spl_image.entry_point);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -230,8 +230,8 @@ static int mmc_load_image_raw_os(struct spl_image_info *spl_image,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (spl_image->os != IH_OS_LINUX) {
|
||||
puts("Expected Linux image is not found. Trying to start U-boot\n");
|
||||
if (spl_image->os != IH_OS_LINUX && spl_image->os != IH_OS_TEE) {
|
||||
puts("Expected image is not found. Trying to start U-boot\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -73,6 +73,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#define RCC_PLL2FRACR 0xA0
|
||||
#define RCC_PLL2CSGR 0xA4
|
||||
#define RCC_I2C46CKSELR 0xC0
|
||||
#define RCC_SPI6CKSELR 0xC4
|
||||
#define RCC_CPERCKSELR 0xD0
|
||||
#define RCC_STGENCKSELR 0xD4
|
||||
#define RCC_DDRITFCR 0xD8
|
||||
|
|
@ -103,6 +104,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#define RCC_I2C12CKSELR 0x8C0
|
||||
#define RCC_I2C35CKSELR 0x8C4
|
||||
#define RCC_SPI2S1CKSELR 0x8D8
|
||||
#define RCC_SPI2S23CKSELR 0x8DC
|
||||
#define RCC_SPI45CKSELR 0x8E0
|
||||
#define RCC_UART6CKSELR 0x8E4
|
||||
#define RCC_UART24CKSELR 0x8E8
|
||||
|
|
@ -313,7 +315,9 @@ enum stm32mp1_parent_sel {
|
|||
_DSI_SEL,
|
||||
_ADC12_SEL,
|
||||
_SPI1_SEL,
|
||||
_SPI23_SEL,
|
||||
_SPI45_SEL,
|
||||
_SPI6_SEL,
|
||||
_RTC_SEL,
|
||||
_PARENT_SEL_NB,
|
||||
_UNKNOWN_SEL = 0xff,
|
||||
|
|
@ -524,6 +528,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
|
|||
STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
|
||||
STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
|
||||
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 11, SPI2_K, _SPI23_SEL),
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 12, SPI3_K, _SPI23_SEL),
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
|
||||
|
|
@ -536,6 +542,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
|
|||
STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
|
||||
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 9, SPI4_K, _SPI45_SEL),
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
|
||||
|
||||
|
|
@ -549,6 +556,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
|
|||
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
|
||||
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
|
||||
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
|
||||
|
|
@ -613,10 +621,13 @@ static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
|
|||
static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
|
||||
static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
|
||||
static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
|
||||
/* same parents for SPI1=RCC_SPI2S1CKSELR and SPI2&3 = RCC_SPI2S23CKSELR */
|
||||
static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
|
||||
_PLL3_R};
|
||||
static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
|
||||
_HSE_KER};
|
||||
static const u8 spi6_parents[] = {_PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER,
|
||||
_HSE_KER, _PLL3_Q};
|
||||
static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
|
||||
|
||||
static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
|
||||
|
|
@ -643,7 +654,9 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
|
|||
STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
|
||||
STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
|
||||
STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
|
||||
STM32MP1_CLK_PARENT(_SPI23_SEL, RCC_SPI2S23CKSELR, 0, 0x7, spi_parents),
|
||||
STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
|
||||
STM32MP1_CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents),
|
||||
STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
|
||||
(RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
|
||||
rtc_parents),
|
||||
|
|
|
|||
|
|
@ -432,6 +432,20 @@ int spl_parse_image_header(struct spl_image_info *spl_image,
|
|||
const struct image_header *header);
|
||||
|
||||
void spl_board_prepare_for_linux(void);
|
||||
|
||||
/**
|
||||
* spl_board_prepare_for_optee() - Prepare board for an OPTEE payload
|
||||
*
|
||||
* Prepares the board for booting an OP-TEE payload. Initialization is platform
|
||||
* specific, and may include configuring the TrustZone memory, and other
|
||||
* initialization steps required by OP-TEE.
|
||||
* Note that @fdt is not used directly by OP-TEE. OP-TEE passes this @fdt to
|
||||
* its normal world target. This target is not guaranteed to be u-boot, so @fdt
|
||||
* changes that would normally be done by u-boot should be done in this step.
|
||||
*
|
||||
* @fdt: Devicetree that will be passed on, or NULL
|
||||
*/
|
||||
void spl_board_prepare_for_optee(void *fdt);
|
||||
void spl_board_prepare_for_boot(void);
|
||||
int spl_board_ubi_load_image(u32 boot_device);
|
||||
int spl_board_boot_device(u32 boot_device);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue