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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86

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- Use device tree for FSP-M and FSP-S configuration on Intel Apollo Lake
- Add SMBIOS cbmem entry parsing for coreboot
- Various clean-ups to CBFS implementation
This commit is contained in:
Tom Rini 2020-05-27 10:55:55 -04:00
commit 0d6a3e2322
18 changed files with 3400 additions and 679 deletions
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1
arch/x86/cpu/apollolake/Makefile
View file

@ -10,6 +10,7 @@ obj-y += cpu_common.o
ifndef CONFIG_TPL_BUILD
obj-y += cpu.o
obj-y += punit.o
obj-y += fsp_bindings.o
ifdef CONFIG_SPL_BUILD
obj-y += fsp_m.o
endif

1805
arch/x86/cpu/apollolake/fsp_bindings.c Normal file
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File diff suppressed because it is too large Load diff

169
arch/x86/cpu/apollolake/fsp_m.c
View file

@ -8,184 +8,27 @@
#include <dm.h>
#include <log.h>
#include <asm/arch/iomap.h>
#include <asm/arch/fsp/fsp_configs.h>
#include <asm/arch/fsp/fsp_m_upd.h>
#include <asm/arch/fsp_bindings.h>
#include <asm/fsp2/fsp_internal.h>
#include <dm/uclass-internal.h>
/*
* ODT settings:
* If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A and HIGH for ODT_B,
* choose ODT_A_B_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A
* and LOW for ODT_B, choose ODT_A_B_HIGH_LOW.
*
* Note that the enum values correspond to the interpreted UPD fields
* within Ch[3:0]_OdtConfig parameters.
*/
enum {
ODT_A_B_HIGH_LOW = 0 << 1,
ODT_A_B_HIGH_HIGH = 1 << 1,
N_WR_24 = 1 << 5,
};
/*
* LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation.
* There are four physical LPDDR4 channels, each 32-bits wide. There are two
* logical channels using two physical channels together to form a 64-bit
* interface to memory for each logical channel.
*/
enum {
LP4_PHYS_CH0A,
LP4_PHYS_CH0B,
LP4_PHYS_CH1A,
LP4_PHYS_CH1B,
LP4_NUM_PHYS_CHANNELS,
};
/*
* The DQs within a physical channel can be bit-swizzled within each byte.
* Within a channel the bytes can be swapped, but the DQs need to be routed
* with the corresponding DQS (strobe).
*/
enum {
LP4_DQS0,
LP4_DQS1,
LP4_DQS2,
LP4_DQS3,
LP4_NUM_BYTE_LANES,
DQ_BITS_PER_DQS = 8,
};
/* Provide bit swizzling per DQS and byte swapping within a channel */
struct lpddr4_chan_swizzle_cfg {
u8 dqs[LP4_NUM_BYTE_LANES][DQ_BITS_PER_DQS];
};
struct lpddr4_swizzle_cfg {
struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS];
};
static void setup_sdram(struct fsp_m_config *cfg,
const struct lpddr4_swizzle_cfg *swizzle_cfg)
{
const struct lpddr4_chan_swizzle_cfg *sch;
/* Number of bytes to copy per DQS */
const size_t sz = DQ_BITS_PER_DQS;
int chan;
cfg->memory_down = 1;
cfg->scrambler_support = 1;
cfg->channel_hash_mask = 0x36;
cfg->slice_hash_mask = 9;
cfg->interleaved_mode = 2;
cfg->channels_slices_enable = 0;
cfg->min_ref_rate2x_enable = 0;
cfg->dual_rank_support_enable = 1;
/* LPDDR4 is memory down so no SPD addresses */
cfg->dimm0_spd_address = 0;
cfg->dimm1_spd_address = 0;
for (chan = 0; chan < 4; chan++) {
struct fsp_ram_channel *ch = &cfg->chan[chan];
ch->rank_enable = 1;
ch->device_width = 1;
ch->dram_density = 2;
ch->option = 3;
ch->odt_config = ODT_A_B_HIGH_HIGH;
}
/*
* CH0_DQB byte lanes in the bit swizzle configuration field are
* not 1:1. The mapping within the swizzling field is:
* indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
* indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
* indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
* indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
*/
sch = &swizzle_cfg->phys[LP4_PHYS_CH0B];
memcpy(&cfg->ch_bit_swizzling[0][0], &sch->dqs[LP4_DQS1], sz);
memcpy(&cfg->ch_bit_swizzling[0][8], &sch->dqs[LP4_DQS0], sz);
memcpy(&cfg->ch_bit_swizzling[0][16], &sch->dqs[LP4_DQS3], sz);
memcpy(&cfg->ch_bit_swizzling[0][24], &sch->dqs[LP4_DQS2], sz);
/*
* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
*/
sch = &swizzle_cfg->phys[LP4_PHYS_CH0A];
memcpy(&cfg->ch_bit_swizzling[1][0], &sch->dqs[LP4_DQS0], sz);
memcpy(&cfg->ch_bit_swizzling[1][8], &sch->dqs[LP4_DQS1], sz);
memcpy(&cfg->ch_bit_swizzling[1][16], &sch->dqs[LP4_DQS2], sz);
memcpy(&cfg->ch_bit_swizzling[1][24], &sch->dqs[LP4_DQS3], sz);
sch = &swizzle_cfg->phys[LP4_PHYS_CH1B];
memcpy(&cfg->ch_bit_swizzling[2][0], &sch->dqs[LP4_DQS1], sz);
memcpy(&cfg->ch_bit_swizzling[2][8], &sch->dqs[LP4_DQS0], sz);
memcpy(&cfg->ch_bit_swizzling[2][16], &sch->dqs[LP4_DQS3], sz);
memcpy(&cfg->ch_bit_swizzling[2][24], &sch->dqs[LP4_DQS2], sz);
/*
* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
*/
sch = &swizzle_cfg->phys[LP4_PHYS_CH1A];
memcpy(&cfg->ch_bit_swizzling[3][0], &sch->dqs[LP4_DQS0], sz);
memcpy(&cfg->ch_bit_swizzling[3][8], &sch->dqs[LP4_DQS1], sz);
memcpy(&cfg->ch_bit_swizzling[3][16], &sch->dqs[LP4_DQS2], sz);
memcpy(&cfg->ch_bit_swizzling[3][24], &sch->dqs[LP4_DQS3], sz);
}
int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
{
struct fsp_m_config *cfg = &upd->config;
struct fspm_arch_upd *arch = &upd->arch;
ofnode node;
arch->nvs_buffer_ptr = NULL;
prepare_mrc_cache(upd);
arch->stack_base = (void *)0xfef96000;
arch->boot_loader_tolum_size = 0;
arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION;
cfg->serial_debug_port_type = 2;
cfg->serial_debug_port_device = 2;
cfg->serial_debug_port_stride_size = 2;
cfg->serial_debug_port_address = 0;
cfg->package = 1;
/* Don't enforce a memory size limit */
cfg->memory_size_limit = 0;
cfg->low_memory_max_value = 2048; /* 2 GB */
/* No restrictions on memory above 4GiB */
cfg->high_memory_max_value = 0;
node = dev_ofnode(dev);
if (!ofnode_valid(node))
return log_msg_ret("fsp-m settings", -ENOENT);
/* Always default to attempt to use saved training data */
cfg->disable_fast_boot = 0;
const u8 *swizzle_data;
swizzle_data = dev_read_u8_array_ptr(dev, "lpddr4-swizzle",
LP4_NUM_BYTE_LANES *
DQ_BITS_PER_DQS *
LP4_NUM_PHYS_CHANNELS);
if (!swizzle_data)
return log_msg_ret("Cannot read swizzel data", -EINVAL);
setup_sdram(cfg, (struct lpddr4_swizzle_cfg *)swizzle_data);
cfg->pre_mem_gpio_table_ptr = 0;
cfg->profile = 0xb;
cfg->msg_level_mask = 0;
/* other */
cfg->skip_cse_rbp = 1;
cfg->periodic_retraining_disable = 0;
cfg->enable_s3_heci2 = 0;
return 0;
return fsp_m_update_config_from_dtb(node, cfg);
}
/*

424
arch/x86/cpu/apollolake/fsp_s.c
View file

@ -24,418 +24,48 @@
#include <asm/arch/fsp/fsp_configs.h>
#include <asm/arch/fsp/fsp_s_upd.h>
#include <linux/bitops.h>
#include <asm/arch/fsp_bindings.h>
#define PCH_P2SB_E0 0xe0
#define HIDE_BIT BIT(0)
#define INTEL_GSPI_MAX 3
#define MAX_USB2_PORTS 8
enum {
CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
};
/* Serial IRQ control. SERIRQ_QUIET is the default (0) */
enum serirq_mode {
SERIRQ_QUIET,
SERIRQ_CONTINUOUS,
SERIRQ_OFF,
};
struct gspi_cfg {
/* Bus speed in MHz */
u32 speed_mhz;
/* Bus should be enabled prior to ramstage with temporary base */
u8 early_init;
};
/*
* This structure will hold data required by common blocks.
* These are soc specific configurations which will be filled by soc.
* We'll fill this structure once during init and use the data in common block.
*/
struct soc_intel_common_config {
int chipset_lockdown;
struct gspi_cfg gspi[INTEL_GSPI_MAX];
};
enum pnp_settings {
PNP_PERF,
PNP_POWER,
PNP_PERF_POWER,
};
struct usb2_eye_per_port {
u8 per_port_tx_pe_half;
u8 per_port_pe_txi_set;
u8 per_port_txi_set;
u8 hs_skew_sel;
u8 usb_tx_emphasis_en;
u8 per_port_rxi_set;
u8 hs_npre_drv_sel;
u8 override_en;
};
struct apl_config {
/* Common structure containing soc config data required by common code*/
struct soc_intel_common_config common_soc_config;
/*
* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
* four CLKREQ inputs, but six root ports. Root ports without an
* associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
*/
u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
/* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */
u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS];
/* De-emphasis enable configuration for each PCIe root port */
u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS];
/*
* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR mode Number of dealy elements.Each = 125pSec.
*/
u32 emmc_tx_cmd_cntl;
/*
* [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
*/
u32 emmc_tx_data_cntl1;
/*
* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR12/Compatibility mode Number of dealy elements.
* Each = 125pSec.
*/
u32 emmc_tx_data_cntl2;
/*
* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR12/Compatibility mode Number of dealy elements.
* Each = 125pSec.
*/
u32 emmc_rx_cmd_data_cntl1;
/*
* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
* [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
*/
u32 emmc_rx_strobe_cntl;
/*
* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
*/
u32 emmc_rx_cmd_data_cntl2;
/* Select the eMMC max speed allowed */
u32 emmc_host_max_speed;
/* Specifies on which IRQ the SCI will internally appear */
u32 sci_irq;
/* Configure serial IRQ (SERIRQ) line */
enum serirq_mode serirq_mode;
/* Configure LPSS S0ix Enable */
bool lpss_s0ix_enable;
/* Enable DPTF support */
bool dptf_enable;
/* TCC activation offset value in degrees Celsius */
int tcc_offset;
/*
* Configure Audio clk gate and power gate
* IOSF-SB port ID 92 offset 0x530 [5] and [3]
*/
bool hdaudio_clk_gate_enable;
bool hdaudio_pwr_gate_enable;
bool hdaudio_bios_config_lockdown;
/* SLP S3 minimum assertion width */
int slp_s3_assertion_width_usecs;
/* GPIO pin for PERST_0 */
u32 prt0_gpio;
/* USB2 eye diagram settings per port */
struct usb2_eye_per_port usb2eye[MAX_USB2_PORTS];
/* GPIO SD card detect pin */
unsigned int sdcard_cd_gpio;
/*
* PRMRR size setting with three options
* 0x02000000 - 32MiB
* 0x04000000 - 64MiB
* 0x08000000 - 128MiB
*/
u32 PrmrrSize;
/*
* Enable SGX feature.
* Enabling SGX feature is 2 step process,
* (1) set sgx_enable = 1
* (2) set PrmrrSize to supported size
*/
bool sgx_enable;
/*
* Select PNP Settings.
* (0) Performance,
* (1) Power
* (2) Power & Performance
*/
enum pnp_settings pnp_settings;
/*
* PMIC PCH_PWROK delay configuration - IPC Configuration
* Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address
* (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
*/
u32 pmic_pmc_ipc_ctrl;
/*
* Options to disable XHCI Link Compliance Mode. Default is FALSE to not
* disable Compliance Mode. Set TRUE to disable Compliance Mode.
* 0:FALSE(Default), 1:True.
*/
bool disable_compliance_mode;
/*
* Options to change USB3 ModPhy setting for the Integrated Filter (IF)
* value. Default is 0 to not changing default IF value (0x12). Set
* value with the range from 0x01 to 0xff to change IF value.
*/
u32 mod_phy_if_value;
/*
* Options to bump USB3 LDO voltage. Default is FALSE to not increasing
* LDO voltage. Set TRUE to increase LDO voltage with 40mV.
* 0:FALSE (default), 1:True.
*/
bool mod_phy_voltage_bump;
/*
* Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting
* the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage
* configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16)
* + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]:
* 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default).
*/
u32 pmic_vdd2_voltage;
/* Option to enable VTD feature */
bool enable_vtd;
};
static int get_config(struct udevice *dev, struct apl_config *apl)
{
const u8 *ptr;
ofnode node;
u32 emmc[4];
int ret;
memset(apl, '\0', sizeof(*apl));
node = dev_read_subnode(dev, "fsp-s");
if (!ofnode_valid(node))
return log_msg_ret("fsp-s settings", -ENOENT);
ptr = ofnode_read_u8_array_ptr(node, "pcie-rp-clkreq-pin",
MAX_PCIE_PORTS);
if (!ptr)
return log_msg_ret("pcie-rp-clkreq-pin", -EINVAL);
memcpy(apl->pcie_rp_clkreq_pin, ptr, MAX_PCIE_PORTS);
ret = ofnode_read_u32(node, "prt0-gpio", &apl->prt0_gpio);
if (ret)
return log_msg_ret("prt0-gpio", ret);
ret = ofnode_read_u32(node, "sdcard-cd-gpio", &apl->sdcard_cd_gpio);
if (ret)
return log_msg_ret("sdcard-cd-gpio", ret);
ret = ofnode_read_u32_array(node, "emmc", emmc, ARRAY_SIZE(emmc));
if (ret)
return log_msg_ret("emmc", ret);
apl->emmc_tx_data_cntl1 = emmc[0];
apl->emmc_tx_data_cntl2 = emmc[1];
apl->emmc_rx_cmd_data_cntl1 = emmc[2];
apl->emmc_rx_cmd_data_cntl2 = emmc[3];
apl->dptf_enable = ofnode_read_bool(node, "dptf-enable");
apl->hdaudio_clk_gate_enable = ofnode_read_bool(node,
"hdaudio-clk-gate-enable");
apl->hdaudio_pwr_gate_enable = ofnode_read_bool(node,
"hdaudio-pwr-gate-enable");
apl->hdaudio_bios_config_lockdown = ofnode_read_bool(node,
"hdaudio-bios-config-lockdown");
apl->lpss_s0ix_enable = ofnode_read_bool(node, "lpss-s0ix-enable");
/* Santa */
apl->usb2eye[1].per_port_pe_txi_set = 7;
apl->usb2eye[1].per_port_txi_set = 2;
return 0;
}
static void apl_fsp_silicon_init_params_cb(struct apl_config *apl,
struct fsp_s_config *cfg)
{
u8 port;
for (port = 0; port < MAX_USB2_PORTS; port++) {
if (apl->usb2eye[port].per_port_tx_pe_half)
cfg->port_usb20_per_port_tx_pe_half[port] =
apl->usb2eye[port].per_port_tx_pe_half;
if (apl->usb2eye[port].per_port_pe_txi_set)
cfg->port_usb20_per_port_pe_txi_set[port] =
apl->usb2eye[port].per_port_pe_txi_set;
if (apl->usb2eye[port].per_port_txi_set)
cfg->port_usb20_per_port_txi_set[port] =
apl->usb2eye[port].per_port_txi_set;
if (apl->usb2eye[port].hs_skew_sel)
cfg->port_usb20_hs_skew_sel[port] =
apl->usb2eye[port].hs_skew_sel;
if (apl->usb2eye[port].usb_tx_emphasis_en)
cfg->port_usb20_i_usb_tx_emphasis_en[port] =
apl->usb2eye[port].usb_tx_emphasis_en;
if (apl->usb2eye[port].per_port_rxi_set)
cfg->port_usb20_per_port_rxi_set[port] =
apl->usb2eye[port].per_port_rxi_set;
if (apl->usb2eye[port].hs_npre_drv_sel)
cfg->port_usb20_hs_npre_drv_sel[port] =
apl->usb2eye[port].hs_npre_drv_sel;
}
}
int fsps_update_config(struct udevice *dev, ulong rom_offset,
struct fsps_upd *upd)
{
struct fsp_s_config *cfg = &upd->config;
struct apl_config *apl;
struct binman_entry vbt;
void *buf;
int ret;
ofnode node;
ret = binman_entry_find("intel-vbt", &vbt);
if (ret)
return log_msg_ret("Cannot find VBT", ret);
vbt.image_pos += rom_offset;
buf = malloc(vbt.size);
if (!buf)
return log_msg_ret("Alloc VBT", -ENOMEM);
if (IS_ENABLED(CONFIG_HAVE_VBT)) {
struct binman_entry vbt;
void *vbt_buf;
int ret;
/*
* Load VBT before devicetree-specific config. This only supports
* memory-mapped SPI at present.
*/
bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
memcpy(buf, (void *)vbt.image_pos, vbt.size);
bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
if (*(u32 *)buf != VBT_SIGNATURE)
return log_msg_ret("VBT signature", -EINVAL);
cfg->graphics_config_ptr = (ulong)buf;
ret = binman_entry_find("intel-vbt", &vbt);
if (ret)
return log_msg_ret("Cannot find VBT", ret);
vbt.image_pos += rom_offset;
vbt_buf = malloc(vbt.size);
if (!vbt_buf)
return log_msg_ret("Alloc VBT", -ENOMEM);
apl = malloc(sizeof(*apl));
if (!apl)
return log_msg_ret("config", -ENOMEM);
get_config(dev, apl);
/*
* Load VBT before devicetree-specific config. This only
* supports memory-mapped SPI at present.
*/
bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
memcpy(vbt_buf, (void *)vbt.image_pos, vbt.size);
bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
if (*(u32 *)vbt_buf != VBT_SIGNATURE)
return log_msg_ret("VBT signature", -EINVAL);
cfg->ish_enable = 0;
cfg->enable_sata = 0;
cfg->pcie_root_port_en[2] = 0;
cfg->pcie_rp_hot_plug[2] = 0;
cfg->pcie_root_port_en[3] = 0;
cfg->pcie_rp_hot_plug[3] = 0;
cfg->pcie_root_port_en[4] = 0;
cfg->pcie_rp_hot_plug[4] = 0;
cfg->pcie_root_port_en[5] = 0;
cfg->pcie_rp_hot_plug[5] = 0;
cfg->pcie_root_port_en[1] = 0;
cfg->pcie_rp_hot_plug[1] = 0;
cfg->usb_otg = 0;
cfg->i2c6_enable = 0;
cfg->i2c7_enable = 0;
cfg->hsuart3_enable = 0;
cfg->spi1_enable = 0;
cfg->spi2_enable = 0;
cfg->sdio_enabled = 0;
memcpy(cfg->pcie_rp_clk_req_number, apl->pcie_rp_clkreq_pin,
sizeof(cfg->pcie_rp_clk_req_number));
memcpy(cfg->pcie_rp_hot_plug, apl->pcie_rp_hotplug_enable,
sizeof(cfg->pcie_rp_hot_plug));
switch (apl->serirq_mode) {
case SERIRQ_QUIET:
cfg->sirq_enable = 1;
cfg->sirq_mode = 0;
break;
case SERIRQ_CONTINUOUS:
cfg->sirq_enable = 1;
cfg->sirq_mode = 1;
break;
case SERIRQ_OFF:
default:
cfg->sirq_enable = 0;
break;
cfg->graphics_config_ptr = (ulong)vbt_buf;
}
if (apl->emmc_tx_cmd_cntl)
cfg->emmc_tx_cmd_cntl = apl->emmc_tx_cmd_cntl;
if (apl->emmc_tx_data_cntl1)
cfg->emmc_tx_data_cntl1 = apl->emmc_tx_data_cntl1;
if (apl->emmc_tx_data_cntl2)
cfg->emmc_tx_data_cntl2 = apl->emmc_tx_data_cntl2;
if (apl->emmc_rx_cmd_data_cntl1)
cfg->emmc_rx_cmd_data_cntl1 = apl->emmc_rx_cmd_data_cntl1;
if (apl->emmc_rx_strobe_cntl)
cfg->emmc_rx_strobe_cntl = apl->emmc_rx_strobe_cntl;
if (apl->emmc_rx_cmd_data_cntl2)
cfg->emmc_rx_cmd_data_cntl2 = apl->emmc_rx_cmd_data_cntl2;
if (apl->emmc_host_max_speed)
cfg->e_mmc_host_max_speed = apl->emmc_host_max_speed;
node = dev_read_subnode(dev, "fsp-s");
if (!ofnode_valid(node))
return log_msg_ret("fsp-s settings", -ENOENT);
cfg->lpss_s0ix_enable = apl->lpss_s0ix_enable;
cfg->skip_mp_init = true;
/* Disable setting of EISS bit in FSP */
cfg->spi_eiss = 0;
/* Disable FSP from locking access to the RTC NVRAM */
cfg->rtc_lock = 0;
/* Enable Audio clk gate and power gate */
cfg->hd_audio_clk_gate = apl->hdaudio_clk_gate_enable;
cfg->hd_audio_pwr_gate = apl->hdaudio_pwr_gate_enable;
/* Bios config lockdown Audio clk and power gate */
cfg->bios_cfg_lock_down = apl->hdaudio_bios_config_lockdown;
apl_fsp_silicon_init_params_cb(apl, cfg);
cfg->usb_otg = true;
cfg->vtd_enable = apl->enable_vtd;
return 0;
return fsp_s_update_config_from_dtb(node, cfg);
}
static void p2sb_set_hide_bit(pci_dev_t dev, int hide)

14
arch/x86/cpu/coreboot/tables.c
View file

@ -69,6 +69,17 @@ static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info)
info->vbnv_size = vbnv->vbnv_size;
}
static void cb_parse_cbmem_entry(unsigned char *ptr, struct sysinfo_t *info)
{
struct cb_cbmem_entry *entry = (struct cb_cbmem_entry *)ptr;
if (entry->id != CBMEM_ID_SMBIOS)
return;
info->smbios_start = entry->address;
info->smbios_size = entry->entry_size;
}
static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info)
{
int i;
@ -206,6 +217,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
case CB_TAG_VBNV:
cb_parse_vbnv(ptr, info);
break;
case CB_TAG_CBMEM_ENTRY:
cb_parse_cbmem_entry(ptr, info);
break;
default:
cb_parse_unhandled(rec->tag, ptr);
break;

73
arch/x86/dts/chromebook_coral.dts
View file

@ -21,6 +21,8 @@
#include <asm/arch-apollolake/iomap.h>
#include <asm/arch-apollolake/pm.h>
#include <dt-bindings/clock/intel-clock.h>
#include <asm/arch-apollolake/fsp/fsp_m_upd.h>
#include <asm/arch-apollolake/fsp/fsp_s_upd.h>
/ {
model = "Google Coral";
@ -436,7 +438,42 @@
PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
>;
lpddr4-swizzle = /bits/ 8 <
fspm,package = <PACKAGE_BGA>;
fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>;
fspm,memory-down = <MEMORY_DOWN_YES>;
fspm,scrambler-support = <1>;
fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>;
fspm,channel-hash-mask = <0x36>;
fspm,slice-hash-mask = <0x9>;
fspm,dual-rank-support-enable = <1>;
fspm,low-memory-max-value = <2048>;
fspm,ch0-rank-enable = <1>;
fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>;
fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>;
fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING |
CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
fspm,ch1-rank-enable = <1>;
fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>;
fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>;
fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING |
CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
fspm,ch2-rank-enable = <1>;
fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>;
fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>;
fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING |
CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
fspm,ch3-rank-enable = <1>;
fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>;
fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>;
fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING |
CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
fspm,fspm,skip-cse-rbp = <1>;
fspm,ch-bit-swizzling = /bits/ 8 <
/* LP4_PHYS_CH0A */
/* DQA[0:7] pins of LPDDR4 module */
@ -484,8 +521,19 @@
&fsp_s {
u-boot,dm-pre-proper;
fsps,ish-enable = <0>;
fsps,enable-sata = <0>;
fsps,pcie-root-port-en = [00 00 00 00 00 01];
fsps,pcie-rp-hot-plug = [00 00 00 00 00 01];
fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>;
fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>;
fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>;
fsps,spi1-enable = <SPIX_ENABLE_DISABLED>;
fsps,spi2-enable = <SPIX_ENABLE_DISABLED>;
fsps,sdio-enabled = <0>;
/* Disable unused clkreq of PCIe root ports */
pcie-rp-clkreq-pin = /bits/ 8 <0 /* wifi/bt */
fsps,pcie-rp-clk-req-number = /bits/ 8 <0 /* wifi/bt */
CLKREQ_DISABLED
CLKREQ_DISABLED
CLKREQ_DISABLED
@ -539,18 +587,27 @@
* [14:8] steps of delay for Auto Tuning Mode, each 125ps
* [6:0] steps of delay for HS200, each 125ps
*/
emmc = <0x0c16 0x28162828 0x00181717 0x10008>;
/* Enable DPTF */
dptf-enable;
fsps,emmc-tx-data-cntl1 = <0x0c16>;
fsps,emmc-tx-data-cntl2 = <0x28162828>;
fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>;
fsps,emmc-rx-cmd-data-cntl2 = <0x10008>;
/* Enable Audio Clock and Power gating */
hdaudio-clk-gate-enable;
hdaudio-pwr-gate-enable;
hdaudio-bios-config-lockdown;
fsps,hd-audio-clk-gate = <1>;
fsps,hd-audio-pwr-gate = <1>;
fsps,bios-cfg-lock-down = <1>;
/* Enable lpss s0ix */
lpss-s0ix-enable;
fsps,lpss-s0ix-enable = <1>;
fsps,skip-mp-init = <1>;
fsps,spi-eiss = <0>;
fsps,rtc-lock = <0>;
fsps,port-usb20-per-port-pe-txi-set = [07 07 06 06 07 07 07 01];
fsps,port-usb20-per-port-txi-set = [00 02 00 00 00 00 00 03];
/*
* TODO(sjg@chromium.org): Move this to the I2C nodes

168
arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h
View file

@ -7,6 +7,7 @@
#ifndef __ASM_ARCH_FSP_M_UDP_H
#define __ASM_ARCH_FSP_M_UDP_H
#ifndef __ASSEMBLY__
#include <asm/fsp2/fsp_api.h>
#define FSP_DRAM_CHANNELS 4
@ -119,5 +120,172 @@ struct __packed fspm_upd {
u8 unused_upd_space2[158];
u16 upd_terminator;
};
#endif
#define SERIAL_DEBUG_PORT_TYPE_NONE 0
#define SERIAL_DEBUG_PORT_TYPE_IO 1
#define SERIAL_DEBUG_PORT_TYPE_MMIO 2
#define SERIAL_DEBUG_PORT_DEVICE_UART0 0
#define SERIAL_DEBUG_PORT_DEVICE_UART1 1
#define SERIAL_DEBUG_PORT_DEVICE_UART2 2
#define SERIAL_DEBUG_PORT_DEVICE_EXTERNAL 3
#define SERIAL_DEBUG_PORT_STRIDE_SIZE_1 0
#define SERIAL_DEBUG_PORT_STRIDE_SIZE_4 2
#define IGD_DVMT_50_PRE_ALLOC_64M 0x02
#define IGD_DVMT_50_PRE_ALLOC_96M 0x03
#define IGD_DVMT_50_PRE_ALLOC_128M 0x04
#define IGD_DVMT_50_PRE_ALLOC_160M 0x05
#define IGD_DVMT_50_PRE_ALLOC_192M 0x06
#define IGD_DVMT_50_PRE_ALLOC_224M 0x07
#define IGD_DVMT_50_PRE_ALLOC_256M 0x08
#define IGD_DVMT_50_PRE_ALLOC_288M 0x09
#define IGD_DVMT_50_PRE_ALLOC_320M 0x0a
#define IGD_DVMT_50_PRE_ALLOC_352M 0x0b
#define IGD_DVMT_50_PRE_ALLOC_384M 0x0c
#define IGD_DVMT_50_PRE_ALLOC_416M 0x0d
#define IGD_DVMT_50_PRE_ALLOC_448M 0x0e
#define IGD_DVMT_50_PRE_ALLOC_480M 0x0f
#define IGD_DVMT_50_PRE_ALLOC_512M 0x10
#define IGD_APERTURE_SIZE_128M 0x1
#define IGD_APERTURE_SIZE_256M 0x2
#define IGD_APERTURE_SIZE_512M 0x3
#define GTT_SIZE_2M 1
#define GTT_SIZE_4M 2
#define GTT_SIZE_8M 3
#define PRIMARY_VIDEO_ADAPTER_AUTO 0
#define PRIMARY_VIDEO_ADAPTER_IGD 2
#define PRIMARY_VIDEO_ADAPTER_PCI 3
#define PACKAGE_SODIMM 0
#define PACKAGE_BGA 1
#define PACKAGE_BGA_MIRRORED 2
#define PACKAGE_SODIMM_UDIMM_RANK_MIRRORED 3
#define PROFILE_WIO2_800_7_8_8 0x1
#define PROFILE_WIO2_1066_9_10_10 0x2
#define PROFILE_LPDDR3_1066_8_10_10 0x3
#define PROFILE_LPDDR3_1333_10_12_12 0x4
#define PROFILE_LPDDR3_1600_12_15_15 0x5
#define PROFILE_LPDDR3_1866_14_17_17 0x6
#define PROFILE_LPDDR3_2133_16_20_20 0x7
#define PROFILE_LPDDR4_1066_10_10_10 0x8
#define PROFILE_LPDDR4_1600_14_15_15 0x9
#define PROFILE_LPDDR4_2133_20_20_20 0xa
#define PROFILE_LPDDR4_2400_24_22_22 0xb
#define PROFILE_LPDDR4_2666_24_24_24 0xc
#define PROFILE_LPDDR4_2933_28_27_27 0xd
#define PROFILE_LPDDR4_3200_28_29_29 0xe
#define PROFILE_DDR3_1066_6_6_6 0xf
#define PROFILE_DDR3_1066_7_7_7 0x10
#define PROFILE_DDR3_1066_8_8_8 0x11
#define PROFILE_DDR3_1333_7_7_7 0x12
#define PROFILE_DDR3_1333_8_8_8 0x13
#define PROFILE_DDR3_1333_9_9_9 0x14
#define PROFILE_DDR3_1333_10_10_10 0x15
#define PROFILE_DDR3_1600_8_8_8 0x16
#define PROFILE_DDR3_1600_9_9_9 0x17
#define PROFILE_DDR3_1600_10_10_10 0x18
#define PROFILE_DDR3_1600_11_11_11 0x19
#define PROFILE_DDR3_1866_10_10_10 0x1a
#define PROFILE_DDR3_1866_11_11_11 0x1b
#define PROFILE_DDR3_1866_12_12_12 0x1c
#define PROFILE_DDR3_1866_13_13_13 0x1d
#define PROFILE_DDR3_2133_11_11_11 0x1e
#define PROFILE_DDR3_2133_12_12_12 0x1f
#define PROFILE_DDR3_2133_13_13_13 0x20
#define PROFILE_DDR3_2133_14_14_14 0x21
#define PROFILE_DDR4_1333_10_10_10 0x22
#define PROFILE_DDR4_1600_10_10_10 0x23
#define PROFILE_DDR4_1600_11_11_11 0x24
#define PROFILE_DDR4_1600_12_12_12 0x25
#define PROFILE_DDR4_1866_12_12_12 0x26
#define PROFILE_DDR4_1866_13_13_13 0x27
#define PROFILE_DDR4_1866_14_14_14 0x28
#define PROFILE_DDR4_2133_14_14_14 0x29
#define PROFILE_DDR4_2133_15_15_15 0x2a
#define PROFILE_DDR4_2133_16_16_16 0x2b
#define PROFILE_DDR4_2400_15_15_15 0x2c
#define PROFILE_DDR4_2400_16_16_16 0x2d
#define PROFILE_DDR4_2400_17_17_17 0x2e
#define PROFILE_DDR4_2400_18_18_18 0x2f
#define MEMORY_DOWN_NO 0
#define MEMORY_DOWN_YES 1
#define MEMORY_DOWN_MD_SODIMM 2
#define MEMORY_DOWN_LPDDR4 3
#define DDR3L_PAGE_SIZE_1KB 1
#define DDR3L_PAGE_SIZE_2KB 2
#define INTERLEAVED_MODE_DISABLE 0
#define INTERLEAVED_MODE_ENABLE 2
#define RMT_MODE_DISABLE 0
#define RMT_MODE_ENABLE 3
#define CHX_DEVICE_WIDTH_X8 0
#define CHX_DEVICE_WIDTH_X16 1
#define CHX_DEVICE_WIDTH_X32 2
#define CHX_DEVICE_WIDTH_X64 3
#define CHX_DEVICE_DENSITY_4GB 0
#define CHX_DEVICE_DENSITY_6GB 1
#define CHX_DEVICE_DENSITY_8GB 2
#define CHX_DEVICE_DENSITY_12GB 3
#define CHX_DEVICE_DENSITY_16GB 4
#define CHX_DEVICE_DENSITY_2GB 5
#define CHX_OPTION_RANK_INTERLEAVING 0x1
#define CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE 0x2
#define CHX_OPTION_CH1_CLK_DISABLE 0x4
#define CHX_OPTION_ADDRESS_MAP_2KB 0x10
#define CHX_ODT_CONFIG_DDR3_RX_ODT 0x1
#define CHX_ODT_CONFIG_DDR4_CA_ODT 0x2
#define CHX_ODT_CONFIG_DDR3L_TX_ODT 0x10
#define CHX_MODE2N_AUTO 0
#define CHX_MODE2N_FORCE 1
#define CHX_ODT_LEVELS_CONNECTED_TO_SOC 0x0
#define CHX_ODT_LEVELS_HELD_HIGH 0x1
#define NPK_EN_DISABLE 0
#define NPK_EN_ENABLE 1
#define NPK_EN_DEBUGGER 2
#define NPK_EN_AUTO 3
#define FW_TRACE_DESTINATION_NPK_TRACE_TO_MEMORY 1
#define FW_TRACE_DESTINATION_NPK_TRACE_TO_DCI 2
#define FW_TRACE_DESTINATION_NPK_NPK_TRACE_TO_BSSB 3
#define FW_TRACE_DESTINATION_NPK_TRACE_TO_PTI 4
#define MSC_X_WRAP_0 0
#define MSC_X_WRAP_1 1
#define MSC_X_SIZE_0M 0
#define MSC_X_SIZE_1M 1
#define MSC_X_SIZE_8M 2
#define MSC_X_SIZE_64M 3
#define MSC_X_SIZE_128M 4
#define MSC_X_SIZE_256M 5
#define MSC_X_SIZE_512M 6
#define MSC_X_SIZE_1GB 7
#define PTI_MODE_0 0
#define PTI_MODE_x4 1
#define PTI_MODE_x8 2
#define PTI_MODE_x12 3
#define PTI_MODE_x16 4
#define PTI_SPEED_FULL 0
#define PTI_SPEED_HALF 1
#define PTI_SPEED_QUARTER 2
#endif

202
arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h
View file

@ -6,6 +6,7 @@
#ifndef __ASM_ARCH_FSP_S_UDP_H
#define __ASM_ARCH_FSP_S_UDP_H
#ifndef __ASSEMBLY__
#include <asm/fsp2/fsp_api.h>
struct __packed fsp_s_config {
@ -288,5 +289,206 @@ struct __packed fsps_upd {
u8 unused_upd_space2[46];
u16 upd_terminator;
};
#endif
#define PROC_TRACE_MEM_SIZE_DISABLE 0xff
#define BOOT_P_STATE_HFM 0
#define BOOT_P_STATE_LFM 1
#define PKG_C_STATE_LIMIT_C0_C1 0
#define PKG_C_STATE_LIMIT_C2 1
#define PKG_C_STATE_LIMIT_C3 2
#define PKG_C_STATE_LIMIT_C6 3
#define PKG_C_STATE_LIMIT_C7 4
#define PKG_C_STATE_LIMIT_C7S 5
#define PKG_C_STATE_LIMIT_C8 6
#define PKG_C_STATE_LIMIT_C9 7
#define PKG_C_STATE_LIMIT_C10 8
#define PKG_C_STATE_LIMIT_CMAX 9
#define PKG_C_STATE_LIMIT_CPU_DEFAULT 254
#define PKG_C_STATE_LIMIT_AUTO 255
#define C_STATE_AUTO_DEMOTION_DISABLE_C1_C3 0
#define C_STATE_AUTO_DEMOTION_ENABLE_C3_C6_C7_TO_C1 1
#define C_STATE_AUTO_DEMOTION_ENABLE_C6_C7_TO_C3 2
#define C_STATE_AUTO_DEMOTION_ENABLE_C6_C7_TO_C1_C3 3
#define C_STATE_UN_DEMOTION_DISABLE_C1_C3 0
#define C_STATE_UN_DEMOTION_ENABLE_C1 1
#define C_STATE_UN_DEMOTION_ENABLE_C3 2
#define C_STATE_UN_DEMOTION_ENABLE_C1_C3 3
#define MAX_CORE_C_STATE_UNLIMITED 0
#define MAX_CORE_C_STATE_C1 1
#define MAX_CORE_C_STATE_C3 2
#define MAX_CORE_C_STATE_C6 3
#define MAX_CORE_C_STATE_C7 4
#define MAX_CORE_C_STATE_C8 5
#define MAX_CORE_C_STATE_C9 6
#define MAX_CORE_C_STATE_C10 7
#define MAX_CORE_C_STATE_CCX 8
#define IPU_ACPI_MODE_DISABLE 0
#define IPU_ACPI_MODE_IGFX_CHILD_DEVICE 1
#define IPU_ACPI_MODE_ACPI_DEVICE 1
#define CD_CLOCK_FREQ_144MHZ 0
#define CD_CLOCK_FREQ_288MHZ 1
#define CD_CLOCK_FREQ_384MHZ 2
#define CD_CLOCK_FREQ_576MHZ 3
#define CD_CLOCK_FREQ_624MHZ 4
#define HDA_IO_BUFFER_OWNERSHIP_HDA_ALL_IO 0
#define HDA_IO_BUFFER_OWNERSHIP_HDA_I2S_SPLIT 1
#define HDA_IO_BUFFER_OWNERSHIP_I2S_ALL_IO 2
#define HDA_IO_BUFFER_VOLTAGE_3V3 0
#define HDA_IO_BUFFER_VOLTAGE_1V8 1
#define HDA_VC_TYPE_VC0 0
#define HDA_VC_TYPE_VC1 1
#define HDA_LINK_FREQ_6MHZ 0
#define HDA_LINK_FREQ_12MHZ 1
#define HDA_LINK_FREQ_24MHZ 2
#define HDA_LINK_FREQ_48MHZ 3
#define HDA_LINK_FREQ_96MHZ 4
#define HDA_LINK_FREQ_INVALID 5
#define HDA_I_DISP_LINK_FREQ_6MHZ 0
#define HDA_I_DISP_LINK_FREQ_12MHZ 1
#define HDA_I_DISP_LINK_FREQ_24MHZ 2
#define HDA_I_DISP_LINK_FREQ_48MHZ 3
#define HDA_I_DISP_LINK_FREQ_96MHZ 4
#define HDA_I_DISP_LINK_FREQ_INVALID 5
#define HDA_I_DISP_LINK_T_MODE_2T 0
#define HDA_I_DISP_LINK_T_MODE_1T 1
#define HDA_DISP_DMIC_DISABLE 0
#define HDA_DISP_DMIC_2CH_ARRAY 1
#define HDA_DISP_DMIC_4CH_ARRAY 2
#define HDA_CSE_MEM_TRANSFERS_VC0 0
#define HDA_CSE_MEM_TRANSFERS_VC2 1
#define HDA_HOST_MEM_TRANSFERS_VC0 0
#define HDA_HOST_MEM_TRANSFERS_VC2 1
#define HDA_DSP_FEATURE_MASK_WOV 0x1
#define HDA_DSP_FEATURE_MASK_BT_SIDEBAND 0x2
#define HDA_DSP_FEATURE_MASK_CODEC_VAD 0x4
#define HDA_DSP_FEATURE_MASK_BT_INTEL_HFP 0x20
#define HDA_DSP_FEATURE_MASK_BT_INTEL_A2DP 0x40
#define HDA_DSP_FEATURE_MASK_DSP_BASED_PRE_PROC_DISABLE 0x80
#define HDA_DSP_PP_MODULE_MASK_WOV 0x1
#define HDA_DSP_PP_MODULE_MASK_BT_SIDEBAND 0x2
#define HDA_DSP_PP_MODULE_MASK_CODEC_VAD 0x4
#define HDA_DSP_PP_MODULE_MASK_BT_INTEL_HFP 0x20
#define HDA_DSP_PP_MODULE_MASK_BT_INTEL_A2DP 0x40
#define HDA_DSP_PP_MODULE_MASK_DSP_BASED_PRE_PROC_DISABLE 0x80
#define I2CX_ENABLE_DISABLED 0
#define I2CX_ENABLE_PCI_MODE 1
#define I2CX_ENABLE_ACPI_MODE 2
#define HSUARTX_ENABLE_DISABLED 0
#define HSUARTX_ENABLE_PCI_MODE 1
#define HSUARTX_ENABLE_ACPI_MODE 2
#define SPIX_ENABLE_DISABLED 0
#define SPIX_ENABLE_PCI_MODE 1
#define SPIX_ENABLE_ACPI_MODE 2
#define PCIE_RP_SPEED_AUTO 0
#define PCIE_RP_SPEED_GEN1 1
#define PCIE_RP_SPEED_GEN2 2
#define PCIE_RP_SPEED_GEN3 3
#define PCIE_RP_ASPM_DISABLE 0
#define PCIE_RP_ASPM_L0S 1
#define PCIE_RP_ASPM_L1 2
#define PCIE_RP_ASPM_L0S_L1 3
#define PCIE_RP_ASPM_AUTO 4
#define PCIE_RP_L1_SUBSTATES_DISABLE 0
#define PCIE_RP_L1_SUBSTATES_L1_1 1
#define PCIE_RP_L1_SUBSTATES_L1_2 2
#define PCIE_RP_L1_SUBSTATES_L1_1_L1_2 3
#define SATA_MODE_AHCI 0
#define SATA_MODE_RAID 1
#define SATA_SPEED_LIMIT_SC_SATA_SPEED 0
#define SATA_SPEED_LIMIT_1_5GBS 1
#define SATA_SPEED_LIMIT_3GBS 2
#define SATA_SPEED_LIMIT_6GBS 3
#define SATA_PORT_SOLID_STATE_DRIVE_HARD_DISK_DRIVE 0
#define SATA_PORT_SOLID_STATE_DRIVE_SOLID_STATE_DRIVE 1
#define CRID_SETTING_DISABLE 0
#define CRID_SETTING_CRID_1 1
#define CRID_SETTING_CRID_2 2
#define CRID_SETTING_CRID_3 3
#define RESET_SELECT_WARM_RESET 0x6
#define RESET_SELECT_COLD_RESET 0xe
#define EMMC_HOST_SPEED_MAX_HS400 0
#define EMMC_HOST_SPEED_MAX_HS200 1
#define EMMC_HOST_SPEED_MAX_DDR50 2
#define SERIAL_IRQ_MODE_QUIET_MODE 0
#define SERIAL_IRQ_MODE_CONTINUOUS_MODE 1
#define START_FRAME_PULSE_WIDTH_SCSFPW4CLK 0
#define START_FRAME_PULSE_WIDTH_SCSFPW6CLK 1
#define START_FRAME_PULSE_WIDTH_SCSFPW8CLK 1
#define USB30_MODE_DISABLE 0
#define USB30_MODE_ENABLE 1
#define USB30_MODE_AUTO 2
#define USB_OTG_DISABLE 0
#define USB_OTG_PCI_MODE 1
#define USB_OTG_ACPI_MODE 2
#define SSIC_RATE_A_SERIES 1
#define SSIC_RATE_B_SERIES 2
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_DISABLE 0
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_ENABLE 1
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MODE_AUTO 2
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1NS 0
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32NS 1
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1024NS 2
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32768NS 3
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1048576NS 4
#define PCIE_RP_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_33554432NS 5
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_DISABLE 0
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_ENABLE 1
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MODE_AUTO 2
#define PWR_BTN_OVERRIDE_PERIOD_4S 0
#define PWR_BTN_OVERRIDE_PERIOD_6S 1
#define PWR_BTN_OVERRIDE_PERIOD_8S 2
#define PWR_BTN_OVERRIDE_PERIOD_10S 3
#define PWR_BTN_OVERRIDE_PERIOD_12S 4
#define PWR_BTN_OVERRIDE_PERIOD_14S 5
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1NS 0
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32NS 1
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1024NS 2
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_32768NS 3
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_1048576NS 4
#define PCIE_RP_NON_SNOOP_LATENCY_OVERRIDE_MULTIPLIER_33554432NS 5
#define PCIE_RP_SELECTABLE_DEEMPHASIS_6_DB 0
#define PCIE_RP_SELECTABLE_DEEMPHASIS_3_5_DB 1
#endif

110
arch/x86/include/asm/arch-apollolake/fsp_bindings.h Normal file
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@ -0,0 +1,110 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2019 Google LLC
* Copyright 2020 B&R Industrial Automation GmbH - http://www.br-automation.com
*/
#ifndef __ASM_ARCH_FSP_BINDINGS_H
#define __ASM_ARCH_FSP_BINDINGS_H
#include <asm/arch/fsp/fsp_m_upd.h>
#include <asm/arch/fsp/fsp_s_upd.h>
#define ARRAY_SIZE_OF_MEMBER(s, m) (ARRAY_SIZE((((s *)0)->m)))
#define SIZE_OF_MEMBER(s, m) (sizeof((((s *)0)->m)))
enum conf_type {
FSP_UINT8,
FSP_UINT16,
FSP_UINT32,
FSP_STRING,
FSP_LPDDR4_SWIZZLE,
};
/**
* struct fsp_binding - Binding describing devicetree/FSP relationships
* @offset: Offset within the FSP config structure
* @propname: Name of property to read
* @type: Type of the property to read
* @count: If the property is expected to be an array, this is the
* number of expected elements
* Set to 0 if the property is expected to be a scalar
*
* The struct fsp_binding is used to describe the relationship between
* values stored in devicetree and where they are placed in the FSP
* configuration structure.
*/
struct fsp_binding {
size_t offset;
char *propname;
enum conf_type type;
size_t count;
};
/*
* LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation.
* There are four physical LPDDR4 channels, each 32-bits wide. There are two
* logical channels using two physical channels together to form a 64-bit
* interface to memory for each logical channel.
*/
enum {
LP4_PHYS_CH0A,
LP4_PHYS_CH0B,
LP4_PHYS_CH1A,
LP4_PHYS_CH1B,
LP4_NUM_PHYS_CHANNELS,
};
/*
* The DQs within a physical channel can be bit-swizzled within each byte.
* Within a channel the bytes can be swapped, but the DQs need to be routed
* with the corresponding DQS (strobe).
*/
enum {
LP4_DQS0,
LP4_DQS1,
LP4_DQS2,
LP4_DQS3,
LP4_NUM_BYTE_LANES,
DQ_BITS_PER_DQS = 8,
};
/* Provide bit swizzling per DQS and byte swapping within a channel */
struct lpddr4_chan_swizzle_cfg {
u8 dqs[LP4_NUM_BYTE_LANES][DQ_BITS_PER_DQS];
};
struct lpddr4_swizzle_cfg {
struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS];
};
/**
* fsp_m_update_config_from_dtb() - Read FSP-M config from devicetree node
* @node: Valid node reference to read property from
* @cfg: Pointer to FSP-M config structure
* @return 0 on success, -ve on error
*
* This function reads the configuration for FSP-M from the provided
* devicetree node and saves it in the FSP-M configuration structure.
* Configuration options that are not present in the devicetree are
* left at their current value.
*/
int fsp_m_update_config_from_dtb(ofnode node, struct fsp_m_config *cfg);
/**
* fsp_s_update_config_from_dtb() - Read FSP-S config from devicetree node
* @node: Valid node reference to read property from
* @cfg: Pointer to FSP-S config structure
* @return 0 on success, -ve on error
*
* This function reads the configuration for FSP-S from the provided
* devicetree node and saves it in the FSP-S configuration structure.
* Configuration options that are not present in the devicetree are
* left at their current value.
*/
int fsp_s_update_config_from_dtb(ofnode node, struct fsp_s_config *cfg);
#endif

2
arch/x86/include/asm/arch-coreboot/sysinfo.h
View file

@ -49,6 +49,8 @@ struct sysinfo_t {
u32 vdat_size;
void *tstamp_table;
void *cbmem_cons;
u64 smbios_start;
u32 smbios_size;
struct cb_serial *serial;
};

11
arch/x86/include/asm/coreboot_tables.h
View file

@ -214,6 +214,17 @@ struct cb_vbnv {
uint32_t vbnv_size;
};
#define CB_TAG_CBMEM_ENTRY 0x0031
#define CBMEM_ID_SMBIOS 0x534d4254
struct cb_cbmem_entry {
uint32_t tag;
uint32_t size;
uint64_t address;
uint32_t entry_size;
uint32_t id;
};
#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
struct cb_cmos_option_table {

3
arch/x86/lib/fsp2/fsp_init.c
View file

@ -81,11 +81,10 @@ static int get_cbfs_fsp(enum fsp_type_t type, ulong map_base,
* 'COREBOOT' (CBFS, size 1814528, offset 2117632).
*/
ulong cbfs_base = 0x205000;
ulong cbfs_size = 0x1bb000;
struct cbfs_priv *cbfs;
int ret;
ret = cbfs_init_mem(map_base + cbfs_base, cbfs_size, &cbfs);
ret = cbfs_init_mem(map_base + cbfs_base, &cbfs);
if (ret)
return ret;
if (!ret) {

3
cmd/cbfs.c
View file

@ -28,8 +28,7 @@ static int do_cbfs_init(struct cmd_tbl *cmdtp, int flag, int argc,
return 1;
}
}
file_cbfs_init(end_of_rom);
if (cbfs_get_result() != CBFS_SUCCESS) {
if (file_cbfs_init(end_of_rom)) {
printf("%s.\n", file_cbfs_error());
return 1;
}

1
cmd/x86/mtrr.c
View file

@ -73,7 +73,6 @@ static int do_mtrr_set(uint reg, int argc, char *const argv[])
if (valid)
mask |= MTRR_PHYS_MASK_VALID;
printf("base=%llx, mask=%llx\n", base, mask);
mtrr_open(&state, true);
wrmsrl(MTRR_PHYS_BASE_MSR(reg), base);
wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask);

320
doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt Normal file
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@ -0,0 +1,320 @@
* Intel FSP-M configuration
Several Intel platforms require the execution of the Intel FSP (Firmware
Support Package) for initialization. The FSP consists of multiple parts, one
of which is the FSP-M (Memory initialization phase).
This binding applies to the FSP-M for the Intel Apollo Lake SoC.
The FSP-M is available on Github [1].
For detailed information on the FSP-M parameters see the documentation in
FSP/ApolloLakeFspBinPkg/Docs [2].
The properties of this binding are all optional. If no properties are set the
values of the FSP-M are used.
[1] https://github.com/IntelFsp/FSP
[2] https://github.com/IntelFsp/FSP/tree/master/ApolloLakeFspBinPkg/Docs
Optional properties:
- fspm,serial-debug-port-address: Debug Serial Port Base address
- fspm,serial-debug-port-type: Debug Serial Port Type
0: NONE
1: I/O
2: MMIO (default)
- fspm,serial-debug-port-device: Serial Port Debug Device
0: SOC UART0
1: SOC UART1
2: SOC UART2 (default)
3: External Device
- fspm,serial-debug-port-stride-size: Debug Serial Port Stride Size
0: 1
2: 4 (default)
- fspm,mrc-fast-boot: Memory Fast Boot
- fspm,igd: Integrated Graphics Device
- fspm,igd-dvmt50-pre-alloc: DVMT Pre-Allocated
0x02: 64 MB (default)
0x03: 96 MB
0x04: 128 MB
0x05: 160 MB
0x06: 192 MB
0x07: 224 MB
0x08: 256 MB
0x09: 288 MB
0x0A: 320 MB
0x0B: 352 MB
0x0C: 384 MB
0x0D: 416 MB
0x0E: 448 MB
0x0F: 480 MB
0x10: 512 MB
- fspm,aperture-size: Aperture Size
0x1: 128 MB (default)
0x2: 256 MB
0x3: 512 MB
- fspm,gtt-size: GTT Size
0x1: 2 MB
0x2: 4 MB
0x3: 8 MB (default)
- fspm,primary-video-adaptor: Primary Display
0x0: AUTO (default)
0x2: IGD
0x3: PCI
- fspm,package: Package
0x0: SODIMM (default)
0x1: BGA
0x2: BGA mirrored (LPDDR3 only)
0x3: SODIMM/UDIMM with Rank 1 Mirrored (DDR3L)
- fspm,profile: Profile
0x01: WIO2_800_7_8_8
0x02: WIO2_1066_9_10_10
0x03: LPDDR3_1066_8_10_10
0x04: LPDDR3_1333_10_12_12
0x05: LPDDR3_1600_12_15_15
0x06: LPDDR3_1866_14_17_17
0x07: LPDDR3_2133_16_20_20
0x08: LPDDR4_1066_10_10_10
0x09: LPDDR4_1600_14_15_15
0x0A: LPDDR4_2133_20_20_20
0x0B: LPDDR4_2400_24_22_22
0x0C: LPDDR4_2666_24_24_24
0x0D: LPDDR4_2933_28_27_27
0x0E: LPDDR4_3200_28_29_29
0x0F: DDR3_1066_6_6_6
0x10: DDR3_1066_7_7_7
0x11: DDR3_1066_8_8_8
0x12: DDR3_1333_7_7_7
0x13: DDR3_1333_8_8_8
0x14: DDR3_1333_9_9_9
0x15: DDR3_1333_10_10_10
0x16: DDR3_1600_8_8_8
0x17: DDR3_1600_9_9_9
0x18: DDR3_1600_10_10_10
0x19: DDR3_1600_11_11_11 (default)
0x1A: DDR3_1866_10_10_10
0x1B: DDR3_1866_11_11_11
0x1C: DDR3_1866_12_12_12
0x1D: DDR3_1866_13_13_13
0x1E: DDR3_2133_11_11_11
0x1F: DDR3_2133_12_12_12
0x20: DDR3_2133_13_13_13
0x21: DDR3_2133_14_14_14
0x22: DDR4_1333_10_10_10
0x23: DDR4_1600_10_10_10
0x24: DDR4_1600_11_11_11
0x25: DDR4_1600_12_12_12
0x26: DDR4_1866_12_12_12
0x27: DDR4_1866_13_13_13
0x28: DDR4_1866_14_14_14
0x29: DDR4_2133_14_14_14
0x2A: DDR4_2133_15_15_15
0x2B: DDR4_2133_16_16_16
0x2C: DDR4_2400_15_15_15
0x2D: DDR4_2400_16_16_16
0x2E: DDR4_2400_17_17_17
0x2F: DDR4_2400_18_18_18
- fspm,memory-down: Memory Down
0x0: No (default)
0x1: Yes
0x2: 1MD+SODIMM (for DDR3L only) ACRD
0x3: 1x32 LPDDR4
- fspm,ddr3l-page-size: DDR3LPageSize
0x1: 1KB (default)
0x2: 2KB
- fspm,ddr3-lasr: DDR3LASR
- fspm,scrambler-support: ScramblerSupport
- fspm,interleaved-mode: InterleavedMode
- fspm,channel-hash-mask: ChannelHashMask
- fspm,fspm,slice-hash-mask: SliceHashMask
- fspm,channels-slices-enable: ChannelsSlices
- fspm,min-ref-rate2x-enable: MinRefRate2x
- fspm,dual-rank-support-enable: DualRankSupport
- fspm,rmt-mode: RmtMode
- fspm,memory-size-limit: MemorySizeLimit
- fspm,low-memory-max-value: LowMemoryMaxValue
- fspm,high-memory-max-value: HighMemoryMaxValue
- fspm,disable-fast-boot: FastBoot
- fspm,dimm0-spd-address: DIMM0 SPD Address
- fspm,dimm1-spd-address: DIMM1 SPD Address
- fspm,chX-rank-enable: Must be set to enable rank (X = 0-3)
- fspm,chX-device-width: DRAM device width per DRAM channel (X = 0-3)
0: x8
1: x16
2: x32
3: x64
- fspm,chX-dram-density: Must specify the DRAM device density (X = 0-3)
0: 4Gb
1: 6Gb
2: 8Gb
3: 12Gb
4: 16Gb
5: 2Gb
- fspm,chX-option: Channel options (X = 0-3)
- fspm,chX-odt-config: Channel Odt Config (X = 0-3)
- fspm,chX-mode2-n: Force 2N Mode (X = 0-3)
0x0: Auto
0x1: Force 2N CMD Timing Mode
- fspm,chX-odt-levels: Channel Odt Levels (X = 0-3)
0: ODT Connected to SoC
1: ODT held high
- fspm,rmt-check-run: RmtCheckRun
- fspm,rmt-margin-check-scale-high-threshold: RmtMarginCheckScaleHighThreshold
- fspm,ch-bit-swizzling: Bit_swizzling
- fspm,msg-level-mask: MsgLevelMask
- fspm,pre-mem-gpio-table-pin-num: PreMem GPIO Pin Number for each table
- fspm,pre-mem-gpio-table-ptr: PreMem GPIO Table Pointer
- fspm,pre-mem-gpio-table-entry-num: PreMem GPIO Table Entry Number
- fspm,enhance-port8xh-decoding: Enhance the port 8xh decoding
- fspm,spd-write-enable: SPD Data Write
- fspm,mrc-data-saving: MRC Training Data Saving
- fspm,oem-loading-base: OEM File Loading Address
- fspm,oem-file-name: OEM File Name to Load
- fspm,mrc-boot-data-ptr:
- fspm,e-mmc-trace-len: eMMC Trace Length
0x0: Long
0x1: Short
- fspm,skip-cse-rbp: Skip CSE RBP to support zero sized IBB
- fspm,npk-en: Npk Enable
0: Disable
1: Enable
2: Debugger
3: Auto (default)
- fspm,fw-trace-en: FW Trace Enable
- fspm,fw-trace-destination: FW Trace Destination
1: NPK_TRACE_TO_MEMORY
2: NPK_TRACE_TO_DCI
3: NPK_TRACE_TO_BSSB
4: NPK_TRACE_TO_PTI (default)
- fspm,recover-dump: NPK Recovery Dump
- fspm,msc0-wrap: Memory Region 0 Buffer WrapAround
0: n0-warp
1: n1-warp (default)
- fspm,msc1-wrap: Memory Region 1 Buffer WrapAround
0: n0-warp
1: n1-warp (default)
- fspm,msc0-size: Memory Region 0 Buffer Size
0: 0MB (default)
1: 1MB
2: 8MB
3: 64MB
4: 128MB
5: 256MB
6: 512MB
7: 1GB
- fspm,msc1-size: Memory Region 1 Buffer Size
0: 0MB (default)
1: 1MB
2: 8MB
3: 64MB
4: 128MB
5: 256MB
6: 512MB
7: 1GB
- fspm,pti-mode: PTI Mode
0: 0ff
1: x4 (default)
2: x8
3: x12
4: x16
- fspm,pti-training: PTI Training
0: off (default)
1-6: 1-6
- fspm,pti-speed:
0: full
1: half
2: quarter (default)
- fspm,punit-mlvl: Punit Message Level
0:
1: (default)
2-4: 2-4
- fspm,pmc-mlvl: PMC Message Level
0:
1: (default)
2-4: 2-4
- fspm,sw-trace-en: SW Trace Enable
- fspm,periodic-retraining-disable: Periodic Retraining Disable
- fspm,enable-reset-system: Enable Reset System
- fspm,enable-s3-heci2: Enable HECI2 in S3 resume path
- fspm,variable-nvs-buffer-ptr:
Example:
&host_bridge {
fspm,package = <PACKAGE_BGA>;
fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>;
fspm,memory-down = <MEMORY_DOWN_YES>;
fspm,scrambler-support = <1>;
fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>;
fspm,channel-hash-mask = <0x36>;
fspm,slice-hash-mask = <0x9>;
fspm,low-memory-max-value = <2048>;
fspm,ch0-rank-enable = <1>;
fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>;
fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>;
fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING |
CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
fspm,ch1-rank-enable = <1>;
fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>;
fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>;
fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING |
CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
fspm,ch2-rank-enable = <1>;
fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>;
fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>;
fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING |
CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
fspm,ch3-rank-enable = <1>;
fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>;
fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>;
fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING |
CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
fspm,fspm,skip-cse-rbp = <1>;
fspm,ch-bit-swizzling = /bits/ 8 <
/* LP4_PHYS_CH0A */
/* DQA[0:7] pins of LPDDR4 module */
6 7 5 4 3 1 0 2
/* DQA[8:15] pins of LPDDR4 module */
12 10 11 13 14 8 9 15
/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
16 22 23 20 18 17 19 21
/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
30 28 29 25 24 26 27 31
/* LP4_PHYS_CH0B */
/* DQA[0:7] pins of LPDDR4 module */
7 3 5 2 6 0 1 4
/* DQA[8:15] pins of LPDDR4 module */
9 14 12 13 10 11 8 15
/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
20 22 23 16 19 17 18 21
/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
28 24 26 27 29 30 31 25
/* LP4_PHYS_CH1A */
/* DQA[0:7] pins of LPDDR4 module */
2 1 6 7 5 4 3 0
/* DQA[8:15] pins of LPDDR4 module */
11 10 8 9 12 15 13 14
/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
17 23 19 16 21 22 20 18
/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
31 29 26 25 28 27 24 30
/* LP4_PHYS_CH1B */
/* DQA[0:7] pins of LPDDR4 module */
4 3 7 5 6 1 0 2
/* DQA[8:15] pins of LPDDR4 module */
15 9 8 11 14 13 12 10
/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
20 23 22 21 18 19 16 17
/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
25 28 30 31 26 27 24 29>;
};

483
doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt Normal file
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@ -0,0 +1,483 @@
* Intel FSP-S configuration
Several Intel platforms require the execution of the Intel FSP (Firmware
Support Package) for initialization. The FSP consists of multiple parts, one
of which is the FSP-S (Silicon initialization phase).
This binding applies to the FSP-S for the Intel Apollo Lake SoC.
The FSP-S is available on Github [1].
For detailed information on the FSP-S parameters see the documentation in
FSP/ApolloLakeFspBinPkg/Docs [2].
The properties of this binding are all optional. If no properties are set the
values of the FSP-S are used.
[1] https://github.com/IntelFsp/FSP
[2] https://github.com/IntelFsp/FSP/tree/master/ApolloLakeFspBinPkg/Docs
Optional properties:
- fsps,active-processor-cores: ActiveProcessorCores
- fsps,disable-core1: Disable Core1
- fsps,disable-core2: Disable Core2
- fsps,disable-core2: Disable Core3
- fsps,vmx-enable: VMX Enable
- fsps,proc-trace-mem-size: Memory region allocation for Processor Trace
0xFF: Disable (default)
- fsps,proc-trace-enable: Enable Processor Trace
- fsps,eist: Eist
- fsps,boot-p-state: Boot PState
0: HFM (default)
1: LFM
- fsps,enable-cx: CPU power states (C-states)
- fsps,c1e: Enhanced C-states
- fsps,bi-proc-hot: Bi-Directional PROCHOT#
- fsps,pkg-c-state-limit: Max Pkg Cstate
0: PkgC0C1
1: PkgC2
2: PkgC3 (default)
3: PkgC6
4: PkgC7
5: PkgC7s
6: PkgC8
7: PkgC9
8: PkgC10
9: PkgCMax
254: PkgCpuDefault
255: PkgAuto
- fsps,c-state-auto-demotion: C-State auto-demotion
0: Disable C1 and C3 Auto-demotion (default)
1: Enable C3/C6/C7 Auto-demotion to C1
2: Enable C6/C7 Auto-demotion to C3
3: Enable C6/C7 Auto-demotion to C1 and C3
- fsps,c-state-un-demotion: C-State un-demotion
0: Disable C1 and C3 Un-demotion (default)
1: Enable C1 Un-demotion
2: Enable C3 Un-demotion
3: Enable C1 and C3 Un-demotion
- fsps,max-core-c-state: Max Core C-State
0: Unlimited
1: C1
2: C3
3: C6
4: C7
5: C8
6: C9
7: C10
8: CCx (default)
- fsps,pkg-c-state-demotion: Package C-State Demotion
- fsps,pkg-c-state-un-demotion: Package C-State Un-demotion
- fsps,turbo-mode: Turbo Mode
- fsps,hda-verb-table-entry-num: SC HDA Verb Table Entry Number
0: (default)
- fsps,hda-verb-table-ptr: SC HDA Verb Table Pointer
0x00000000: (default)
- fsps,p2sb-unhide: Enable/Disable P2SB device hidden
- fsps,ipu-en: IPU Enable/Disable
- fsps,ipu-acpi-mode: IMGU ACPI mode selection
0: Auto
1: IGFX Child device (default)
2: ACPI device
- fsps,force-wake: Enable ForceWake
- fsps,gtt-mm-adr: GttMmAdr
0xbf000000: (default)
- fsps,gm-adr: GmAdr
0xa0000000: (default)
- fsps,pavp-lock: Enable PavpLock
- fsps,graphics-freq-modify: Enable GraphicsFreqModify
- fsps,graphics-freq-req: Enable GraphicsFreqReq
- fsps,graphics-video-freq: Enable GraphicsVideoFreq
- fsps,pm-lock: Enable PmLock
- fsps,dop-clock-gating: Enable DopClockGating
- fsps,unsolicited-attack-override: Enable UnsolicitedAttackOverride
- fsps,wopcm-support: Enable WOPCMSupport
- fsps,wopcm-size: Enable WOPCMSize
- fsps,power-gating: Enable PowerGating
- fsps,unit-level-clock-gating: Enable UnitLevelClockGating
- fsps,fast-boot: Enable FastBoot
- fsps,dyn-sr: Enable DynSR
- fsps,sa-ipu-enable: Enable SaIpuEnable
- fsps,pm-support: GT PM Support
- fsps,enable-render-standby: RC6(Render Standby)
- fsps,logo-size: BMP Logo Data Size
- fsps,logo-ptr: BMP Logo Data Pointer
- fsps,graphics-config-ptr: Graphics Configuration Data Pointer
- fsps,pavp-enable: PAVP Enable
- fsps,pavp-pr3: PAVP PR3
- fsps,cd-clock: CdClock Frequency selection
0: 144MHz
1: 288MHz
2: 384MHz
3: 576MHz
4: 624MHz (default)
- fsps,pei-graphics-peim-init: Enable/Disable PeiGraphicsPeimInit
- fsps,write-protection-enable: Write Protection Support
- fsps,read-protection-enable: Read Protection Support
- fsps,protected-range-limit: Protected Range Limitation
0x0FFF: (default)
- fsps,protected-range-base: Protected Range Base
0x0000: (default)
- fsps,gmm: Enable SC Gaussian Mixture Models
- fsps,clk-gating-pgcb-clk-trunk: GMM Clock Gating - PGCB Clock Trunk
- fsps,clk-gating-sb: GMM Clock Gating - Sideband
- fsps,clk-gating-sb-clk-trunk: GMM Clock Gating - Sideband
- fsps,clk-gating-sb-clk-partition: GMM Clock Gating - Sideband Clock
Partition
- fsps,clk-gating-core: GMM Clock Gating - Core
- fsps,clk-gating-dma: GMM Clock Gating - DMA
- fsps,clk-gating-reg-access: GMM Clock Gating - Register Access
- fsps,clk-gating-host: GMM Clock Gating - Host
- fsps,clk-gating-partition: GMM Clock Gating - Partition
- fsps,clk-gating-trunk: Clock Gating - Trunk
- fsps,hda-enable: HD Audio Support
- fsps,dsp-enable: HD Audio DSP Support
- fsps,pme: Azalia wake-on-ring
- fsps,hd-audio-io-buffer-ownership: HD-Audio I/O Buffer Ownership
0: HD-Audio link owns all the I/O buffers (default)
1: HD-Audio link owns 4 I/O buffers and I2S port owns 4 I/O buffers
3: I2S port owns all the I/O buffers
- fsps,hd-audio-io-buffer-voltage: HD-Audio I/O Buffer Voltage
0: 3.3V (default)
1: 1.8V
- fsps,hd-audio-vc-type: HD-Audio Virtual Channel Type
0: VC0 (default)
1: VC1
- fsps,hd-audio-link-frequency: HD-Audio Link Frequency
0: 6MHz (default)
1: 12MHz
2: 24MHz
3: 48MHz
4: 96MHz
5: Invalid
- fsps,hd-audio-i-disp-link-frequency: HD-Audio iDisp-Link Frequency
0: 6MHz (default)
1: 12MHz
2: 24MHz
3: 48MHz
4: 96MHz
5: Invalid
- fsps,hd-audio-i-disp-link-tmode: HD-Audio iDisp-Link T-Mode
0: 2T (default)
1: 1T
- fsps,dsp-endpoint-dmic: HD-Audio Disp DMIC
0: disable,
1: 2ch array (default)
2: 4ch array
- fsps,dsp-endpoint-bluetooth: HD-Audio Bluetooth
- fsps,dsp-endpoint-i2s-skp: HD-Audio I2S SHK
- fsps,dsp-endpoint-i2s-hp: HD-Audio I2S HP
- fsps,audio-ctl-pwr-gate: HD-Audio Controller Power Gating (deprecated)
- fsps,audio-dsp-pwr-gate: HD-Audio ADSP Power Gating (deprecated)
- fsps,mmt: HD-Audio CSME Memory Transfers
0: VC0 (default)
1: VC2
- fsps,hmt: HD-Audio Host Memory Transfers
0: VC0 (default)
1: VC2
- fsps,hd-audio-pwr-gate: HD-Audio Power Gating
- fsps,hd-audio-clk-gate: HD-Audio Clock Gating
- fsps,dsp-feature-mask: Bitmask of DSP Feature
0x01: WoV
0x02: BT Sideband
0x04: Codec VAD
0x20: BT Intel HFP
0x40: BT Intel A2DP
0x80: DSP based speech pre-processing disabled
- fsps,dsp-pp-module-mask: Bitmask of supported DSP Post-Processing Modules
0x01: WoV
0x02: BT Sideband
0x04: Codec VAD
0x20: BT Intel HFP
0x40: BT Intel A2DP
0x80: DSP based speech pre-processing disabled
- fsps,bios-cfg-lock-down: HD-Audio BIOS Configuration Lock Down
- fsps,hpet: Enable High Precision Timer
- fsps,hpet-bdf-valid: Hpet Valid BDF Value
- fsps,hpet-bus-number: Bus Number of Hpet
0xFA: (default)
- fsps,hpet-device-number: Device Number of Hpet
0x1F: (default)
- fsps,hpet-function-number: Function Number of Hpet
0x00: (default)
- fsps,io-apic-bdf-valid: IoApic Valid BDF Value
- fsps,io-apic-bus-number: Bus Number of IoApic
0xFA: (default)
- fsps,io-apic-device-number: Device Number of IoApic
0x0F: (default)
- fsps,io-apic-function-number: Function Number of IoApic
0x00: (default)
- fsps,io-apic-entry24-119: IOAPIC Entry 24-119
- fsps,io-apic-id: IO APIC ID
0x01: (default)
- fsps,io-apic-range-select: IoApic Range
0x00: (default)
- fsps,ish-enable: ISH Controller
- fsps,bios-interface: BIOS Interface Lock Down
- fsps,bios-lock: Bios LockDown Enable
- fsps,spi-eiss: SPI EISS Status
- fsps,bios-lock-sw-smi-number: BiosLock SWSMI Number
0xA9: (default)
- fsps,lpss-s0ix-enable: LPSS IOSF PMCTL S0ix Enable
- fsps,i2c-clk-gate-cfg: LPSS I2C Clock Gating Configuration
- fsps,hsuart-clk-gate-cfg: LPSS HSUART Clock Gating Configuration
- fsps,spi-clk-gate-cfg: LPSS SPI Clock Gating Configuration
- fsps,i2cX-enable: 2C Device X
0: Disabled
1: PCI Mode (default)
2: ACPI Mode
- fsps,hsuartX-enable: UART Device X
0: Disabled
1: PCI Mode (default)
2: ACPI Mode
- fsps,spiX-enable: SPI UART Device X
0: Disabled
1: PCI Mode (default)
2: ACPI Mode
- fsps,os-dbg-enable: OS Debug Feature
- fsps,dci-en: DCI Feature
- fsps,uart2-kernel-debug-base-address: UART Debug Base Address
0x00000000: (default)
- fsps,pcie-clock-gating-disabled: Enable PCIE Clock Gating
- fsps,pcie-root-port8xh-decode: Enable PCIE Root Port 8xh Decode
- fsps,pcie8xh-decode-port-index: PCIE 8xh Decode Port Index
0x00: (default)
- fsps,pcie-root-port-peer-memory-write-enable: Enable PCIE Root Port Peer
Memory Write
- fsps,pcie-aspm-sw-smi-number: PCIE SWSMI Number
0xAA: (default)
- fsps,pcie-root-port-en: PCI Express Root Port
- fsps,pcie-rp-hide: Hide PCIE Root Port Configuration Space
- fsps,pcie-rp-slot-implemented: PCIE Root Port Slot Implement
- fsps,pcie-rp-hot-plug: Hot Plug
- fsps,pcie-rp-pm-sci: PCIE PM SCI
- fsps,pcie-rp-ext-sync: PCIE Root Port Extended Sync
- fsps,pcie-rp-transmitter-half-swing: Transmitter Half Swing
- fsps,pcie-rp-acs: ACS
- fsps,pcie-rp-clk-req-supported: Clock Request Support
- fsps,pcie-rp-clk-req-number: Configure CLKREQ Number
- fsps,pcie-rp-clk-req-detect: CLKREQ# Detection
- fsps,advanced-error-reportingt: Advanced Error Reporting
- fsps,pme-interrupt: PME Interrupt
- fsps,fatal-error-report: URR
- fsps,no-fatal-error-report: FER
- fsps,correctable-error-report: NFER
- fsps,system-error-on-fatal-error: CER
- fsps,system-error-on-non-fatal-error: SEFE
- fsps,system-error-on-correctable-error: SENFE
- fsps,pcie-rp-speed: SECE
- fsps,physical-slot-number: PCIe Speed
0: Auto (default)
1: Gen1
2: Gen2
3: Gen3
- fsps,pcie-rp-completion-timeout: Physical Slot Number
0x00, 0x01, 0x02, 0x03, 0x04, 0x05 (default)
- fsps,enable-ptm: PTM Support
- fsps,pcie-rp-aspm: ASPM
- fsps,pcie-rp-l1-substates: L1 Substates
- fsps,pcie-rp-ltr-enable: PCH PCIe LTR
- fsps,pcie-rp-ltr-config-lock: PCIE LTR Lock
- fsps,pme-b0-s5-di: PME_B0_S5 Disable bit
- fsps,pci-clock-run: PCI Clock Run
- fsps,timer8254-clk-setting: Enable/Disable Timer 8254 Clock Setting
- fsps,enable-sata: Chipset SATA
- fsps,sata-mode: SATA Mode Selection
0: AHCI (default)
1: RAID
- fsps,sata-salp-support: Aggressive LPM Support
- fsps,sata-pwr-opt-enable: SATA Power Optimization
- fsps,e-sata-speed-limit: eSATA Speed Limit
- fsps,speed-limit: SATA Speed Limit
0x1: 1.5Gb/s(Gen 1)
0x2: 3Gb/s(Gen 2)
0x3: 6Gb/s(Gen 3)
- fsps,sata-ports-enable: SATA Port
- fsps,sata-ports-dev-slp: SATA Port DevSlp
- fsps,sata-ports-hot-plug: SATA Port HotPlug
- fsps,sata-ports-interlock-sw: Mechanical Presence Switch
- fsps,sata-ports-external: External SATA Ports
- fsps,sata-ports-spin-up: Spin Up Device
- fsps,sata-ports-solid-state-drive: SATA Solid State
0: Hard Disk Drive (default)
1: Solid State Drive
- fsps,sata-ports-enable-dito-config: DITO Configuration
- fsps,sata-ports-dm-val: DM Value
0x0F: Maximum (default)
- fsps,sata-ports-dito-val: DITO Value
0x0271 (default)
- fsps,sub-system-vendor-id: Subsystem Vendor ID
0x8086: (default)
- fsps,sub-system-id: Subsystem ID
0x7270: (default)
- fsps,crid-setting: CRIDSettings
0: Disable (default)
1: CRID_1
2: CRID_2
3: CRID_3
- fsps,reset-select: ResetSelect
0x6: warm reset (default)
0xE: cold reset
- fsps,sdcard-enabled: SD Card Support (D27:F0)
- fsps,e-mmc-enabled: SeMMC Support (D28:F0)
- fsps,emmc-host-max-speed: eMMC Max Speed
0: HS400(default)
1: HS200
2: DDR50
- fsps,ufs-enabled: UFS Support (D29:F0)
- fsps,sdio-enabled: SDIO Support (D30:F0)
- fsps,gpp-lock: GPP Lock Feature
- fsps,sirq-enable: Serial IRQ
- fsps,sirq-mode: Serial IRQ Mode
0: Quiet mode (default)
1: Continuous mode
- fsps,start-frame-pulse: Start Frame Pulse Width
0: ScSfpw4Clk (default)
1: ScSfpw6Clk
2: ScSfpw8Clk
- fsps,smbus-enable: SMBus
- fsps,arp-enable: SMBus ARP Support
- fsps,num-rsvd-smbus-addresses: SMBus Table Elements
0x0080: (default)
- fsps,rsvd-smbus-address-table: Reserved SMBus Address Table
0x00: (default)
- fsps,disable-compliance-mode: XHCI Disable Compliance Mode
- fsps,usb-per-port-ctl: USB Per-Port Control
- fsps,usb30-mode: xHCI Mode
0: Disable
1: Enable
2: Auto (default)
- fsps,port-usb20-enable: Enable USB2 ports
- fsps,port-usb20-over-current-pin: USB20 Over Current Pin
- fsps,usb-otg: XDCI Support
0: Disable
1: PCI_Mode (default)
2: ACPI_mode
- fsps,hsic-support-enable: Enable XHCI HSIC Support
- fsps,port-usb30-enable: Enable USB3 ports
- fsps,port-usb30-over-current-pin: USB30 Over Current Pin
- fsps,ssic-port-enable: Enable XHCI SSIC Support
- fsps,dlane-pwr-gating: SSIC Dlane PowerGating
- fsps,vtd-enable: VT-d
- fsps,lock-down-global-smi: SMI Lock bit
- fsps,reset-wait-timer: HDAudio Delay Timer
0x012C: (default)
- fsps,rtc-lock: RTC Lock Bits
- fsps,sata-test-mode: SATA Test Mode Selection
- fsps,ssic-rate: XHCI SSIC RATE
1: A Series (default)
2: B Series
- fsps,dynamic-power-gating: SMBus Dynamic Power Gating
- fsps,pcie-rp-ltr-max-snoop-latency: Max Snoop Latency
0x0000: (default)
- fsps,pcie-rp-snoop-latency-override-mode: Snoop Latency Override
0: Disable
1: Enable
2: Auto (default)
- fsps,pcie-rp-snoop-latency-override-value: Snoop Latency Value
0x003C (default)
- fsps,pcie-rp-snoop-latency-override-multiplier: Snoop Latency Multiplier
0: 1ns
1: 32ns
2: 1024ns (default)
3: 32768ns
4: 1048576ns
5: 33554432ns
- fsps,skip-mp-init: Skip Multi-Processor Initialization
- fsps,dci-auto-detect: DCI Auto Detect
- fsps,pcie-rp-ltr-max-non-snoop-latency: Max Non-Snoop Latency
0x0000: (default)
- fsps,pcie-rp-non-snoop-latency-override-mode: Non Snoop Latency Override
- fsps,tco-timer-halt-lock: Halt and Lock TCO Timer
- fsps,pwr-btn-override-period: Power Button Override Period
000: 4s (default)
001: 6s
010: 8s
011: 10s
100: 12s
101: 14s
- fsps,pcie-rp-non-snoop-latency-override-value:
0x003C: (default)
- fsps,pcie-rp-non-snoop-latency-override-multiplier: Non Snoop Latency Value
0: 1ns
1: 32ns
2: 1024ns (default)
3: 32768ns
4: 1048576ns
5: 33554432ns
- fsps,pcie-rp-slot-power-limit-scale: PCIE Root Port Slot Power Limit Scale
0x00: (default)
- fsps,pcie-rp-slot-power-limit-value:
0x00: (default)
- fsps,disable-native-power-button: Power Button Native Mode Disable
- fsps,power-butter-debounce-mode: Power Button Debounce Mode
- fsps,sdio-tx-cmd-cntl: SDIO_TX_CMD_DLL_CNTL
0x505: (default)
- fsps,sdio-tx-data-cntl1: SDIO_TX_DATA_DLL_CNTL1
0xE: (default)
- fsps,sdio-tx-data-cntl2: SDIO_TX_DATA_DLL_CNTL2
0x22272828: (default)
- fsps,sdio-rx-cmd-data-cntl1: SDIO_RX_CMD_DATA_DLL_CNTL1
0x16161616: (default)
- fsps,sdio-rx-cmd-data-cntl2: SDIO_RX_CMD_DATA_DLL_CNTL2
0x10000: (default)
- fsps,sdcard-tx-cmd-cntl: SDCARD_TX_CMD_DLL_CNTL
0x505 (default)
- fsps,sdcard-tx-data-cntl1: SDCARD_TX_DATA_DLL_CNTL1
0xA13: (default)
- fsps,sdcard-tx-data-cntl2: SDCARD_TX_DATA_DLL_CNTL2
0x24242828: (default)
- fsps,sdcard-rx-cmd-data-cntl1: SDCARD_RX_CMD_DATA_DLL_CNTL1
0x73A3637 (default)
- fsps,sdcard-rx-strobe-cntl: SDCARD_RX_STROBE_DLL_CNTL
0x0: (default)
- fsps,sdcard-rx-cmd-data-cntl2: SDCARD_RX_CMD_DATA_DLL_CNTL2
0x10000: (default)
- fsps,emmc-tx-cmd-cntl: EMMC_TX_CMD_DLL_CNTL
0x505: (default)
- fsps,emmc-tx-data-cntl1: EMMC_TX_DATA_DLL_CNTL1
0xC11: (default)
- fsps,emmc-tx-data-cntl2: EMMC_TX_DATA_DLL_CNTL2
0x1C2A2927: (default)
- fsps,emmc-rx-cmd-data-cntl1: EMMC_RX_CMD_DATA_DLL_CNTL1
0x000D162F: (default)
- fsps,emmc-rx-strobe-cntl: EMMC_RX_STROBE_DLL_CNTL
0x0a0a: (default)
- fsps,emmc-rx-cmd-data-cntl2: EMMC_RX_CMD_DATA_DLL_CNTL2
0x1003b: (default)
- fsps,emmc-master-sw-cntl: EMMC_MASTER_DLL_CNTL
0x001: (default)
- fsps,pcie-rp-selectable-deemphasis: PCIe Selectable De-emphasis
1: -3.5 dB (default)
0: -6 dB
- fsps,monitor-mwait-enable: Monitor Mwait Enable
- fsps,hd-audio-dsp-uaa-compliance: Universal Audio Architecture
compliance for DSP enabled system
- fsps,ipc: IRQ Interrupt Polarity Control
- fsps,sata-ports-disable-dynamic-pg: Disable ModPHY dynamic power gate
- fsps,init-s3-cpu: Init CPU during S3 resume
- fsps,skip-punit-init: Skip P-unit Initialization
- fsps,port-usb20-per-port-tx-pe-half: PerPort Half Bit Pre-emphasis
- fsps,port-usb20-per-port-pe-txi-set: PerPort HS Pre-emphasis Bias
- fsps,port-usb20-per-port-txi-set: PerPort HS Transmitter Bias
- fsps,port-usb20-hs-skew-sel: Select the skew direction for HS transition
- fsps,port-usb20-i-usb-tx-emphasis-en: PerPort HS Transmitter Emphasis
- fsps,port-usb20-per-port-rxi-set: PerPort HS Receiver Bias
- fsps,port-usb20-hs-npre-drv-sel: Delay/skew's strength control for HS driver
Example:
&fsp_s {
u-boot,dm-pre-proper;
fsps,ish-enable = <0>;
fsps,enable-sata = <0>;
fsps,pcie-root-port-en = [00 00 00 00 00 01];
fsps,pcie-rp-hot-plug = [00 00 00 00 00 01];
fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>;
fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>;
fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>;
fsps,spi1-enable = <SPIX_ENABLE_DISABLED>;
fsps,spi2-enable = <SPIX_ENABLE_DISABLED>;
fsps,sdio-enabled = <0>;
...
};

248
fs/cbfs/cbfs.c
View file

@ -5,14 +5,28 @@
#include <common.h>
#include <cbfs.h>
#include <log.h>
#include <malloc.h>
#include <asm/byteorder.h>
/* Offset of master header from the start of a coreboot ROM */
#define MASTER_HDR_OFFSET 0x38
static const u32 good_magic = 0x4f524243;
static const u8 good_file_magic[] = "LARCHIVE";
/**
* struct cbfs_priv - Private data for this driver
*
* @initialised: true if this CBFS has been inited
* @start: Start position of CBFS in memory, typically memory-mapped SPI flash
* @header: Header read from the CBFS, byte-swapped so U-Boot can access it
* @file_cache: List of file headers read from CBFS
* @result: Success/error result
*/
struct cbfs_priv {
int initialized;
bool initialized;
void *start;
struct cbfs_header header;
struct cbfs_cachenode *file_cache;
enum cbfs_result result;
@ -77,19 +91,19 @@ static void swap_file_header(struct cbfs_fileheader *dest,
* @param used A pointer to the count of of bytes scanned through,
* including the file if one is found.
*
* @return 1 if a file is found, 0 if one isn't.
* @return 0 if a file is found, -ENOENT if one isn't, -EBADF if a bad header
* is found.
*/
static int file_cbfs_next_file(struct cbfs_priv *priv, u8 *start, u32 size,
u32 align, struct cbfs_cachenode *new_node,
u32 *used)
static int file_cbfs_next_file(struct cbfs_priv *priv, void *start, int size,
int align, struct cbfs_cachenode *new_node,
int *used)
{
struct cbfs_fileheader header;
*used = 0;
while (size >= align) {
const struct cbfs_fileheader *file_header =
(const struct cbfs_fileheader *)start;
const struct cbfs_fileheader *file_header = start;
u32 name_len;
u32 step;
@ -105,7 +119,7 @@ static int file_cbfs_next_file(struct cbfs_priv *priv, u8 *start, u32 size,
swap_file_header(&header, file_header);
if (header.offset < sizeof(struct cbfs_fileheader)) {
priv->result = CBFS_BAD_FILE;
return -1;
return -EBADF;
}
new_node->next = NULL;
new_node->type = header.type;
@ -122,18 +136,19 @@ static int file_cbfs_next_file(struct cbfs_priv *priv, u8 *start, u32 size,
step = step + align - step % align;
*used += step;
return 1;
return 0;
}
return 0;
return -ENOENT;
}
/* Look through a CBFS instance and copy file metadata into regular memory. */
static void file_cbfs_fill_cache(struct cbfs_priv *priv, u8 *start, u32 size,
u32 align)
static int file_cbfs_fill_cache(struct cbfs_priv *priv, int size, int align)
{
struct cbfs_cachenode *cache_node;
struct cbfs_cachenode *new_node;
struct cbfs_cachenode **cache_tail = &priv->file_cache;
void *start;
/* Clear out old information. */
cache_node = priv->file_cache;
@ -144,21 +159,23 @@ static void file_cbfs_fill_cache(struct cbfs_priv *priv, u8 *start, u32 size,
}
priv->file_cache = NULL;
start = priv->start;
while (size >= align) {
int result;
u32 used;
int used;
int ret;
new_node = (struct cbfs_cachenode *)
malloc(sizeof(struct cbfs_cachenode));
result = file_cbfs_next_file(priv, start, size, align, new_node,
&used);
if (!new_node)
return -ENOMEM;
ret = file_cbfs_next_file(priv, start, size, align, new_node,
&used);
if (result < 0) {
if (ret < 0) {
free(new_node);
return;
} else if (result == 0) {
free(new_node);
break;
if (ret == -ENOENT)
break;
return ret;
}
*cache_tail = new_node;
cache_tail = &new_node->next;
@ -167,85 +184,117 @@ static void file_cbfs_fill_cache(struct cbfs_priv *priv, u8 *start, u32 size,
start += used;
}
priv->result = CBFS_SUCCESS;
}
/* Get the CBFS header out of the ROM and do endian conversion. */
static int file_cbfs_load_header(uintptr_t end_of_rom,
struct cbfs_header *header)
{
struct cbfs_header *header_in_rom;
int32_t offset = *(u32 *)(end_of_rom - 3);
header_in_rom = (struct cbfs_header *)(end_of_rom + offset + 1);
swap_header(header, header_in_rom);
if (header->magic != good_magic || header->offset >
header->rom_size - header->boot_block_size) {
cbfs_s.result = CBFS_BAD_HEADER;
return 1;
}
return 0;
}
static int cbfs_load_header_ptr(struct cbfs_priv *priv, ulong base,
struct cbfs_header *header)
/**
* load_header() - Load the CBFS header
*
* Get the CBFS header out of the ROM and do endian conversion.
*
* @priv: Private data, which is inited by this function
* @addr: Address of CBFS header in memory-mapped SPI flash
* @return 0 if OK, -ENXIO if the header is bad
*/
static int load_header(struct cbfs_priv *priv, ulong addr)
{
struct cbfs_header *header = &priv->header;
struct cbfs_header *header_in_rom;
header_in_rom = (struct cbfs_header *)base;
memset(priv, '\0', sizeof(*priv));
header_in_rom = (struct cbfs_header *)addr;
swap_header(header, header_in_rom);
if (header->magic != good_magic || header->offset >
header->rom_size - header->boot_block_size) {
priv->result = CBFS_BAD_HEADER;
return -EFAULT;
return -ENXIO;
}
return 0;
}
static void cbfs_init(struct cbfs_priv *priv, uintptr_t end_of_rom)
/**
* file_cbfs_load_header() - Get the CBFS header out of the ROM, given the end
*
* @priv: Private data, which is inited by this function
* @end_of_rom: Address of the last byte of the ROM (typically 0xffffffff)
* @return 0 if OK, -ENXIO if the header is bad
*/
static int file_cbfs_load_header(struct cbfs_priv *priv, ulong end_of_rom)
{
u8 *start_of_rom;
int offset = *(u32 *)(end_of_rom - 3);
int ret;
priv->initialized = 0;
ret = load_header(priv, end_of_rom + offset + 1);
if (ret)
return ret;
priv->start = (void *)(end_of_rom + 1 - priv->header.rom_size);
if (file_cbfs_load_header(end_of_rom, &priv->header))
return;
start_of_rom = (u8 *)(end_of_rom + 1 - priv->header.rom_size);
file_cbfs_fill_cache(priv, start_of_rom, priv->header.rom_size,
priv->header.align);
if (priv->result == CBFS_SUCCESS)
priv->initialized = 1;
return 0;
}
void file_cbfs_init(uintptr_t end_of_rom)
/**
* cbfs_load_header_ptr() - Get the CBFS header out of the ROM, given the base
*
* @priv: Private data, which is inited by this function
* @base: Address of the first byte of the ROM (e.g. 0xff000000)
* @return 0 if OK, -ENXIO if the header is bad
*/
static int cbfs_load_header_ptr(struct cbfs_priv *priv, ulong base)
{
cbfs_init(&cbfs_s, end_of_rom);
int ret;
ret = load_header(priv, base + MASTER_HDR_OFFSET);
if (ret)
return ret;
priv->start = (void *)base;
return 0;
}
int cbfs_init_mem(ulong base, ulong size, struct cbfs_priv **privp)
static int cbfs_init(struct cbfs_priv *priv, ulong end_of_rom)
{
int ret;
ret = file_cbfs_load_header(priv, end_of_rom);
if (ret)
return ret;
ret = file_cbfs_fill_cache(priv, priv->header.rom_size,
priv->header.align);
if (ret)
return ret;
priv->initialized = true;
return 0;
}
int file_cbfs_init(ulong end_of_rom)
{
return cbfs_init(&cbfs_s, end_of_rom);
}
int cbfs_init_mem(ulong base, struct cbfs_priv **privp)
{
struct cbfs_priv priv_s, *priv = &priv_s;
int ret;
/*
* Use a local variable to start with until we know that the CBFS is
* valid. Assume that a master header appears at the start, at offset
* 0x38.
* valid.
*/
ret = cbfs_load_header_ptr(priv, base + 0x38, &priv->header);
ret = cbfs_load_header_ptr(priv, base);
if (ret)
return ret;
file_cbfs_fill_cache(priv, (u8 *)base, priv->header.rom_size,
priv->header.align);
if (priv->result != CBFS_SUCCESS)
return -EINVAL;
ret = file_cbfs_fill_cache(priv, priv->header.rom_size,
priv->header.align);
if (ret)
return log_msg_ret("fill", ret);
priv->initialized = 1;
priv->initialized = true;
priv = malloc(sizeof(priv_s));
if (!priv)
return -ENOMEM;
@ -324,42 +373,59 @@ const struct cbfs_cachenode *file_cbfs_find(const char *name)
return cbfs_find_file(&cbfs_s, name);
}
const struct cbfs_cachenode *file_cbfs_find_uncached(uintptr_t end_of_rom,
const char *name)
static int find_uncached(struct cbfs_priv *priv, const char *name, void *start,
struct cbfs_cachenode *node)
{
struct cbfs_priv *priv = &cbfs_s;
u8 *start;
u32 size;
u32 align;
static struct cbfs_cachenode node;
if (file_cbfs_load_header(end_of_rom, &priv->header))
return NULL;
start = (u8 *)(end_of_rom + 1 - priv->header.rom_size);
size = priv->header.rom_size;
align = priv->header.align;
int size = priv->header.rom_size;
int align = priv->header.align;
while (size >= align) {
int result;
u32 used;
int used;
int ret;
result = file_cbfs_next_file(priv, start, size, align, &node,
&used);
if (result < 0)
return NULL;
else if (result == 0)
ret = file_cbfs_next_file(priv, start, size, align, node,
&used);
if (ret == -ENOENT)
break;
if (!strcmp(name, node.name))
return &node;
else if (ret)
return ret;
if (!strcmp(name, node->name))
return 0;
size -= used;
start += used;
}
cbfs_s.result = CBFS_FILE_NOT_FOUND;
return NULL;
priv->result = CBFS_FILE_NOT_FOUND;
return -ENOENT;
}
int file_cbfs_find_uncached(ulong end_of_rom, const char *name,
struct cbfs_cachenode *node)
{
struct cbfs_priv priv;
void *start;
int ret;
ret = file_cbfs_load_header(&priv, end_of_rom);
if (ret)
return ret;
start = priv.start;
return find_uncached(&priv, name, start, node);
}
int file_cbfs_find_uncached_base(ulong base, const char *name,
struct cbfs_cachenode *node)
{
struct cbfs_priv priv;
int ret;
ret = cbfs_load_header_ptr(&priv, base);
if (ret)
return ret;
return find_uncached(&priv, name, (void *)base, node);
}
const char *file_cbfs_name(const struct cbfs_cachenode *file)

42
include/cbfs.h
View file

@ -80,8 +80,6 @@ struct cbfs_cachenode {
u32 attributes_offset;
};
extern enum cbfs_result file_cbfs_result;
/**
* file_cbfs_error() - Return a string describing the most recent error
* condition.
@ -100,10 +98,10 @@ enum cbfs_result cbfs_get_result(void);
/**
* file_cbfs_init() - Initialize the CBFS driver and load metadata into RAM.
*
* @end_of_rom: Points to the end of the ROM the CBFS should be read
* from.
* @end_of_rom: Points to the end of the ROM the CBFS should be read from
* @return 0 if OK, -ve on error
*/
void file_cbfs_init(uintptr_t end_of_rom);
int file_cbfs_init(ulong end_of_rom);
/**
* file_cbfs_get_header() - Get the header structure for the current CBFS.
@ -151,11 +149,10 @@ const struct cbfs_cachenode *cbfs_find_file(struct cbfs_priv *cbfs,
* cbfs_init_mem() - Set up a new CBFS
*
* @base: Base address of CBFS
* @size: Size of CBFS in bytes
* @cbfsp: Returns a pointer to CBFS on success
* @return 0 if OK, -ve on error
*/
int cbfs_init_mem(ulong base, ulong size, struct cbfs_priv **privp);
int cbfs_init_mem(ulong base, struct cbfs_priv **privp);
/***************************************************************************/
@ -163,17 +160,32 @@ int cbfs_init_mem(ulong base, ulong size, struct cbfs_priv **privp);
/***************************************************************************/
/**
* file_cbfs_find_uncached() - Find a file with a particular name in CBFS
* without using the heap.
* file_cbfs_find_uncached() - Find a file in CBFS given the end of the ROM
*
* @end_of_rom: Points to the end of the ROM the CBFS should be read
* from.
* @name: The name to search for.
* Note that @node should be declared by the caller. This design is to avoid
* the need for allocation here.
*
* @return A handle to the file, or NULL on error.
* @end_of_rom: Points to the end of the ROM the CBFS should be read from
* @name: The name to search for
* @node: Returns the contents of the node if found (i.e. copied into *node)
* @return 0 on success, -ENOENT if not found, -EFAULT on bad header
*/
const struct cbfs_cachenode *file_cbfs_find_uncached(uintptr_t end_of_rom,
const char *name);
int file_cbfs_find_uncached(ulong end_of_rom, const char *name,
struct cbfs_cachenode *node);
/**
* file_cbfs_find_uncached_base() - Find a file in CBFS given the base address
*
* Note that @node should be declared by the caller. This design is to avoid
* the need for allocation here.
*
* @base: Points to the base of the CBFS
* @name: The name to search for
* @node: Returns the contents of the node if found (i.e. copied into *node)
* @return 0 on success, -ENOENT if not found, -EFAULT on bad header
*/
int file_cbfs_find_uncached_base(ulong base, const char *name,
struct cbfs_cachenode *node);
/**
* file_cbfs_name() - Get the name of a file in CBFS.