From 6ed695238304db5a650065fbdb9b41a5b916ff09 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Wed, 18 Sep 2019 16:50:52 +0800 Subject: [PATCH 01/11] armv8: ls1028a: Add more personalities support Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by: Tang Yuantian Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index a5d0b5370f..8fd6c751c6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -59,6 +59,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), + CPU_TYPE_ENTRY(LS1017A, LS1017A, 1), + CPU_TYPE_ENTRY(LS1018A, LS1018A, 1), + CPU_TYPE_ENTRY(LS1027A, LS1027A, 2), CPU_TYPE_ENTRY(LS1028A, LS1028A, 2), CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 234440b5fe..b7267a653e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -83,6 +83,9 @@ enum boot_src get_boot_src(void); /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ #define SVR_LS1043A_P23 0x879202 #define SVR_LS1023A_P23 0x87920A +#define SVR_LS1017A 0x870B24 +#define SVR_LS1018A 0x870B20 +#define SVR_LS1027A 0x870B04 #define SVR_LS1028A 0x870B00 #define SVR_LS1046A 0x870700 #define SVR_LS1026A 0x870708 From 60b0055ba53ac908715be27404c9f4790a3b36f8 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Wed, 18 Sep 2019 14:58:11 +0530 Subject: [PATCH 02/11] configs: ls1012ardb: Add CONFIG_ENV_ADDR CONFIG_ENV_ADDR config option enables picking the environment from flash before DDR init. Signed-off-by: Ashish Kumar Signed-off-by: Kuldeep Singh Signed-off-by: Priyanka Jain --- include/configs/ls1012ardb.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index f6640fa499..a5e27404f8 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -17,6 +17,10 @@ #define CONFIG_SYS_MEMTEST_END 0x9fffffff +/* ENV */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ + CONFIG_ENV_OFFSET) /* * I2C IO expander */ From bb6f3c0f76347a3a8d701f2318bbf0b7eef5279e Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Wed, 18 Sep 2019 16:28:04 +0530 Subject: [PATCH 03/11] armv7: ls102xa: Update SCFG_QSPI_CLKSEL value Update SCFG_QSPI_CLKSEL value : 0xC -> 0x5 which means ClusterPLL/16 Signed-off-by: Ashish Kumar Signed-off-by: Kuldeep Singh Signed-off-by: Priyanka Jain --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 137cd61804..f2ba182346 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -155,7 +155,7 @@ struct ccsr_gur { #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 -#define SCFG_QSPI_CLKSEL 0xc0100000 +#define SCFG_QSPI_CLKSEL 0x50100000 #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000 #define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000 #define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000 From 3d23b6c5836c004c5f9a8281b03a2da98f20d9ff Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Fri, 20 Sep 2019 17:34:29 +0800 Subject: [PATCH 04/11] armv8: fsl-layerscape: Make USB masters snoopable Program register bit of SCFG_SNPCNFGCR_USBxRDSNP and SCFG_SNPCNFGCR_USBxWRSNP(x = 1, 2, 3) to drive USBx read/write snoop signal on LS1043A and LS1046A. Signed-off-by: Ran Wang Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 +++++++++ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 3fd34e3a43..1f1869e8cf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -627,10 +627,19 @@ void fsl_lsch2_early_init_f(void) #endif #endif /* Make SEC reads and writes snoopable */ +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | + SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP | + SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP | + SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP | + SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP | + SCFG_SNPCNFGCR_SATAWRSNP); +#else setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_SATARDSNP | SCFG_SNPCNFGCR_SATAWRSNP); +#endif /* * Enable snoop requests and DVM message requests for diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 3a59abb10e..862ec2e2f1 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -409,6 +409,12 @@ struct ccsr_gur { #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 +#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000 +#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000 +#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000 +#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000 +#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000 +#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000 /* RGMIIPCR bit definitions*/ #define SCFG_RGMIIPCR_EN_AUTO BIT(3) From 3f4bc67548595258764b6fb15717b17a05b6be58 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Wed, 25 Sep 2019 17:48:11 +0800 Subject: [PATCH 05/11] armv7: ls102xa: Correct endianness of SCFG_SPARECR8 read The patch corrects endianness of register SCFG_SPARECR8 read in_le32 -> in_be32 Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index bb169aaaf4..00b6ad48ce 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -72,7 +72,7 @@ static void __secure ls1_deepsleep_irq_cfg(void) * returns zero, so its value is saved to a scrachpad register to be * read, that is why we don't read it from register ippdexpcr1 itself. */ - ippdexpcr1 = in_le32(&scfg->sparecr[7]); + ippdexpcr1 = in_be32(&scfg->sparecr[7]); out_be32(&rcpm->ippdexpcr1, ippdexpcr1); if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC) From 6972c60f8c54f77bcdb43139b3765fe6f4a4366a Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Mon, 30 Sep 2019 12:38:34 +0530 Subject: [PATCH 06/11] configs: ls1012afrwy: Add CONFIG_ENV_ADDR This configuration enables picking the environment from flash before DDR init. Signed-off-by: Kuldeep Singh Signed-off-by: Priyanka Jain --- include/configs/ls1012afrwy.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 77aa22bfde..1b0f1566d3 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -23,6 +23,11 @@ #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff +/* ENV */ +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ + CONFIG_ENV_OFFSET) + #ifndef CONFIG_SPL_BUILD #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ From 72c3bfaad5cfd6272a47fffb538db0beb0ead942 Mon Sep 17 00:00:00 2001 From: Udit Agarwal Date: Mon, 30 Sep 2019 10:16:57 +0000 Subject: [PATCH 07/11] board/ls1028a: Add call to sec_init() Adds sec_init call to initialise the job ring parameters for secure boot operations. Signed-off-by: Udit Agarwal Signed-off-by: Priyanka Jain --- board/freescale/ls1028a/ls1028a.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 095971448f..a9606b8865 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -63,6 +63,10 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif From 54d5c06cb9e8dac1d7e2d81bedb0f143ba0b0dbf Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Thu, 10 Oct 2019 17:19:37 +0800 Subject: [PATCH 08/11] armv8: ls1028a: disable multimedia for ls1027a, ls1017a ls1028a has 4 personalities: ls1028a, ls1027a, ls1017a and ls1018a. Both ls1027a and ls1017a personalities are lower functionality version which doesn't support the multimedia subsystems, like LCD, GPU. To disable multimedia feature on non-multimedia version, set the status property to disabled in dts nodes. Signed-off-by: Tang Yuantian Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 23 +++++++++++++++++++ .../arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++ 2 files changed, 26 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 19917b207a..e993209593 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -401,6 +401,26 @@ void fdt_fixup_remove_jr(void *blob) } #endif +#ifdef CONFIG_ARCH_LS1028A +static void fdt_disable_multimedia(void *blob, unsigned int svr) +{ + int off; + + if (IS_MULTIMEDIA_EN(svr)) + return; + + /* Disable eDP/LCD node */ + off = fdt_node_offset_by_compatible(blob, -1, "arm,mali-dp500"); + if (off != -FDT_ERR_NOTFOUND) + fdt_status_disabled(blob, off); + + /* Disable GPU node */ + off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu"); + if (off != -FDT_ERR_NOTFOUND) + fdt_status_disabled(blob, off); +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -462,4 +482,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI fdt_fixup_msi(blob); #endif +#ifdef CONFIG_ARCH_LS1028A + fdt_disable_multimedia(blob, svr); +#endif } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index b7267a653e..52f5560e06 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -115,6 +115,9 @@ enum boot_src get_boot_src(void); #ifdef CONFIG_ARCH_LX2160A #define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) #endif +#ifdef CONFIG_ARCH_LS1028A +#define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1)) +#endif #define IS_SVR_REV(svr, maj, min) \ ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) #define SVR_DEV(svr) ((svr) >> 8) From e93a7caf86cd23ab2cc8d0b138b3634896f8909a Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Tue, 15 Oct 2019 08:54:11 +0000 Subject: [PATCH 09/11] armv8: Update LX2160A/LX2120A/LX2080A SVR value LX2160A/LX2120A/LX2080A SVR value should be 0x873600/0x873620/0x873602 Previous values were valid only if CAN fuse is blown. Signed-off-by: Wasim Khan Signed-off-by: Priyanka Jain --- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 52f5560e06..35719d747b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * Copyright 2015 Freescale Semiconductor */ @@ -103,9 +103,9 @@ enum boot_src get_boot_src(void); #define SVR_LS2044A 0x870930 #define SVR_LS2081A 0x870918 #define SVR_LS2041A 0x870914 -#define SVR_LX2160A 0x873601 -#define SVR_LX2120A 0x873621 -#define SVR_LX2080A 0x873603 +#define SVR_LX2160A 0x873600 +#define SVR_LX2120A 0x873620 +#define SVR_LX2080A 0x873602 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) From 1936841b11759957f78ed1c30e9d728aa9bb6c0c Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Wed, 25 Sep 2019 18:40:42 +0800 Subject: [PATCH 10/11] armv7: ls102xa: add errata ID A-008646 for workaround The patch adds an errata ID A-008646 for workaround to provide more information by errata ID. Signed-off-by: Biwen Li Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index 00b6ad48ce..86693edf5d 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -68,9 +68,10 @@ static void __secure ls1_deepsleep_irq_cfg(void) ippdexpcr0 = in_be32(&rcpm->ippdexpcr0); /* - * Workaround: There is bug of register ippdexpcr1, when read it always - * returns zero, so its value is saved to a scrachpad register to be - * read, that is why we don't read it from register ippdexpcr1 itself. + * Workaround of errata A-008646 + * Errata states that read to register ippdexpcr1 always returns + * zero irrespective of what value is written into it. So its value + * is first saved to a spare register and then read from it */ ippdexpcr1 = in_be32(&scfg->sparecr[7]); out_be32(&rcpm->ippdexpcr1, ippdexpcr1); From d20f184ce3a012ab2c0abe4792bc130c238fa5b0 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 21 Oct 2019 12:23:30 +0530 Subject: [PATCH 11/11] armv7: ls102xa: Don't power down OCRAM1 during deep sleep To allow OCRAM to be used as wakeup source in deep sleep, do not power it down. Signed-off-by: Biwen Li Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index 86693edf5d..df64f5415a 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -74,7 +74,12 @@ static void __secure ls1_deepsleep_irq_cfg(void) * is first saved to a spare register and then read from it */ ippdexpcr1 = in_be32(&scfg->sparecr[7]); - out_be32(&rcpm->ippdexpcr1, ippdexpcr1); + + /* + * To allow OCRAM to be used as wakeup source in deep sleep, + * do not power it down. + */ + out_be32(&rcpm->ippdexpcr1, ippdexpcr1 | RCPM_IPPDEXPCR1_OCRAM1); if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC) pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 |