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Stefan Roese 2007-03-31 13:44:12 +02:00
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CHANGELOG
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@ -1,3 +1,239 @@
commit 2a8dfe08359a1b663418b2faa1da1d7bce34d302
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Mar 21 23:26:15 2007 +0100
Code cleanup. Update CHANGELOG
commit e6615ecf4eaf4dd52696934aed8f5c6474cfd286
Author: Stefan Roese <sr@denx.de>
Date: Wed Mar 21 14:54:29 2007 +0100
ppc4xx: Fix file mode of include/configs/acadia.h
Signed-off-by: Stefan Roese <sr@denx.de>
commit d5f4614c9350d9333e575100fb250aab774d0258
Author: Markus Klotzbuecher <mk@denx.de>
Date: Wed Mar 21 14:41:46 2007 +0100
SPC1920: fix small clock routing bug
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
commit 16c0cc1c82081a493ab87c51980b28336ce1bce8
Author: Stefan Roese <sr@denx.de>
Date: Wed Mar 21 13:39:57 2007 +0100
[PATCH] Add AMCC Acadia (405EZ) eval board support
This patch adds support for the new AMCC Acadia eval board.
Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.
Signed-off-by: Stefan Roese <sr@denx.de>
commit e01bd218b00af73499331a1a701625a852cd286f
Author: Stefan Roese <sr@denx.de>
Date: Wed Mar 21 13:38:59 2007 +0100
[PATCH] Add AMCC PPC405EZ support
This patch adds support for the new AMCC 405EZ PPC. It is in
preparation for the AMCC Acadia board support.
Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.
Signed-off-by: Stefan Roese <sr@denx.de>
commit 07e82cb2e284a893df6693f2a1337ab2c47bf6a1
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Wed Mar 21 08:45:17 2007 +0100
[PATCH] TQM8272: dont change the bits given from the HRCW
for the SIUMCR and BCR Register.
Fix the calculation for the EEprom Size
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 654589873dbafcf104dff133ce0d03a4506e9cc3
Author: Aubrey Li <aubrey.adi@gmail.com>
Date: Tue Mar 20 18:16:24 2007 +0800
[Blackfin][PATCH] Add BF561 EZKIT board support
commit a6154fd1cfd020f6da8527e0365b1020a11a71d0
Author: Aubrey Li <aubrey.adi@gmail.com>
Date: Mon Mar 19 22:55:58 2007 +0800
[Blackfin][PATCH] minor cleanup
commit 389b6bb50f745bf5038ce030300d8a8512e96f79
Author: Wolfgang Denk <wd@denx.de>
Date: Mon Mar 19 13:10:08 2007 +0100
Remove obsoleted POST files.
Signed-off-by: Wolfgang Denk <wd@denx.de>
commit 8e709bbb2636b5670a8f2b575e138eb1f55773f6
Author: Aubrey Li <aubrey.adi@gmail.com>
Date: Mon Mar 19 01:26:11 2007 +0800
[PATCH] Add flash chip M29W320ET/B support
commit 26bf7deca364a5b33f39e8f14ddd3f4081345015
Author: Aubrey Li <aubrey.adi@gmail.com>
Date: Mon Mar 19 01:24:52 2007 +0800
[Blackfin][PATCH] Add BF537 stamp board support
commit 8423e5e31a7235d05a482627315fb11d49c17bd7
Author: Stefan Roese <sr@denx.de>
Date: Fri Mar 16 21:11:42 2007 +0100
[PATCH] Use dynamic SDRAM TLB setup on AMCC Ebony eval board
Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the
DDR memory are dynamically programmed matching the total size
of the equipped memory (DIMM modules).
Signed-off-by: Stefan Roese <sr@denx.de>
commit 76d1466f918b881cda2d259254761e73885093c2
Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Tue Mar 13 13:38:05 2007 +0100
[PATCH] renamed environment variable 'addcon' to 'addcons' for PCI405
boards in terms of unification.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
commit a7090b993d3d4d2221ac3f33e6cb1d1b2ccc6bf0
Author: Wolfgang Denk <wd@denx.de>
Date: Tue Mar 13 16:05:55 2007 +0100
Make SC3 board build with 'make O='; use 'addcons' consistently
(SC3 and Jupiter used to use 'addcon' instead).
Signed-off-by: Wolfgang Denk wd@denx.de
commit 8502e30a28e492c756ea2d7df0ace026388fce4b
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Tue Mar 13 09:40:59 2007 +0100
[PATCH] update board config for jupiter Board:
added Hush Shell,
CONFIG_CMDLINE_EDITING,
CFG_ENV_ADDR_REDUND activated
Signed-off-by: Heiko Schocher <hs@denx.de>
commit 0d93de11449390a5984b0236c3612e50f6dbb7e8
Author: Aubrey Li <aubrey.adi@gmail.com>
Date: Mon Mar 12 12:11:55 2007 +0800
[Blackfin][PATCH] minor cleanup
commit bfa5754a58477ac917d21527cd0f079d87cf188e
Author: Aubrey Li <aubrey.adi@gmail.com>
Date: Mon Mar 12 01:42:06 2007 +0800
[Blackfin][PATCH] Fix BUILD_DIR option of MAKEALL building issue
commit 8440bb14581a294375c34b91b42512f9753d1130
Author: Aubrey Li <aubrey.adi@gmail.com>
Date: Mon Mar 12 00:25:14 2007 +0800
[Blackfin][PATCH] code cleanup
commit 8db13d63157811c839d15a313d9f2d2f5fd10af3
Author: Aubrey Li <aubrey.adi@gmail.com>
Date: Sat Mar 10 23:49:29 2007 +0800
[Blackfin][PATCH] code cleanup
commit ef26a08fef928b7bc11ae2c109e638dc3a016d91
Author: Aubrey.Li <aubrey.adi@gmail.com>
Date: Fri Mar 9 13:40:56 2007 +0800
[Blackfin][PATCH-2/2] Common files changed to support bf533 platform
commit 3f0606ad0b5639f7f22848fe5b4574e754d0470f
Author: Aubrey.Li <aubrey.adi@gmail.com>
Date: Fri Mar 9 13:38:44 2007 +0800
[Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support
commit 992423ab43c2bcf6b704853bd00af77450915e20
Author: Stefan Roese <sr@denx.de>
Date: Thu Mar 8 23:00:08 2007 +0100
ppc4xx: Fix file mode of sequoia.c
Signed-off-by: Stefan Roese <sr@denx.de>
commit eb92f613556800f7483666db09d9a237ad911d4a
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Thu Mar 8 22:52:51 2007 +0100
Minor cleanup.
commit 8ce16f55c7b9752af3d8bed84521aec5337e2de1
Author: John Otken john@softadvances.com <john@softadvances.com>
Date: Thu Mar 8 09:39:48 2007 -0600
ppc4xx: Clear Sequoia/Rainier security engine reset bits
Signed-off-by: John Otken john@softadvances.com <john@softadvances.com>
commit 650a330dd2539130c8c324791e2f9f75aed79d4e
Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Thu Mar 8 16:26:52 2007 +0100
[PATCH] I2C: add some more SPD eeprom decoding for DDR2 modules
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
commit d9fc703246840c4b268debf48c334ba55c597dc0
Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Thu Mar 8 16:25:47 2007 +0100
[PATCH] I2C: disable flat i2c commands when CONFIG_I2C_CMD_TREE is defined
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
commit ced5b9029043397348cdc88e0cfcd6b1f629250b
Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Thu Mar 8 16:23:11 2007 +0100
[PATCH] 4xx: allow CONFIG_I2C_CMD_TREE without CONFIG_I2C_MULTI_BUS
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
commit d8a8ea5c476d37006fc7f85b7f903142795c8b14
Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Thu Mar 8 16:20:32 2007 +0100
[PATCH] I2C: Add missing default CFG_SPD_BUS_NUM
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
commit f9fc6a5852a6335840882fa2111925010eea1abe
Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Wed Mar 7 15:32:01 2007 +0100
fixed ethernet phy configuration for plu405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
commit 769104c9356594deb2092e204a39c05b33202d6c
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Thu Mar 8 21:49:27 2007 +0100
Minor cleanup
commit 00cdb4ce5e1b42248e7e6522ad0da3421b988afa
Author: Stefan Roese <sr@denx.de>
Date: Thu Mar 8 10:13:16 2007 +0100
@ -122,6 +358,347 @@ Date: Tue Mar 6 07:47:04 2007 +0100
Signed-off-by: Stefan Roese <sr@denx.de>
commit 781e026c8aa6f7e9eb5f0e72cc4d20971219b148
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Wed Feb 28 00:02:04 2007 -0600
mpc83xx: fix implicit declaration of function 'ft_get_prop' warnings
(cherry picked from c5bf13b02284c3204a723566a9bab700e5059659 commit)
commit 4feab4de7bfc2cb2fed36ad76f93c3a69659bbaf
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Tue Feb 27 23:51:42 2007 -0600
mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode
The config value for:
* CFG_ACR_PIPE_DEP
* CFG_ACR_RPTCNT
* CFG_SPCR_TSEC1EP
* CFG_SPCR_TSEC2EP
* CFG_SCCR_TSEC1CM
* CFG_SCCR_TSEC2CM
Were not being used when setting the appropriate register
Added:
* CFG_SCCR_USBMPHCM
* CFG_SCCR_USBDRCM
* CFG_SCCR_PCICM
* CFG_SCCR_ENCCM
To allow full config of the SCCR.
Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349
that were just bogus.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit d51b3cf371cd441030460ef19d36b2924c361b1a
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Thu Feb 22 20:06:57 2007 -0600
mpc83xx: update [local-]mac-address properties on UEC based devices
8360 and 832x weren't updating their [local-]mac-address
properties. This patch fixes that.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
commit 61f4f912acbe60776c5e00df1ec94094ce672957
Author: Timur Tabi <timur@freescale.com>
Date: Tue Feb 13 10:41:42 2007 -0600
mpc83xx: write MAC address to mac-address and local-mac-address
Some device trees have a mac-address property, some have local-mac-address,
and some have both. To support all of these device trees, this patch
updates ftp_cpu_setup() to write the MAC address to mac-address if it exists.
This function already updates local-mac-address.
Signed-off-by: Timur Tabi <timur@freescale.com>
commit 22d71a71f57fd5d38b27ac3848e50d790360a598
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Tue Feb 27 18:41:08 2007 -0600
mpc83xx: add command line editing by default
commit 3fc0bd159103b536e1c54c6f4457a09b3aba66ca
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Wed Feb 14 19:50:53 2007 -0600
mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers
Disable G1TXCLK, G2TXCLK h/w buffers. This patch
fixes a networking timeout issue with MPC8360EA (Rev.2) PBs.
Verified on Rev. 1.1, Rev. 1.2, and Rev. 2.0 boards.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Emilian Medve <Emilian.Medve@freescale.com>
commit d61853cf2472e0b8bcbd131461a93d1c49ff0c1f
Author: Xie Xiaobo <r63061@freescale.com>
Date: Wed Feb 14 18:27:17 2007 +0800
mpc83xx: Add DDR2 controller fixed/SPD Init for MPC83xx
The code supply fixed and SPD initialization for MPC83xx DDR2 Controller.
it pass DDR/DDR2 compliance tests.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
commit b110f40bd180c6b560276589beedf753e97c46ce
Author: Xie Xiaobo <r63061@freescale.com>
Date: Wed Feb 14 18:27:06 2007 +0800
mpc83xx: Add the cpu specific code for MPC8360E rev2.0 MDS
MPC8360E rev2.0 have new spridr,and PVR value,
The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
commit 8d172c0f0d85998a256a95b7459a5403a30380ed
Author: Xie Xiaobo <r63061@freescale.com>
Date: Wed Feb 14 18:26:44 2007 +0800
mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDS
MPC8349E rev3.1 have new spridr,and PVR value,
The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM.
Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
commit f6f5f709e5c8e4564c4dfeecfdf2279244f9c83b
Author: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Date: Wed Jan 31 11:04:19 2007 +0100
mpc83xx: Fix empty i2c reads/writes in fsl_i2c.c
Fix empty i2c reads/writes, i2c_write(0x50, 0x00, 0, NULL, 0)
which is used to se if an slave will ACK after receiving its address.
Correct i2c probing to use this method as the old method could upset
a slave as it wrote a data byte to it.
Add a small delay in i2c_init() to let the controller
shutdown any ongoing I2C activity.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
commit 7a78f148d6a7298e4fface680dc7eacd877b1aba
Author: Timur Tabi <timur@freescale.com>
Date: Wed Jan 31 15:54:29 2007 -0600
mpc83xx: Add support for the MPC8349E-mITX-GP
Add support for the MPC8349E-mITX-GP, a stripped-down version of the
MPC8349E-mITX. Bonus features include support for low-boot (BMS bit in
HRCW is 0) for the ITX and a README for the ITX and the ITX-GP.
Signed-off-by: Timur Tabi <timur@freescale.com>
commit fab16807adad350f618024350c6950165c247c72
Author: Timur Tabi <timur@freescale.com>
Date: Wed Jan 31 15:54:20 2007 -0600
mpc83xx: Delete sdram_init() for MPC8349E-mITX
There is no SDRAM on any of the 8349 ITX variants, so function sdram_init()
never does anything. This patch deletes it.
Signed-off-by: Timur Tabi <timur@freescale.com>
commit a87c856eb411b9365937d0d4b9c21e46adbe1c14
Author: Dave Liu <daveliu@freescale.com>
Date: Fri Jan 19 10:43:26 2007 +0800
mpc83xx: Fix the LAW1/3 bug
The patch solves the alignment problem of the local bus access windows to
render accessible the memory bank and PHY registers of UPC 1 (starting at
0xf801 0000). What we actually did was to adjust the sizes of the bus
access windows so that the base address alignment requirement would be met.
Signed-off-by: Chereji Marian <marian.chereji@freescale.com>
Signed-off-by: Gridish Shlomi <gridish@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
commit 97c4b397dce236a7318b304667bf89e59d08b17c
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Tue Jan 30 16:15:31 2007 -0600
mpc83xx: don't hang if watchdog configured on 8360, 832x
don't hang if watchdog configured on 8360, 832x
The watchdog programming model is the same across all 83xx devices;
make the code reflect that.
commit b70047478570e371ce7223be342ce98afea0f7d6
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Tue Jan 30 16:15:21 2007 -0600
mpc83xx: protect memcpy to bad address if a local-mac-address is missing from dt
protect memcpy to bad address if a local-mac-address is missing from dt
commit 6752ed088c75c26a89b70c46b7326a4cd6015f29
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Tue Jan 30 16:15:04 2007 -0600
mpc83xx: make 8360 default environment fdt be 8360 (not 8349)
make 8360 default environment fdt be 8360 (not 8349)
commit a28899c910024a0226331df07207b1038c300c93
Author: Emilian Medve <Emilian.Medve@freescale.com>
Date: Tue Jan 30 16:14:50 2007 -0600
mpc83xx: Fix alternating tx error / tx buffer not ready bug in QE UEC
The problem is not gcc4 but the code itself. The BD_STATUS() macro can't
be used for busy-waiting since it strips the 'volatile' property from
the bd variable. gcc3 was working by pure luck.
This is a follow on patch to "Fix the UEC driver bug of QE"
commit 3e78a31cfe3d3022f46f67eb88e1281d5cc2eb89
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Tue Jan 30 14:08:30 2007 -0600
mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X instead
The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all
MPC834X class processors. Change the protections from CONFIG_MPC8349 to
CONFIG_MPC834X so they are more generic.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit ae246dc6c1937c291014eadd90b6d48c438c7cb0
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Thu Jan 25 13:40:55 2007 -0600
mpc83xx: add MPC832XEMDS and sbc8349 to MAKEALL
commit 4decd84e8f04279c5cfff7f8e907465ef8d8a3fb
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Wed Jan 24 17:18:37 2007 -0600
mpc83xx: sort Makefile targets
reordered targets alphabetically
commit 91e25769771c1164ed63ffca0add49f934ae3343
Author: Paul Gortmaker <paul.gortmaker@windriver.com>
Date: Tue Jan 16 11:38:14 2007 -0500
mpc83xx: U-Boot support for Wind River SBC8349
I've redone the SBC8349 support to match git-current, which
incorporates all the MPC834x updates from Freescale since the 1.1.6
release, including the DDR changes.
I've kept all the SBC8349 files as parallel as possible to the
MPC8349EMDS ones for ease of maintenance and to allow for easy
inspection of what was changed to support this board. Hence the SBC8349
U-Boot has FDT support and everything else that the MPC8349EMDS has.
Fortunately the Freescale updates added support for boards using CS0,
but I had to change spd_sdram.c to allow for board specific settings for
the sdram_clk_cntl (it is/was hard coded to zero, and that remains the
default if the board doesn't specify a value.)
Hopefully this should be mergeable as-is and require no whitespace
cleanups or similar, but if something doesn't measure up then let me
know and I'll fix it.
Thanks,
Paul.
commit 05031db456ab227f3e3752f37b9b812b65bb83ad
Author: Sam Song <samsongshu@yahoo.com.cn>
Date: Thu Dec 14 19:03:21 2006 +0800
mpc83xx: Remove a redundant semicolon in mpc8349itx.c
A redundant semicolon existed in mpc8349itx.c
should be removed.
Signed-off-by: Sam Song <samsongshu@yahoo.com.cn>
commit f35f358241c549be3f75cfe2eaa642914275b7ba
Author: Jerry Van Baren <gerald.vanbaren@comcast.net>
Date: Wed Dec 6 21:23:55 2006 -0500
mpc83xx: Put the version (and magic) after the HRCW.
Put the version (and magic) after the HRCW. This puts it in a fixed
location in flash, not at the start of flash but as close as we can get.
Signed-off-by: Jerry Van Baren <vanbaren@cideas.com>
commit 48aecd969171a6e99a55fae04933857787f9a5bd
Author: Dave Liu <r63238@freescale.com>
Date: Thu Dec 7 21:14:51 2006 +0800
mpc83xx: Add the MPC832XEMDS board readme
Add the MPC832XEMDS board readme
Signed-off-by: Dave Liu <daveliu@freescale.com>
commit 24c3aca3f1358b113d3215adb5433b156e99f72b
Author: Dave Liu <r63238@freescale.com>
Date: Thu Dec 7 21:13:15 2006 +0800
mpc83xx: Add support for the MPC832XEMDS board
This patch supports DUART, ETH3/4 and PCI etc.
Signed-off-by: Dave Liu <daveliu@freescale.com>
commit e080313c32322e15ab5a18eb896a252858c57284
Author: Dave Liu <r63238@freescale.com>
Date: Thu Dec 7 21:11:58 2006 +0800
mpc83xx: streamline the 83xx immr head file
For better format and style, I streamlined the 83xx head files,
including immap_83xx.h and mpc83xx.h. In the old head files, 1)
duplicated macro definition appear in the both files; 2) the structure
of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The
macro definition put inside the each structure. So, I cleaned up the
structure of QE immr from immap_83xx.h, deleted the duplicated stuff and
moved the macro definition to mpc83xx.h, Just like MPC8260.
CHANGELOG
*streamline the 83xx immr head file
Signed-off-by: Dave Liu <daveliu@freescale.com>
commit ddd02492f43db5408f5ab9f823b0ba5796e28ef0
Author: Dave Liu <r63238@freescale.com>
Date: Wed Dec 6 11:38:17 2006 +0800
mpc83xx: Fix the UEC driver bug of QE
The patch prevents the GCC tool chain from striping useful code for
optimization. It will make UEC ethernet driver workable, Otherwise the
UEC will fail in tx when you are using gcc4.x. but the driver can work
when using gcc3.4.3.
CHANGELOG
*Prevent the GCC from striping code for optimization, Otherwise the UEC
will tx failed when you are using gcc4.x.
Signed-off-by: Dave Liu <daveliu@freescale.com>
commit ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35
Author: Stefan Roese <sr@denx.de>
Date: Thu Mar 1 21:11:36 2007 +0100
@ -1204,6 +1781,14 @@ Date: Tue Nov 28 11:04:45 2006 +0100
Signed-off-by: Stefan Roese <sr@denx.de>
commit 58e3b14c18ed3288ceef8d086946dbf3df64ccf2
Author: Stefan Roese <sr@denx.de>
Date: Tue Nov 28 11:04:45 2006 +0100
[PATCH] nand: Fix patch merge problem
Signed-off-by: Stefan Roese <sr@denx.de>
commit 4f4b602ec7524a032bdf3c6d28c7f525a4a67eaa
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Mon Nov 27 22:53:53 2006 +0100

19
MAKEALL
View file

@ -312,6 +312,14 @@ LIST_coldfire=" \
LIST_avr32="atstk1002"
#########################################################################
## Blackfin Systems
#########################################################################
LIST_blackfin=" \
bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit \
"
#-----------------------------------------------------------------------
#----- for now, just run PPC by default -----
@ -338,14 +346,15 @@ build_target() {
for arg in $@
do
case "$arg" in
ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
arm|SA|ARM7|ARM9|ARM10|ARM11|pxa|ixp| \
arm|SA|ARM7|ARM9|ARM10|ARM11|ixp|pxa| \
avr32| \
blackfin| \
coldfire| \
microblaze| \
mips|mips_el| \
nios|nios2| \
x86|I486| \
coldfire| \
avr32)
ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
x86|I486)
for target in `eval echo '$LIST_'${arg}`
do
build_target ${target}

29
Makefile
View file

@ -146,7 +146,7 @@ ifeq ($(ARCH),microblaze)
CROSS_COMPILE = mb-
endif
ifeq ($(ARCH),blackfin)
CROSS_COMPILE = bfin-elf-
CROSS_COMPILE = bfin-uclinux-
endif
ifeq ($(ARCH),avr32)
CROSS_COMPILE = avr32-
@ -178,7 +178,15 @@ OBJS += cpu/$(CPU)/resetvec.o
endif
ifeq ($(CPU),bf533)
OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
OBJS += cpu/$(CPU)/cplbhdlr.o cpu/$(CPU)/cplbmgr.o cpu/$(CPU)/flush.o
OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
endif
ifeq ($(CPU),bf537)
OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
endif
ifeq ($(CPU),bf561)
OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
endif
OBJS := $(addprefix $(obj),$(OBJS))
@ -2341,14 +2349,17 @@ suzaku_config: unconfig
#########################################################################
## Blackfin
#########################################################################
ezkit533_config : unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf533 ezkit533
bf533-ezkit_config: unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-ezkit
stamp_config : unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf533 stamp
bf533-stamp_config: unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf533 bf533-stamp
dspstamp_config : unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf533 dsp_stamp
bf537-stamp_config: unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf537 bf537-stamp
bf561-ezkit_config: unconfig
@$(MKCONFIG) $(@:_config=) blackfin bf561 bf561-ezkit
#========================================================================
# AVR32
@ -2385,6 +2396,8 @@ clean:
rm -f $(obj)board/netstar/*.srec $(obj)board/netstar/*.bin
rm -f $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom
rm -f $(obj)board/integratorap/u-boot.lds $(obj)board/integratorcp/u-boot.lds
rm -f $(obj)board/bf533-ezkit/u-boot.lds $(obj)board/bf533-stamp/u-boot.lds
rm -f $(obj)board/bf537-stamp/u-boot.lds $(obj)board/bf561-ezkit/u-boot.lds
rm -f $(obj)include/bmp_logo.h
rm -f $(obj)nand_spl/u-boot-spl $(obj)nand_spl/u-boot-spl.map

2
blackfin_config.mk
View file

@ -21,4 +21,4 @@
# MA 02111-1307 USA
#
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__blackfin__
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN

20
board/amcc/acadia/Makefile
View file

@ -23,25 +23,29 @@
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
LIB = $(obj)lib$(BOARD).a
OBJS = $(BOARD).o cpr.o memory.o
COBJS = $(BOARD).o cpr.o memory.o
SOBJS =
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
rm -f $(LIB) core *.bak .depend *~
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude .depend
sinclude $(obj).depend
#########################################################################

2
board/amcc/acadia/config.mk
View file

@ -21,8 +21,6 @@
# MA 02111-1307 USA
#
sinclude $(TOPDIR)/board/amcc/liveoak/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0xFFFC0000
endif

41
board/stamp/Makefile → board/bf533-ezkit/Makefile
View file

@ -1,7 +1,7 @@
#
# U-boot - Makefile
#
# Copyright (c) 2005 blackfin.uclinux.org
# Copyright (c) 2007 Analog Device Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -25,41 +25,28 @@
# MA 02111-1307 USA
#
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o stamp.o
COBJS := $(BOARD).o flash.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################

24
board/ezkit533/ezkit533.c → board/bf533-ezkit/bf533-ezkit.c
View file

@ -30,24 +30,28 @@
#include "psd4256.h"
#endif
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
#if (BFIN_CPU == ADSP_BF531)
printf("CPU: ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28);
#elif (BFIN_CPU == ADSP_BF532)
printf("CPU: ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28);
#else
printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
#endif
printf("Board: ADI BF533 EZ-Kit Lite board\n");
printf(" Support: http://blackfin.uclinux.org/\n");
printf(" Richard Klingler <richard@uclinux.net>\n");
return 0;
}
long int initdram(int board_type)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");
brate = simple_strtoul(tmp, NULL, 16);
printf("Serial Port initialized with Baud rate = %x\n",brate);
printf("Serial Port initialized with Baud rate = %x\n", brate);
printf("SDRAM attributes:\n");
printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
"tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
@ -64,9 +68,13 @@ long int initdram(int board_type)
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{
/* Set direction bits for Video en/decoder reset as output */
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST;
/* Deactivate Video en/decoder reset lines */
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST;
/* Set direction bits for Video en/decoder reset as output */
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) =
PSDA_VDEC_RST | PSDA_VENC_RST;
/* Deactivate Video en/decoder reset lines */
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) =
PSDA_VDEC_RST | PSDA_VENC_RST;
return 0;
}
#endif

4
board/ezkit533/config.mk → board/bf533-ezkit/config.mk
View file

@ -20,6 +20,6 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
TEXT_BASE = 0x01FC0000
PLATFORM_CPPFLAGS += -I$(TOPDIR)

6
board/ezkit533/flash-defines.h → board/bf533-ezkit/flash-defines.h
View file

@ -52,17 +52,13 @@
#define CFG_FLASH0_BASE 0x20000000
#define RESET_VAL 0xF0
asm("#define FLASH_START_L 0x0000");
asm("#define FLASH_START_H 0x2000");
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
int get_codes(void);
int poll_toggle_bit(long lOffset);
void reset_flash(void);
int erase_flash(void);
int erase_block_flash(int,unsigned long);
int erase_block_flash(int, unsigned long);
void unlock_flash(long lOffset);
int write_data(long lStart, long lCount, long lStride, int *pnData);
int FillData(long lStart, long lCount, long lStride, int *pnData);

148
board/ezkit533/flash.c → board/bf533-ezkit/flash.c
View file

@ -26,6 +26,7 @@
* MA 02111-1307 USA
*/
#include <asm/io.h>
#include "flash-defines.h"
void flash_reset(void)
@ -33,14 +34,13 @@ void flash_reset(void)
reset_flash();
}
unsigned long flash_get_size(ulong baseaddr, flash_info_t * info,
int bank_flag)
unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
{
int id = 0, i = 0;
static int FlagDev = 1;
id = get_codes();
if(FlagDev) {
if (FlagDev) {
#ifdef DEBUG
printf("Device ID of the Flash is %x\n", id);
#endif
@ -100,10 +100,11 @@ unsigned long flash_init(void)
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 >> 20);
size_b0, size_b0 >> 20);
}
(void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]);
(void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH0_BASE,
(flash_info[0].start[2] - 1), &flash_info[0]);
return (size_b0 + size_b1 + size_b2);
}
@ -122,15 +123,14 @@ void flash_print_info(flash_info_t * info)
printf("ST Microelectronics ");
break;
default:
printf("Unknown Vendor ");
printf("Unknown Vendor: (0x%08X) ", info->flash_id);
break;
}
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf("\n");
return;
@ -138,8 +138,8 @@ void flash_print_info(flash_info_t * info)
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
int cnt = 0,i;
int prot,sect;
int cnt = 0, i;
int prot, sect;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
@ -148,15 +148,16 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
}
if (prot)
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
printf("- Warning: %d protected sectors will not be erased!\n",
prot);
else
printf ("\n");
printf("\n");
cnt = s_last - s_first + 1;
if (cnt == FLASH_TOT_SECT) {
printf("Erasing flash, Please Wait \n");
if(erase_flash() < 0) {
if (erase_flash() < 0) {
printf("Erasing flash failed \n");
return FLASH_FAIL;
}
@ -164,7 +165,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
printf("Erasing Flash locations, Please Wait\n");
for (i = s_first; i <= s_last; i++) {
if (info->protect[i] == 0) { /* not protected */
if(erase_block_flash(i, info->start[i]) < 0) {
if (erase_block_flash(i, info->start[i]) < 0) {
printf("Error Sector erasing \n");
return FLASH_FAIL;
}
@ -178,13 +179,12 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int ret;
ret = write_data(addr, cnt, 1, (int *) src);
if(ret == FLASH_FAIL)
ret = write_data(addr, cnt, 1, (int *)src);
if (ret == FLASH_FAIL)
return ERR_NOT_ERASED;
return FLASH_SUCCESS;
}
int write_data(long lStart, long lCount, long lStride, int *pnData)
{
long i = 0;
@ -198,20 +198,23 @@ int write_data(long lStart, long lCount, long lStride, int *pnData)
for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
for (iShift = 0, j = 0; (j < iNumWords);
j++, ulOffset += (lStride * 2)) {
j++, ulOffset += (lStride * 2)) {
if ((ulOffset >= INVALIDLOCNSTART)
&& (ulOffset < INVALIDLOCNEND)) {
printf("Invalid locations, Try writing to another location \n");
&& (ulOffset < INVALIDLOCNEND)) {
printf
("Invalid locations, Try writing to another location \n");
return FLASH_FAIL;
}
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset,&d);
if(d != 0xffff) {
printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset);
read_flash(ulOffset, &d);
if (d != 0xffff) {
printf
("Flash not erased at offset 0x%x Please erase to reprogram \n",
ulOffset);
return FLASH_FAIL;
}
unlock_flash(ulOffset);
if(write_flash(ulOffset, (pnData[i] >> iShift)) < 0) {
if (write_flash(ulOffset, (pnData[i] >> iShift)) < 0) {
printf("Error programming the flash \n");
return FLASH_FAIL;
}
@ -220,17 +223,18 @@ int write_data(long lStart, long lCount, long lStride, int *pnData)
}
if (nLeftover > 0) {
if ((ulOffset >= INVALIDLOCNSTART)
&& (ulOffset < INVALIDLOCNEND))
return FLASH_FAIL;
&& (ulOffset < INVALIDLOCNEND))
return FLASH_FAIL;
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset,&d);
if(d != 0xffff) {
printf("Flash already programmed. Please erase to reprogram \n");
printf("uloffset = 0x%x \t d = 0x%x\n",ulOffset,d);
read_flash(ulOffset, &d);
if (d != 0xffff) {
printf
("Flash already programmed. Please erase to reprogram \n");
printf("uloffset = 0x%x \t d = 0x%x\n", ulOffset, d);
return FLASH_FAIL;
}
unlock_flash(ulOffset);
if(write_flash(ulOffset, pnData[i]) < 0) {
if (write_flash(ulOffset, pnData[i]) < 0) {
printf("Error programming the flash \n");
return FLASH_FAIL;
}
@ -252,8 +256,8 @@ int read_data(long ulStart, long lCount, long lStride, int *pnData)
for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
for (iShift = 0, j = 0; j < iNumWords; j += 2) {
if ((ulOffset >= INVALIDLOCNSTART)
&& (ulOffset < INVALIDLOCNEND))
return FLASH_FAIL;
&& (ulOffset < INVALIDLOCNEND))
return FLASH_FAIL;
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset, &nLow);
@ -265,8 +269,8 @@ int read_data(long ulStart, long lCount, long lStride, int *pnData)
}
if (nLeftover > 0) {
if ((ulOffset >= INVALIDLOCNSTART)
&& (ulOffset < INVALIDLOCNEND))
return FLASH_FAIL;
&& (ulOffset < INVALIDLOCNEND))
return FLASH_FAIL;
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset, &pnData[i]);
@ -279,10 +283,10 @@ int write_flash(long nOffset, int nValue)
long addr;
addr = (CFG_FLASH_BASE + nOffset);
asm("ssync;");
*(unsigned volatile short *) addr = nValue;
asm("ssync;");
if(poll_toggle_bit(nOffset) < 0)
sync();
*(unsigned volatile short *)addr = nValue;
sync();
if (poll_toggle_bit(nOffset) < 0)
return FLASH_FAIL;
return FLASH_SUCCESS;
}
@ -294,29 +298,30 @@ int read_flash(long nOffset, int *pnValue)
if (nOffset != 0x2)
reset_flash();
asm("ssync;");
nValue = *(volatile unsigned short *) addr;
asm("ssync;");
sync();
nValue = *(volatile unsigned short *)addr;
sync();
*pnValue = nValue;
return TRUE;
}
int poll_toggle_bit(long lOffset)
{
unsigned int u1,u2;
unsigned int u1, u2;
unsigned long timeout = 0xFFFFFFFF;
volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset);
while(1) {
if(timeout < 0)
volatile unsigned long *FB =
(volatile unsigned long *)(0x20000000 + lOffset);
while (1) {
if (timeout < 0)
break;
u1 = *(volatile unsigned short *)FB;
u2 = *(volatile unsigned short *)FB;
if((u1 & 0x0040) == (u2 & 0x0040))
if ((u1 & 0x0040) == (u2 & 0x0040))
return FLASH_SUCCESS;
if((u2 & 0x0020) == 0x0000)
if ((u2 & 0x0020) == 0x0000)
continue;
u1 = *(volatile unsigned short *)FB;
if((u2 & 0x0040) == (u1 & 0x0040))
if ((u2 & 0x0040) == (u1 & 0x0040))
return FLASH_SUCCESS;
else {
reset_flash();
@ -325,7 +330,8 @@ int poll_toggle_bit(long lOffset)
timeout--;
}
printf("Time out occured \n");
if(timeout <0) return FLASH_FAIL;
if (timeout < 0)
return FLASH_FAIL;
}
void reset_flash(void)
@ -344,7 +350,7 @@ int erase_flash(void)
write_flash(WRITESEQ5, WRITEDATA5);
write_flash(WRITESEQ6, WRITEDATA6);
if(poll_toggle_bit(0x0000) < 0)
if (poll_toggle_bit(0x0000) < 0)
return FLASH_FAIL;
write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1);
@ -354,7 +360,7 @@ int erase_flash(void)
write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5);
write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6);
if(poll_toggle_bit(SecFlashASec1Off) < 0)
if (poll_toggle_bit(SecFlashASec1Off) < 0)
return FLASH_FAIL;
write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1);
@ -364,7 +370,7 @@ int erase_flash(void)
write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5);
write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6);
if(poll_toggle_bit(PriFlashBOff) <0)
if (poll_toggle_bit(PriFlashBOff) < 0)
return FLASH_FAIL;
write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1);
@ -374,7 +380,7 @@ int erase_flash(void)
write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5);
write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6);
if(poll_toggle_bit(SecFlashBOff) < 0)
if (poll_toggle_bit(SecFlashBOff) < 0)
return FLASH_FAIL;
return FLASH_SUCCESS;
@ -397,7 +403,7 @@ int erase_block_flash(int nBlock, unsigned long address)
write_flash(ulSectorOff, BlockEraseVal);
if(poll_toggle_bit(ulSectorOff) < 0)
if (poll_toggle_bit(ulSectorOff) < 0)
return FLASH_FAIL;
return FLASH_SUCCESS;
@ -435,34 +441,34 @@ void get_sector_number(long ulOffset, int *pnSector)
if (ulOffset >= SecFlashAOff) {
if ((ulOffset < SecFlashASec1Off)
&& (ulOffset < SecFlashASec2Off)) {
nSector = SECT32;
&& (ulOffset < SecFlashASec2Off)) {
nSector = SECT32;
} else if ((ulOffset >= SecFlashASec2Off)
&& (ulOffset < SecFlashASec3Off)) {
nSector = SECT33;
&& (ulOffset < SecFlashASec3Off)) {
nSector = SECT33;
} else if ((ulOffset >= SecFlashASec3Off)
&& (ulOffset < SecFlashASec4Off)) {
nSector = SECT34;
&& (ulOffset < SecFlashASec4Off)) {
nSector = SECT34;
} else if ((ulOffset >= SecFlashASec4Off)
&& (ulOffset < SecFlashAEndOff)) {
nSector = SECT35;
&& (ulOffset < SecFlashAEndOff)) {
nSector = SECT35;
}
} else if (ulOffset >= SecFlashBOff) {
if ((ulOffset < SecFlashBSec1Off)
&& (ulOffset < SecFlashBSec2Off)) {
nSector = SECT36;
&& (ulOffset < SecFlashBSec2Off)) {
nSector = SECT36;
}
if ((ulOffset < SecFlashBSec2Off)
&& (ulOffset < SecFlashBSec3Off)) {
nSector = SECT37;
&& (ulOffset < SecFlashBSec3Off)) {
nSector = SECT37;
}
if ((ulOffset < SecFlashBSec3Off)
&& (ulOffset < SecFlashBSec4Off)) {
nSector = SECT38;
&& (ulOffset < SecFlashBSec4Off)) {
nSector = SECT38;
}
if ((ulOffset < SecFlashBSec4Off)
&& (ulOffset < SecFlashBEndOff)) {
nSector = SECT39;
&& (ulOffset < SecFlashBEndOff)) {
nSector = SECT39;
}
} else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) {
nSector = ulOffset & 0xffff0000;

22
board/ezkit533/psd4256.h → board/bf533-ezkit/psd4256.h
View file

@ -49,19 +49,19 @@
* Flash A Port A Bit definitions
*/
#define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */
#define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */
#define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */
#define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */
#define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */
#define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */
#define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */
#define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */
#define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */
#define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */
/*
* Flash A Port B Bit definitions
*/
#define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */
#define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */
#define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */
#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */
#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */
#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */
#define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */
#define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */
#define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */
#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */
#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */
#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */

16
board/ezkit533/u-boot.lds → board/bf533-ezkit/u-boot.lds.S
View file

@ -1,7 +1,7 @@
/*
* U-boot - u-boot.lds
* U-boot - u-boot.lds.S
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -25,6 +25,8 @@
* MA 02111-1307 USA
*/
#include <config.h>
OUTPUT_ARCH(bfin)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
@ -55,6 +57,7 @@ SECTIONS
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
. = CFG_MONITOR_BASE;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
@ -68,10 +71,11 @@ SECTIONS
cpu/bf533/interrupt.o (.text)
cpu/bf533/serial.o (.text)
common/dlmalloc.o (.text)
lib_generic/vsprintf.o (.text)
/* lib_blackfin/bf533_string.o (.text) */
/* lib_generic/vsprintf.o (.text) */
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
board/ezkit533/ezkit533.o (.text)
board/bf533-ezkit/bf533-ezkit.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
@ -119,9 +123,9 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
___u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
___u_boot_cmd_end = .;
__start___ex_table = .;

58
board/bf533-stamp/Makefile Normal file
View file

@ -0,0 +1,58 @@
#
# U-boot - Makefile
#
# Copyright (c) 2007 Analog Device Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o spi.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

136
board/stamp/stamp.c → board/bf533-stamp/bf533-stamp.c
View file

@ -27,9 +27,8 @@
#include <common.h>
#include <asm/mem_init.h>
#include "stamp.h"
DECLARE_GLOBAL_DATA_PTR;
#include <asm/io.h>
#include "bf533-stamp.h"
#define STATUS_LED_OFF 0
#define STATUS_LED_ON 1
@ -40,42 +39,45 @@ DECLARE_GLOBAL_DATA_PTR;
# define SHOW_BOOT_PROGRESS(arg)
#endif
int checkboard (void)
int checkboard(void)
{
printf ("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
printf ("Board: ADI BF533 Stamp board\n");
printf (" Support: http://blackfin.uclinux.org/\n");
printf (" Richard Klingler <richard@uclinux.net>\n");
#if (BFIN_CPU == ADSP_BF531)
printf("CPU: ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28);
#elif (BFIN_CPU == ADSP_BF532)
printf("CPU: ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28);
#else
printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
#endif
printf("Board: ADI BF533 Stamp board\n");
printf(" Support: http://blackfin.uclinux.org/\n");
return 0;
}
long int initdram (int board_type)
long int initdram(int board_type)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
printf ("SDRAM attributes:\n");
printf (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
"CAS Latency:%d cycles\n",
(SDRAM_tRCD >> 15),
(SDRAM_tRP >> 11),
(SDRAM_tRAS >> 6),
(SDRAM_tWR >> 19),
(SDRAM_CL >> 2));
printf ("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
printf ("Bank size = %d MB\n", 128);
printf("SDRAM attributes:\n");
printf
(" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
"CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11),
(SDRAM_tRAS >> 6), (SDRAM_tWR >> 19), (SDRAM_CL >> 2));
printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
printf("Bank size = %d MB\n", 128);
#endif
gd->bd->bi_memstart = CFG_SDRAM_BASE;
gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
return (gd->bd->bi_memsize);
}
void swap_to (int device_id)
void swap_to(int device_id)
{
if (device_id == ETHERNET) {
*pFIO_DIR = PF0;
asm ("ssync;");
sync();
*pFIO_FLAG_S = PF0;
asm ("ssync;");
sync();
} else if (device_id == FLASH) {
*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
*pFIO_FLAG_S = (PF4 | PF3 | PF2);
@ -85,9 +87,9 @@ void swap_to (int device_id)
*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
*pFIO_FLAG_D = (PF4 | PF3 | PF2);
asm ("ssync;");
sync();
} else {
printf ("Unknown bank to switch\n");
printf("Unknown bank to switch\n");
}
return;
@ -95,7 +97,7 @@ void swap_to (int device_id)
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
int misc_init_r (void)
int misc_init_r(void)
{
int i;
int cf_stat = 0;
@ -104,7 +106,7 @@ int misc_init_r (void)
*pFIO_EDGE = FIO_EDGE_CF_BITS;
*pFIO_POLAR = FIO_POLAR_CF_BITS;
for (i = 0; i < 0x300; i++)
asm ("nop;");
asm("nop;");
if ((*pFIO_FLAG_S) & CF_STAT_BITS) {
cf_stat = 0;
@ -115,37 +117,36 @@ int misc_init_r (void)
*pFIO_EDGE = FIO_EDGE_BITS;
*pFIO_POLAR = FIO_POLAR_BITS;
if (cf_stat) {
printf ("Booting from COMPACT flash\n");
printf("Booting from COMPACT flash\n");
/* Set cycle time for CF */
*(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL;
*(volatile unsigned long *)ambctl1 = CF_AMBCTL1VAL;
for (i = 0; i < 0x1000; i++)
asm ("nop;");
asm("nop;");
for (i = 0; i < 0x1000; i++)
asm ("nop;");
asm("nop;");
for (i = 0; i < 0x1000; i++)
asm ("nop;");
asm("nop;");
serial_setbrg ();
ide_init ();
serial_setbrg();
ide_init();
setenv ("bootargs", "");
setenv ("bootcmd",
"fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
setenv("bootargs", "");
setenv("bootcmd",
"fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000");
} else {
printf ("Booting from FLASH\n");
printf("Booting from FLASH\n");
}
return 1;
return 0;
}
#endif
#ifdef CONFIG_STAMP_CF
void cf_outb (unsigned char val, volatile unsigned char *addr)
void cf_outb(unsigned char val, volatile unsigned char *addr)
{
/*
* Set PF1 PF0 respectively to 0 1 to divert address
@ -153,70 +154,70 @@ void cf_outb (unsigned char val, volatile unsigned char *addr)
*/
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
asm ("ssync;");
sync();
*(addr) = val;
asm ("ssync;");
sync();
/* Setback PF1 PF0 to 0 0 to address external
* memory banks */
*(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0;
asm ("ssync;");
*(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
sync();
}
unsigned char cf_inb (volatile unsigned char *addr)
unsigned char cf_inb(volatile unsigned char *addr)
{
volatile unsigned char c;
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
asm ("ssync;");
sync();
c = *(addr);
asm ("ssync;");
sync();
*pFIO_FLAG_C = CF_PF1_PF0;
asm ("ssync;");
sync();
return c;
}
void cf_insw (unsigned short *sect_buf, unsigned short *addr, int words)
void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
{
int i;
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
asm ("ssync;");
sync();
for (i = 0; i < words; i++) {
*(sect_buf + i) = *(addr);
asm ("ssync;");
sync();
}
*pFIO_FLAG_C = CF_PF1_PF0;
asm ("ssync;");
sync();
}
void cf_outsw (unsigned short *addr, unsigned short *sect_buf, int words)
void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
{
int i;
*pFIO_FLAG_S = CF_PF0;
*pFIO_FLAG_C = CF_PF1;
asm ("ssync;");
sync();
for (i = 0; i < words; i++) {
*(addr) = *(sect_buf + i);
asm ("ssync;");
sync();
}
*pFIO_FLAG_C = CF_PF1_PF0;
asm ("ssync;");
sync();
}
#endif
void stamp_led_set (int LED1, int LED2, int LED3)
void stamp_led_set(int LED1, int LED2, int LED3)
{
*pFIO_INEN &= ~(PF2 | PF3 | PF4);
*pFIO_DIR |= (PF2 | PF3 | PF4);
@ -233,31 +234,31 @@ void stamp_led_set (int LED1, int LED2, int LED3)
*pFIO_FLAG_S = PF4;
else
*pFIO_FLAG_C = PF4;
asm ("ssync;");
sync();
}
void show_boot_progress (int status)
void show_boot_progress(int status)
{
switch (status) {
case 1:
stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
break;
case 2:
stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
break;
case 3:
stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
break;
case 4:
stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
break;
case 5:
case 6:
stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
break;
case 7:
case 8:
stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
break;
case 9:
case 10:
@ -266,11 +267,10 @@ void show_boot_progress (int status)
case 13:
case 14:
case 15:
stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF,
STATUS_LED_OFF);
stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_OFF);
break;
default:
stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
break;
}
}

1
board/stamp/stamp.h → board/bf533-stamp/bf533-stamp.h
View file

@ -36,7 +36,6 @@ extern volatile unsigned long *amgctl;
extern unsigned long pll_div_fact;
extern void serial_setbrg(void);
extern void pll_set(int vco, int crystal_frq, int pll_div);
/* Definitions used in Compact Flash Boot support */
#define FIO_EDGE_CF_BITS 0x0000

4
board/stamp/config.mk → board/bf533-stamp/config.mk
View file

@ -20,6 +20,6 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
TEXT_BASE = 0x07FC0000
PLATFORM_CPPFLAGS += -I$(TOPDIR)

473
board/bf533-stamp/spi.c Normal file
View file

@ -0,0 +1,473 @@
/****************************************************************************
* SPI flash driver for M25P64
****************************************************************************/
#include <common.h>
#include <linux/ctype.h>
#include <asm/io.h>
#if defined(CONFIG_SPI)
/*Application definitions */
#define NUM_SECTORS 128 /* number of sectors */
#define SECTOR_SIZE 0x10000
#define NOP_NUM 1000
#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) /*Settings to the SPI_CTL */
#define TIMOD01 (0x01) /*stes the SPI to work with core instructions */
/*Flash commands */
#define SPI_WREN (0x06) /*Set Write Enable Latch */
#define SPI_WRDI (0x04) /*Reset Write Enable Latch */
#define SPI_RDSR (0x05) /*Read Status Register */
#define SPI_WRSR (0x01) /*Write Status Register */
#define SPI_READ (0x03) /*Read data from memory */
#define SPI_PP (0x02) /*Program Data into memory */
#define SPI_SE (0xD8) /*Erase one sector in memory */
#define SPI_BE (0xC7) /*Erase all memory */
#define WIP (0x1) /*Check the write in progress bit of the SPI status register */
#define WEL (0x2) /*Check the write enable bit of the SPI status register */
#define TIMEOUT 350000000
typedef enum {
NO_ERR,
POLL_TIMEOUT,
INVALID_SECTOR,
INVALID_BLOCK,
} ERROR_CODE;
void spi_init_f(void);
void spi_init_r(void);
ssize_t spi_read(uchar *, int, uchar *, int);
ssize_t spi_write(uchar *, int, uchar *, int);
char ReadStatusRegister(void);
void Wait_For_SPIF(void);
void SetupSPI(const int spi_setting);
void SPI_OFF(void);
void SendSingleCommand(const int iCommand);
ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector);
ERROR_CODE EraseBlock(int nBlock);
ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData);
ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData);
ERROR_CODE Wait_For_Status(char Statusbit);
ERROR_CODE Wait_For_WEL(void);
/* -------------------
* Variables
* ------------------- */
/* **************************************************************************
*
* Function: spi_init_f
*
* Description: Init SPI-Controller (ROM part)
*
* return: ---
*
* *********************************************************************** */
void spi_init_f(void)
{
}
/* **************************************************************************
*
* Function: spi_init_r
*
* Description: Init SPI-Controller (RAM part) -
* The malloc engine is ready and we can move our buffers to
* normal RAM
*
* return: ---
*
* *********************************************************************** */
void spi_init_r(void)
{
return;
}
/****************************************************************************
* Function: spi_write
**************************************************************************** */
ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len)
{
unsigned long offset;
int start_block, end_block;
int start_byte, end_byte;
ERROR_CODE result = NO_ERR;
uchar temp[SECTOR_SIZE];
int i, num;
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
/* Get the start block number */
result = GetSectorNumber(offset, &start_block);
if (result == INVALID_SECTOR) {
printf("Invalid sector! ");
return 0;
}
/* Get the end block number */
result = GetSectorNumber(offset + len - 1, &end_block);
if (result == INVALID_SECTOR) {
printf("Invalid sector! ");
return 0;
}
for (num = start_block; num <= end_block; num++) {
ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
start_byte = num * SECTOR_SIZE;
end_byte = (num + 1) * SECTOR_SIZE - 1;
if (start_byte < offset)
start_byte = offset;
if (end_byte > (offset + len))
end_byte = (offset + len - 1);
for (i = start_byte; i <= end_byte; i++)
temp[i - num * SECTOR_SIZE] = buffer[i - offset];
EraseBlock(num);
result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
if (result != NO_ERR)
return 0;
printf(".");
}
return len;
}
/****************************************************************************
* Function: spi_read
**************************************************************************** */
ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len)
{
unsigned long offset;
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
ReadData(offset, len, (int *)buffer);
return len;
}
void SendSingleCommand(const int iCommand)
{
unsigned short dummy;
/*turns on the SPI in single write mode */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
/*sends the actual command to the SPI TX register */
*pSPI_TDBR = iCommand;
sync();
/*The SPI status register will be polled to check the SPIF bit */
Wait_For_SPIF();
dummy = *pSPI_RDBR;
/*The SPI will be turned off */
SPI_OFF();
}
void SetupSPI(const int spi_setting)
{
if (icache_status() || dcache_status())
udelay(CONFIG_CCLK_HZ / 50000000);
/*sets up the PF2 to be the slave select of the SPI */
*pSPI_FLG = 0xFB04;
*pSPI_BAUD = CONFIG_SPI_BAUD;
*pSPI_CTL = spi_setting;
sync();
}
void SPI_OFF(void)
{
*pSPI_CTL = 0x0400; /* disable SPI */
*pSPI_FLG = 0;
*pSPI_BAUD = 0;
sync();
udelay(CONFIG_CCLK_HZ / 50000000);
}
void Wait_For_SPIF(void)
{
unsigned short dummyread;
while ((*pSPI_STAT & TXS)) ;
while (!(*pSPI_STAT & SPIF)) ;
while (!(*pSPI_STAT & RXS)) ;
dummyread = *pSPI_RDBR; /* Read dummy to empty the receive register */
}
ERROR_CODE Wait_For_WEL(void)
{
int i;
char status_register = 0;
ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
for (i = 0; i < TIMEOUT; i++) {
status_register = ReadStatusRegister();
if ((status_register & WEL)) {
ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
break;
}
ErrorCode = POLL_TIMEOUT; /* Time out error */
};
return ErrorCode;
}
ERROR_CODE Wait_For_Status(char Statusbit)
{
int i;
char status_register = 0xFF;
ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
for (i = 0; i < TIMEOUT; i++) {
status_register = ReadStatusRegister();
if (!(status_register & Statusbit)) {
ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
break;
}
ErrorCode = POLL_TIMEOUT; /* Time out error */
};
return ErrorCode;
}
char ReadStatusRegister(void)
{
char status_register = 0;
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */
*pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
*pSPI_TDBR = 0; /*send dummy to receive the status register */
sync();
Wait_For_SPIF(); /*wait until the data has been sent */
status_register = *pSPI_RDBR; /*read the status register */
SPI_OFF(); /* Turn off the SPI */
return status_register;
}
ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector)
{
int nSector = 0;
ERROR_CODE ErrorCode = NO_ERR;
if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) {
ErrorCode = INVALID_SECTOR;
return ErrorCode;
}
nSector = (int)ulOffset / 0x10000;
*pnSector = nSector;
/* ok */
return ErrorCode;
}
ERROR_CODE EraseBlock(int nBlock)
{
unsigned long ulSectorOff = 0x0, ShiftValue;
ERROR_CODE ErrorCode = NO_ERR;
/* if the block is invalid just return */
if ((nBlock < 0) || (nBlock > NUM_SECTORS)) {
ErrorCode = INVALID_BLOCK; /* tells us if there was an error erasing flash */
return ErrorCode;
}
/* figure out the offset of the block in flash */
if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) {
ulSectorOff = (nBlock * SECTOR_SIZE);
} else {
ErrorCode = INVALID_BLOCK; /* tells us if there was an error erasing flash */
return ErrorCode;
}
/* A write enable instruction must previously have been executed */
SendSingleCommand(SPI_WREN);
/*The status register will be polled to check the write enable latch "WREN" */
ErrorCode = Wait_For_WEL();
if (POLL_TIMEOUT == ErrorCode) {
printf("SPI Erase block error\n");
return ErrorCode;
} else
/*Turn on the SPI to send single commands */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
/* Send the erase block command to the flash followed by the 24 address */
/* to point to the start of a sector. */
*pSPI_TDBR = SPI_SE;
sync();
Wait_For_SPIF();
ShiftValue = (ulSectorOff >> 16); /* Send the highest byte of the 24 bit address at first */
*pSPI_TDBR = ShiftValue;
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
ShiftValue = (ulSectorOff >> 8); /* Send the middle byte of the 24 bit address at second */
*pSPI_TDBR = ShiftValue;
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
*pSPI_TDBR = ulSectorOff; /* Send the lowest byte of the 24 bit address finally */
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
/*Turns off the SPI */
SPI_OFF();
/* Poll the status register to check the Write in Progress bit */
/* Sector erase takes time */
ErrorCode = Wait_For_Status(WIP);
/* block erase should be complete */
return ErrorCode;
}
/*****************************************************************************
* ERROR_CODE ReadData()
*
* Read a value from flash for verify purpose
*
* Inputs: unsigned long ulStart - holds the SPI start address
* int pnData - pointer to store value read from flash
* long lCount - number of elements to read
***************************************************************************** */
ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
{
unsigned long ShiftValue;
char *cnData;
int i;
cnData = (char *)pnData; /* Pointer cast to be able to increment byte wise */
/* Start SPI interface */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
*pSPI_TDBR = SPI_READ; /* Send the read command to SPI device */
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
ShiftValue = (ulStart >> 16); /* Send the highest byte of the 24 bit address at first */
*pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
ShiftValue = (ulStart >> 8); /* Send the middle byte of the 24 bit address at second */
*pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
*pSPI_TDBR = ulStart; /* Send the lowest byte of the 24 bit address finally */
sync();
Wait_For_SPIF(); /* Wait until the instruction has been sent */
/* After the SPI device address has been placed on the MOSI pin the data can be */
/* received on the MISO pin. */
for (i = 0; i < lCount; i++) {
*pSPI_TDBR = 0; /*send dummy */
sync();
while (!(*pSPI_STAT & RXS)) ;
*cnData++ = *pSPI_RDBR; /*read */
if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0))
printf(".");
}
SPI_OFF(); /* Turn off the SPI */
return NO_ERR;
}
ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
int *iDataSource, long *lWriteCount)
{
unsigned long ulWAddr;
long lWTransferCount = 0;
int i;
char iData;
char *temp = (char *)iDataSource;
ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
/* First, a Write Enable Command must be sent to the SPI. */
SendSingleCommand(SPI_WREN);
/* Second, the SPI Status Register will be tested whether the */
/* Write Enable Bit has been set. */
ErrorCode = Wait_For_WEL();
if (POLL_TIMEOUT == ErrorCode) {
printf("SPI Write Time Out\n");
return ErrorCode;
} else
/* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turns the SPI on */
*pSPI_TDBR = SPI_PP;
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
ulWAddr = (ulStartAddr >> 16);
*pSPI_TDBR = ulWAddr;
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
ulWAddr = (ulStartAddr >> 8);
*pSPI_TDBR = ulWAddr;
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
ulWAddr = ulStartAddr;
*pSPI_TDBR = ulWAddr;
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
/* Fourth, maximum number of 256 bytes will be taken from the Buffer */
/* and sent to the SPI device. */
for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
iData = *temp;
*pSPI_TDBR = iData;
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
temp++;
}
SPI_OFF(); /* Turns the SPI off */
/* Sixth, the SPI Write in Progress Bit must be toggled to ensure the */
/* programming is done before start of next transfer. */
ErrorCode = Wait_For_Status(WIP);
if (POLL_TIMEOUT == ErrorCode) {
printf("SPI Program Time out!\n");
return ErrorCode;
} else
*lWriteCount = lWTransferCount;
return ErrorCode;
}
ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData)
{
unsigned long ulWStart = ulStart;
long lWCount = lCount, lWriteCount;
long *pnWriteCount = &lWriteCount;
ERROR_CODE ErrorCode = NO_ERR;
while (lWCount != 0) {
ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
/* After each function call of WriteFlash the counter must be adjusted */
lWCount -= *pnWriteCount;
/* Also, both address pointers must be recalculated. */
ulWStart += *pnWriteCount;
pnData += *pnWriteCount / 4;
}
/* return the appropriate error code */
return ErrorCode;
}
#endif /* CONFIG_SPI */

17
board/stamp/u-boot.lds → board/bf533-stamp/u-boot.lds.S
View file

@ -1,7 +1,7 @@
/*
* U-boot - u-boot.lds
* U-boot - u-boot.lds.S
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -25,6 +25,8 @@
* MA 02111-1307 USA
*/
#include <config.h>
OUTPUT_ARCH(bfin)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
@ -55,6 +57,7 @@ SECTIONS
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
. = CFG_MONITOR_BASE;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
@ -68,9 +71,11 @@ SECTIONS
cpu/bf533/interrupt.o (.text)
cpu/bf533/serial.o (.text)
common/dlmalloc.o (.text)
lib_generic/vsprintf.o (.text)
/* lib_blackfin/bf533_string.o (.text) */
/* lib_generic/vsprintf.o (.text) */
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
/* lib_generic/zlib.o (.text) */
/* board/stamp/stamp.o (.text) */
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
@ -118,9 +123,9 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
___u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
___u_boot_cmd_end = .;
__start___ex_table = .;

58
board/bf537-stamp/Makefile Normal file
View file

@ -0,0 +1,58 @@
#
# U-boot - Makefile
#
# Copyright (c) 2005-2007 Analog Device Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o flash.o ether_bf537.o post-memory.o stm_m25p64.o cmd_bf537led.o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

437
board/bf537-stamp/bf537-stamp.c Normal file
View file

@ -0,0 +1,437 @@
/*
* U-boot - BF537.c
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <command.h>
#include <asm/blackfin.h>
#include <asm/io.h>
#include "ether_bf537.h"
#define POST_WORD_ADDR 0xFF903FFC
/*
* the bootldr command loads an address, checks to see if there
* is a Boot stream that the on-chip BOOTROM can understand,
* and loads it via the BOOTROM Callback. It is possible
* to also add booting from SPI, or TWI, but this function does
* not currently support that.
*/
int do_bootldr(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong addr, entry;
ulong *data;
/* Get the address */
if (argc < 2) {
addr = load_addr;
} else {
addr = simple_strtoul(argv[1], NULL, 16);
}
/* Check if it is a LDR file */
data = (ulong *) addr;
if (*data == 0xFF800060 || *data == 0xFF800040 || *data == 0xFF800020) {
/* We want to boot from FLASH or SDRAM */
entry = _BOOTROM_BOOT_DXE_FLASH;
printf("## Booting ldr image at 0x%08lx ...\n", addr);
if (icache_status())
icache_disable();
if (dcache_status())
dcache_disable();
__asm__("R7=%[a];\n" "P0=%[b];\n" "JUMP (P0);\n":
:[a] "d"(addr),[b] "a"(entry)
:"R7", "P0");
} else {
printf("## No ldr image at address 0x%08lx\n", addr);
}
return 0;
}
U_BOOT_CMD(bootldr, 2, 0, do_bootldr,
"bootldr - boot ldr image from memory\n",
"[addr]\n - boot ldr image stored in memory\n");
int checkboard(void)
{
#if (BFIN_CPU == ADSP_BF534)
printf("CPU: ADSP BF534 Rev.: 0.%d\n", *pCHIPID >> 28);
#elif (BFIN_CPU == ADSP_BF536)
printf("CPU: ADSP BF536 Rev.: 0.%d\n", *pCHIPID >> 28);
#else
printf("CPU: ADSP BF537 Rev.: 0.%d\n", *pCHIPID >> 28);
#endif
printf("Board: ADI BF537 stamp board\n");
printf(" Support: http://blackfin.uclinux.org/\n");
return 0;
}
#if defined(CONFIG_BFIN_IDE)
void cf_outb(unsigned char val, volatile unsigned char *addr)
{
*(addr) = val;
sync();
}
unsigned char cf_inb(volatile unsigned char *addr)
{
volatile unsigned char c;
c = *(addr);
sync();
return c;
}
void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
{
int i;
for (i = 0; i < words; i++)
*(sect_buf + i) = *(addr);
sync();
}
void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
{
int i;
for (i = 0; i < words; i++)
*(addr) = *(sect_buf + i);
sync();
}
#endif /* CONFIG_BFIN_IDE */
long int initdram(int board_type)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");
brate = simple_strtoul(tmp, NULL, 16);
printf("Serial Port initialized with Baud rate = %x\n", brate);
printf("SDRAM attributes:\n");
printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
"tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
3, 3, 6, 2, 3);
printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
#endif
gd->bd->bi_memstart = CFG_SDRAM_BASE;
gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
return CFG_MAX_RAM_SIZE;
}
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
char nid[32];
unsigned char *pMACaddr = (unsigned char *)0x203F0000;
u8 SrcAddr[6] = { 0x02, 0x80, 0xAD, 0x20, 0x31, 0xB8 };
#if (CONFIG_COMMANDS & CFG_CMD_NET)
/* The 0xFF check here is to make sure we don't use the address
* in flash if it's simply been erased (aka all 0xFF values) */
if (getenv("ethaddr") == NULL && is_valid_ether_addr(pMACaddr)) {
sprintf(nid, "%02x:%02x:%02x:%02x:%02x:%02x",
pMACaddr[0], pMACaddr[1],
pMACaddr[2], pMACaddr[3], pMACaddr[4], pMACaddr[5]);
setenv("ethaddr", nid);
}
if (getenv("ethaddr")) {
SetupMacAddr(SrcAddr);
}
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
#endif /* BFIN_BOOT_MODE == BF537_BYPASS_BOOT */
#if defined(CONFIG_BFIN_IDE)
#if defined(CONFIG_BFIN_TRUE_IDE)
/* Enable ATASEL when in True IDE mode */
printf("Using CF True IDE Mode\n");
cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
udelay(1000);
#elif defined(CONFIG_BFIN_CF_IDE)
/* Disable ATASEL when we're in Common Memory Mode */
printf("Using CF Common Memory Mode\n");
cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
udelay(1000);
#elif defined(CONFIG_BFIN_HDD_IDE)
printf("Using HDD IDE Mode\n");
#endif
ide_init();
#endif /* CONFIG_BFIN_IDE */
return 0;
}
#endif /* CONFIG_MISC_INIT_R */
#ifdef CONFIG_POST
#if (BFIN_BOOT_MODE != BF537_BYPASS_BOOT)
/* Using sw10-PF5 as the hotkey */
int post_hotkeys_pressed(void)
{
return 0;
}
#else
/* Using sw10-PF5 as the hotkey */
int post_hotkeys_pressed(void)
{
int delay = 3;
int i;
unsigned short value;
*pPORTF_FER &= ~PF5;
*pPORTFIO_DIR &= ~PF5;
*pPORTFIO_INEN |= PF5;
printf("########Press SW10 to enter Memory POST########: %2d ", delay);
while (delay--) {
for (i = 0; i < 100; i++) {
value = *pPORTFIO & PF5;
if (value != 0) {
break;
}
udelay(10000);
}
printf("\b\b\b%2d ", delay);
}
printf("\b\b\b 0");
printf("\n");
if (value == 0)
return 0;
else {
printf("Hotkey has been pressed, Enter POST . . . . . .\n");
return 1;
}
}
#endif
#endif
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
void post_word_store(ulong a)
{
volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
*save_addr = a;
}
ulong post_word_load(void)
{
volatile ulong *save_addr = (volatile ulong *)POST_WORD_ADDR;
return *save_addr;
}
#endif
#ifdef CONFIG_POST
int uart_post_test(int flags)
{
return 0;
}
#define BLOCK_SIZE 0x10000
#define VERIFY_ADDR 0x2000000
extern int erase_block_flash(int);
extern int write_data(long lStart, long lCount, uchar * pnData);
int flash_post_test(int flags)
{
unsigned short *pbuf, *temp;
int offset, n, i;
int value = 0;
int result = 0;
printf("\n");
pbuf = (unsigned short *)VERIFY_ADDR;
temp = pbuf;
for (n = FLASH_START_POST_BLOCK; n < FLASH_END_POST_BLOCK; n++) {
offset = (n - 7) * BLOCK_SIZE;
printf("--------Erase block:%2d..", n);
erase_block_flash(n);
printf("OK\r");
printf("--------Program block:%2d...", n);
write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
printf("OK\r");
printf("--------Verify block:%2d...", n);
for (i = 0; i < BLOCK_SIZE; i += 2) {
if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
*temp++) {
value = 1;
result = 1;
}
}
if (value)
printf("failed\n");
else
printf("OK %3d%%\r",
(int)(
(n + 1 -
FLASH_START_POST_BLOCK) *
100 / (FLASH_END_POST_BLOCK -
FLASH_START_POST_BLOCK)));
temp = pbuf;
value = 0;
}
printf("\n");
if (result)
return -1;
else
return 0;
}
/****************************************************
* LED1 ---- PF6 LED2 ---- PF7 *
* LED3 ---- PF8 LED4 ---- PF9 *
* LED5 ---- PF10 LED6 ---- PF11 *
****************************************************/
int led_post_test(int flags)
{
*pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
*pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11;
*pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
*pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11);
udelay(1000000);
printf("LED1 on");
*pPORTFIO |= PF6;
udelay(1000000);
printf("\b\b\b\b\b\b\b");
printf("LED2 on");
*pPORTFIO |= PF7;
udelay(1000000);
printf("\b\b\b\b\b\b\b");
printf("LED3 on");
*pPORTFIO |= PF8;
udelay(1000000);
printf("\b\b\b\b\b\b\b");
printf("LED4 on");
*pPORTFIO |= PF9;
udelay(1000000);
printf("\b\b\b\b\b\b\b");
printf("LED5 on");
*pPORTFIO |= PF10;
udelay(1000000);
printf("\b\b\b\b\b\b\b");
printf("lED6 on");
*pPORTFIO |= PF11;
printf("\b\b\b\b\b\b\b ");
return 0;
}
/************************************************
* SW10 ---- PF5 SW11 ---- PF4 *
* SW12 ---- PF3 SW13 ---- PF2 *
************************************************/
int button_post_test(int flags)
{
int i, delay = 5;
unsigned short value = 0;
int result = 0;
*pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2);
*pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2);
*pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2);
printf("\n--------Press SW10: %2d ", delay);
while (delay--) {
for (i = 0; i < 100; i++) {
value = *pPORTFIO & PF5;
if (value != 0) {
break;
}
udelay(10000);
}
printf("\b\b\b%2d ", delay);
}
if (value != 0)
printf("\b\bOK");
else {
result = -1;
printf("\b\bfailed");
}
delay = 5;
printf("\n--------Press SW11: %2d ", delay);
while (delay--) {
for (i = 0; i < 100; i++) {
value = *pPORTFIO & PF4;
if (value != 0) {
break;
}
udelay(10000);
}
printf("\b\b\b%2d ", delay);
}
if (value != 0)
printf("\b\bOK");
else {
result = -1;
printf("\b\bfailed");
}
delay = 5;
printf("\n--------Press SW12: %2d ", delay);
while (delay--) {
for (i = 0; i < 100; i++) {
value = *pPORTFIO & PF3;
if (value != 0) {
break;
}
udelay(10000);
}
printf("\b\b\b%2d ", delay);
}
if (value != 0)
printf("\b\bOK");
else {
result = -1;
printf("\b\bfailed");
}
delay = 5;
printf("\n--------Press SW13: %2d ", delay);
while (delay--) {
for (i = 0; i < 100; i++) {
value = *pPORTFIO & PF2;
if (value != 0) {
break;
}
udelay(10000);
}
printf("\b\b\b%2d ", delay);
}
if (value != 0)
printf("\b\bOK");
else {
result = -1;
printf("\b\bfailed");
}
printf("\n");
return result;
}
#endif

201
board/bf537-stamp/cmd_bf537led.c Normal file
View file

@ -0,0 +1,201 @@
/*
* U-boot - cmd_bf537led.c
*
* Copyright (C) 2006 Aaron Gage, Ocean Optics Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <command.h>
#include <asm/blackfin.h>
#include <asm-blackfin/string.h>
#ifdef CONFIG_BF537_STAMP_LEDCMD
/* Define the command usage in a reusable way */
#define USAGE_LONG \
"led <number> <action>\n" \
" <number> - Index (0-5) of LED to change, or \"all\"\n" \
" <action> - Must be one of:\n" \
" on off toggle\n"
/* Number of LEDs supported by the board */
#define NUMBER_LEDS 6
/* The BF537 stamp has 6 LEDs. This mask indicates that all should be lit. */
#define LED_ALL_MASK 0x003F
void show_cmd_usage(void);
void set_led_state(int index, int state);
void configure_GPIO_to_output(int index);
/* Map of LEDs according to their GPIO ports. This can be rearranged or
* otherwise changed to account for different GPIO configurations.
*/
int led_ports[] = { PF6, PF7, PF8, PF9, PF10, PF11 };
#define ACTION_TOGGLE -1
#define ACTION_OFF 0
#define ACTION_ON 1
#define LED_STATE_OFF 0
#define LED_STATE_ON 1
/* This is a trivial atoi implementation since we don't have one available */
int atoi(char *string)
{
int length;
int retval = 0;
int i;
int sign = 1;
length = strlen(string);
for (i = 0; i < length; i++) {
if (0 == i && string[0] == '-') {
sign = -1;
continue;
}
if (string[i] > '9' || string[i] < '0') {
break;
}
retval *= 10;
retval += string[i] - '0';
}
retval *= sign;
return retval;
}
int do_bf537led(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int led_mask = 0;
int led_current_state = 0;
int action = ACTION_OFF;
int temp;
if (3 != argc) {
/* Not enough arguments, so just show usage information */
show_cmd_usage();
return 1;
}
if (strcmp(argv[1], "all") == 0) {
led_mask = LED_ALL_MASK;
} else {
temp = atoi(argv[1]);
if (temp < 0 || temp >= NUMBER_LEDS) {
printf("Invalid LED number [%s]\n", argv[1]);
show_cmd_usage();
return 2;
}
led_mask |= (1 << temp);
}
if (strcmp(argv[2], "off") == 0) {
action = ACTION_OFF;
} else if (strcmp(argv[2], "on") == 0) {
action = ACTION_ON;
} else if (strcmp(argv[2], "toggle") == 0) {
action = ACTION_TOGGLE;
} else {
printf("Invalid action [%s]\n", argv[2]);
show_cmd_usage();
return 3;
}
for (temp = 0; temp < NUMBER_LEDS; temp++) {
if ((led_mask & (1 << temp)) > 0) {
/*
* It is possible that the user has wired one of PF6-PF11 to
* something other than an LED, so this will only change a pin
* to output if the user has indicated a state change. This may
* happen a lot, but this way is safer than just setting all pins
* to output.
*/
configure_GPIO_to_output(temp);
led_current_state =
((*pPORTFIO & led_ports[temp]) >
0) ? LED_STATE_ON : LED_STATE_OFF;
/*
printf("LED state for index %d (%x) is %d\n", temp, led_ports[temp],
led_current_state);
printf("*pPORTFIO is %x\n", *pPORTFIO);
*/
if (ACTION_ON == action
|| (ACTION_TOGGLE == action
&& 0 == led_current_state)) {
printf("Turning LED %d on\n", temp);
set_led_state(temp, LED_STATE_ON);
} else {
printf("Turning LED %d off\n", temp);
set_led_state(temp, LED_STATE_OFF);
}
}
}
return 0;
}
/*
* The GPIO pins that go to the LEDs on the BF537 stamp must be configured
* as output. This function simply configures them that way. This could
* be done to all of the GPIO lines at once, but if a user is using a
* custom board, this will try to be nice and only change the GPIO lines
* that the user specifically names.
*/
void configure_GPIO_to_output(int index)
{
int port;
port = led_ports[index];
/* Clear the Port F Function Enable Register */
*pPORTF_FER &= ~port;
/* Set the Port F I/O direction register */
*pPORTFIO_DIR |= port;
/* Clear the Port F I/O Input Enable Register */
*pPORTFIO_INEN &= ~port;
}
/* Enforce the given state on the GPIO line for the indicated LED */
void set_led_state(int index, int state)
{
int port;
port = led_ports[index];
if (LED_STATE_OFF == state) {
/* Clear the bit to turn off the LED */
*pPORTFIO &= ~port;
} else {
/* Set the bit to turn on the LED */
*pPORTFIO |= port;
}
}
/* Display usage information */
void show_cmd_usage()
{
printf("Usage:\n%s", USAGE_LONG);
}
/* Register information for u-boot to find this command */
U_BOOT_CMD(led, 3, 1, do_bf537led,
"led- Control BF537 stamp LEDs\n", USAGE_LONG);
#endif

25
board/bf537-stamp/config.mk Normal file
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#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
TEXT_BASE = 0x03FC0000

545
board/bf537-stamp/ether_bf537.c Normal file
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/*
* ADI Blackfin 537 MAC Ethernet
*
* Copyright (c) 2005 Analog Device, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <asm/blackfin.h>
#include <net.h>
#include <command.h>
#include <malloc.h>
#include "ether_bf537.h"
#ifdef CONFIG_POST
#include <post.h>
#endif
#undef DEBUG_ETHERNET
#ifdef DEBUG_ETHERNET
#define DEBUGF(fmt,args...) printf(fmt,##args)
#else
#define DEBUGF(fmt,args...)
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET)
#define RXBUF_BASE_ADDR 0xFF900000
#define TXBUF_BASE_ADDR 0xFF800000
#define TX_BUF_CNT 1
#define TOUT_LOOP 1000000
ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
static u16 txIdx; /* index of the current RX buffer */
static u16 rxIdx; /* index of the current TX buffer */
u8 SrcAddr[6];
u16 PHYregs[NO_PHY_REGS]; /* u16 PHYADDR; */
/* DMAx_CONFIG values at DMA Restart */
const ADI_DMA_CONFIG_REG rxdmacfg = { 1, 1, 2, 0, 0, 0, 0, 5, 7 };
#if 0
rxdmacfg.b_DMA_EN = 1; /* enabled */
rxdmacfg.b_WNR = 1; /* write to memory */
rxdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */
rxdmacfg.b_DMA2D = 0; /* N/A */
rxdmacfg.b_RESTART= 0; /* N/A */
rxdmacfg.b_DI_SEL = 0; /* N/A */
rxdmacfg.b_DI_EN = 0; /* no interrupt */
rxdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */
rxdmacfg.b_FLOW = 7; /* large desc flow */
#endif
const ADI_DMA_CONFIG_REG txdmacfg = { 1, 0, 2, 0, 0, 0, 0, 5, 7 };
#if 0
txdmacfg.b_DMA_EN = 1; /* enabled */
txdmacfg.b_WNR = 0; /* read from memory */
txdmacfg.b_WDSIZE = 2; /* wordsize is 32 bits */
txdmacfg.b_DMA2D = 0; /* N/A */
txdmacfg.b_RESTART= 0; /* N/A */
txdmacfg.b_DI_SEL = 0; /* N/A */
txdmacfg.b_DI_EN = 0; /* no interrupt */
txdmacfg.b_NDSIZE = 5; /* 5 half words is desc size. */
txdmacfg.b_FLOW = 7; /* large desc flow */
#endif
ADI_ETHER_BUFFER *SetupRxBuffer(int no);
ADI_ETHER_BUFFER *SetupTxBuffer(int no);
static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd);
static void bfin_EMAC_halt(struct eth_device *dev);
static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
int length);
static int bfin_EMAC_recv(struct eth_device *dev);
int bfin_EMAC_initialize(bd_t * bis)
{
struct eth_device *dev;
dev = (struct eth_device *)malloc(sizeof(*dev));
if (dev == NULL)
hang();
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "BF537 ETHERNET");
dev->iobase = 0;
dev->priv = 0;
dev->init = bfin_EMAC_init;
dev->halt = bfin_EMAC_halt;
dev->send = bfin_EMAC_send;
dev->recv = bfin_EMAC_recv;
eth_register(dev);
return 1;
}
static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
int length)
{
int i;
int result = 0;
unsigned int *buf;
buf = (unsigned int *)packet;
if (length <= 0) {
printf("Ethernet: bad packet size: %d\n", length);
goto out;
}
if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
printf("Ethernet: tx DMA error\n");
goto out;
}
for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
if (i > TOUT_LOOP) {
puts("Ethernet: tx time out\n");
goto out;
}
}
txbuf[txIdx]->FrmData->NoBytes = length;
memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
*pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
*pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
*pEMAC_OPMODE |= TE;
for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
if (i > TOUT_LOOP) {
puts("Ethernet: tx error\n");
goto out;
}
}
result = txbuf[txIdx]->StatusWord;
txbuf[txIdx]->StatusWord = 0;
if ((txIdx + 1) >= TX_BUF_CNT)
txIdx = 0;
else
txIdx++;
out:
DEBUGF("BFIN EMAC send: length = %d\n", length);
return result;
}
static int bfin_EMAC_recv(struct eth_device *dev)
{
int length = 0;
for (;;) {
if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
length = -1;
break;
}
if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
printf("Ethernet: rx dma overrun\n");
break;
}
if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
printf("Ethernet: rx error\n");
break;
}
length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
if (length <= 4) {
printf("Ethernet: bad frame\n");
break;
}
NetRxPackets[rxIdx] =
(volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
NetReceive(NetRxPackets[rxIdx], length - 4);
*pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
rxbuf[rxIdx]->StatusWord = 0x00000000;
if ((rxIdx + 1) >= PKTBUFSRX)
rxIdx = 0;
else
rxIdx++;
}
return length;
}
/**************************************************************
*
* Ethernet Initialization Routine
*
*************************************************************/
static int bfin_EMAC_init(struct eth_device *dev, bd_t * bd)
{
u32 opmode;
int dat;
int i;
DEBUGF("Eth_init: ......\n");
txIdx = 0;
rxIdx = 0;
/* Initialize System Register */
if (SetupSystemRegs(&dat) < 0)
return -1;
/* Initialize EMAC address */
SetupMacAddr(SrcAddr);
/* Initialize TX and RX buffer */
for (i = 0; i < PKTBUFSRX; i++) {
rxbuf[i] = SetupRxBuffer(i);
if (i > 0) {
rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
&(rxbuf[i]->Dma[0]);
if (i == (PKTBUFSRX - 1))
rxbuf[i]->Dma[1].NEXT_DESC_PTR =
&(rxbuf[0]->Dma[0]);
}
}
for (i = 0; i < TX_BUF_CNT; i++) {
txbuf[i] = SetupTxBuffer(i);
if (i > 0) {
txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
&(txbuf[i]->Dma[0]);
if (i == (TX_BUF_CNT - 1))
txbuf[i]->Dma[1].NEXT_DESC_PTR =
&(txbuf[0]->Dma[0]);
}
}
/* Set RX DMA */
*pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
*pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
/* Wait MII done */
PollMdcDone();
/* We enable only RX here */
/* ASTP : Enable Automatic Pad Stripping
PR : Promiscuous Mode for test
PSF : Receive frames with total length less than 64 bytes.
FDMODE : Full Duplex Mode
LB : Internal Loopback for test
RE : Receiver Enable */
if (dat == FDMODE)
opmode = ASTP | FDMODE | PSF;
else
opmode = ASTP | PSF;
opmode |= RE;
#ifdef CONFIG_BFIN_MAC_RMII
opmode |= TE | RMII;
#endif
/* Turn on the EMAC */
*pEMAC_OPMODE = opmode;
return 0;
}
static void bfin_EMAC_halt(struct eth_device *dev)
{
DEBUGF("Eth_halt: ......\n");
/* Turn off the EMAC */
*pEMAC_OPMODE = 0x00000000;
/* Turn off the EMAC RX DMA */
*pDMA1_CONFIG = 0x0000;
*pDMA2_CONFIG = 0x0000;
}
void SetupMacAddr(u8 * MACaddr)
{
char *tmp, *end;
int i;
/* this depends on a little-endian machine */
tmp = getenv("ethaddr");
if (tmp) {
for (i = 0; i < 6; i++) {
MACaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
if (tmp)
tmp = (*end) ? end + 1 : end;
}
#ifndef CONFIG_NETCONSOLE
printf("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n",
MACaddr[0], MACaddr[1],
MACaddr[2], MACaddr[3], MACaddr[4], MACaddr[5]);
#endif
*pEMAC_ADDRLO = MACaddr[0] | MACaddr[1] << 8 |
MACaddr[2] << 16 | MACaddr[3] << 24;
*pEMAC_ADDRHI = MACaddr[4] | MACaddr[5] << 8;
}
}
void PollMdcDone(void)
{
/* poll the STABUSY bit */
while (*pEMAC_STAADD & STABUSY) ;
}
void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data)
{
PollMdcDone();
*pEMAC_STADAT = Data;
*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
STAOP | STAIE | STABUSY;
}
/*********************************************************************************
* Read an off-chip register in a PHY through the MDC/MDIO port *
*********************************************************************************/
u16 RdPHYReg(u16 PHYAddr, u16 RegAddr)
{
u16 Data;
PollMdcDone();
*pEMAC_STAADD = SET_PHYAD(PHYAddr) | SET_REGAD(RegAddr) |
STAIE | STABUSY;
PollMdcDone();
Data = (u16) * pEMAC_STADAT;
PHYregs[RegAddr] = Data; /* save shadow copy */
return Data;
}
void SoftResetPHY(void)
{
u16 phydat;
/* set the reset bit */
WrPHYReg(PHYADDR, PHY_MODECTL, PHY_RESET);
/* and clear it again */
WrPHYReg(PHYADDR, PHY_MODECTL, 0x0000);
do {
/* poll until reset is complete */
phydat = RdPHYReg(PHYADDR, PHY_MODECTL);
} while ((phydat & PHY_RESET) != 0);
}
int SetupSystemRegs(int *opmode)
{
u16 sysctl, phydat;
int count = 0;
/* Enable PHY output */
*pVR_CTL |= PHYCLKOE;
/* MDC = 2.5 MHz */
sysctl = SET_MDCDIV(24);
/* Odd word alignment for Receive Frame DMA word */
/* Configure checksum support and rcve frame word alignment */
sysctl |= RXDWA | RXCKS;
*pEMAC_SYSCTL = sysctl;
/* auto negotiation on */
/* full duplex */
/* 100 Mbps */
phydat = PHY_ANEG_EN | PHY_DUPLEX | PHY_SPD_SET;
WrPHYReg(PHYADDR, PHY_MODECTL, phydat);
do {
udelay(1000);
phydat = RdPHYReg(PHYADDR, PHY_MODESTAT);
if (count > 3000) {
printf
("Link is down, please check your network connection\n");
return -1;
}
count++;
} while (!(phydat & 0x0004));
phydat = RdPHYReg(PHYADDR, PHY_ANLPAR);
if ((phydat & 0x0100) || (phydat & 0x0040))
*opmode = FDMODE;
else
*opmode = 0;
*pEMAC_MMC_CTL = RSTC | CROLL;
/* Initialize the TX DMA channel registers */
*pDMA2_X_COUNT = 0;
*pDMA2_X_MODIFY = 4;
*pDMA2_Y_COUNT = 0;
*pDMA2_Y_MODIFY = 0;
/* Initialize the RX DMA channel registers */
*pDMA1_X_COUNT = 0;
*pDMA1_X_MODIFY = 4;
*pDMA1_Y_COUNT = 0;
*pDMA1_Y_MODIFY = 0;
return 0;
}
ADI_ETHER_BUFFER *SetupRxBuffer(int no)
{
ADI_ETHER_FRAME_BUFFER *frmbuf;
ADI_ETHER_BUFFER *buf;
int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
int total_size = nobytes_buffer + RECV_BUFSIZE;
buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
frmbuf =
(ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
nobytes_buffer);
memset(buf, 0x00, nobytes_buffer);
buf->FrmData = frmbuf;
memset(frmbuf, 0xfe, RECV_BUFSIZE);
/* set up first desc to point to receive frame buffer */
buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
buf->Dma[0].START_ADDR = (u32) buf->FrmData;
buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
/* set up second desc to point to status word */
buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
return buf;
}
ADI_ETHER_BUFFER *SetupTxBuffer(int no)
{
ADI_ETHER_FRAME_BUFFER *frmbuf;
ADI_ETHER_BUFFER *buf;
int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
int total_size = nobytes_buffer + RECV_BUFSIZE;
buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
frmbuf =
(ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
nobytes_buffer);
memset(buf, 0x00, nobytes_buffer);
buf->FrmData = frmbuf;
memset(frmbuf, 0x00, RECV_BUFSIZE);
/* set up first desc to point to receive frame buffer */
buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
buf->Dma[0].START_ADDR = (u32) buf->FrmData;
buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
/* set up second desc to point to status word */
buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
return buf;
}
#if defined(CONFIG_POST) && defined(CFG_POST_ETHER)
int ether_post_test(int flags)
{
uchar buf[64];
int i, value = 0;
int length;
printf("\n--------");
bfin_EMAC_init(NULL, NULL);
/* construct the package */
buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
buf[12] = 0x08; /* Type: ARP */
buf[13] = 0x06;
buf[14] = 0x00; /* Hardware type: Ethernet */
buf[15] = 0x01;
buf[16] = 0x08; /* Protocal type: IP */
buf[17] = 0x00;
buf[18] = 0x06; /* Hardware size */
buf[19] = 0x04; /* Protocol size */
buf[20] = 0x00; /* Opcode: request */
buf[21] = 0x01;
for (i = 0; i < 42; i++)
buf[i + 22] = i;
printf("--------Send 64 bytes......\n");
bfin_EMAC_send(NULL, (volatile void *)buf, 64);
for (i = 0; i < 100; i++) {
udelay(10000);
if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
value = 1;
break;
}
}
if (value == 0) {
printf("--------EMAC can't receive any data\n");
eth_halt();
return -1;
}
length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
for (i = 0; i < length; i++) {
if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
printf("--------EMAC receive error data!\n");
eth_halt();
return -1;
}
}
printf("--------receive %d bytes, matched\n", length);
bfin_EMAC_halt(NULL);
return 0;
}
#endif
#endif /* CFG_CMD_NET */

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#define PHYADDR 0x01
#define NO_PHY_REGS 0x20
#define DEFAULT_PHY_PHYID1 0x0007
#define DEFAULT_PHY_PHYID2 0xC0A3
#define PHY_MODECTL 0x00
#define PHY_MODESTAT 0x01
#define PHY_PHYID1 0x02
#define PHY_PHYID2 0x03
#define PHY_ANAR 0x04
#define PHY_ANLPAR 0x05
#define PHY_ANER 0x06
#define PHY_RESET 0x8000
#define PHY_ANEG_EN 0x1000
#define PHY_DUPLEX 0x0100
#define PHY_SPD_SET 0x2000
#define RECV_BUFSIZE (0x614)
typedef volatile u32 reg32;
typedef volatile u16 reg16;
typedef struct ADI_DMA_CONFIG_REG {
u16 b_DMA_EN:1; /* 0 Enabled */
u16 b_WNR:1; /* 1 Direction */
u16 b_WDSIZE:2; /* 2:3 Transfer word size */
u16 b_DMA2D:1; /* 4 DMA mode */
u16 b_RESTART:1; /* 5 Retain FIFO */
u16 b_DI_SEL:1; /* 6 Data interrupt timing select */
u16 b_DI_EN:1; /* 7 Data interrupt enabled */
u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */
u16 b_FLOW:3; /* 12:14Flow */
} ADI_DMA_CONFIG_REG;
typedef struct adi_ether_frame_buffer {
u16 NoBytes; /* the no. of following bytes */
u8 Dest[6]; /* destination MAC address */
u8 Srce[6]; /* source MAC address */
u16 LTfield; /* length/type field */
u8 Data[0]; /* payload bytes */
} ADI_ETHER_FRAME_BUFFER;
/* 16 bytes/struct */
typedef struct dma_descriptor {
struct dma_descriptor *NEXT_DESC_PTR;
u32 START_ADDR;
ADI_DMA_CONFIG_REG CONFIG;
} DMA_DESCRIPTOR;
/* 10 bytes/struct in 12 bytes */
typedef struct adi_ether_buffer {
DMA_DESCRIPTOR Dma[2]; /* first for the frame, second for the status */
ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
struct adi_ether_buffer *pNext; /* next buffer */
struct adi_ether_buffer *pPrev; /* prev buffer */
u16 IPHdrChksum; /* the IP header checksum */
u16 IPPayloadChksum; /* the IP header and payload checksum */
volatile u32 StatusWord; /* the frame status word */
} ADI_ETHER_BUFFER;
/* 40 bytes/struct in 44 bytes */
void SetupMacAddr(u8 * MACaddr);
void PollMdcDone(void);
void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data);
u16 RdPHYReg(u16 PHYAddr, u16 RegAddr);
void SoftResetPHY(void);
void DumpPHYRegs(void);
int SetupSystemRegs(int *opmode);
/**
* is_zero_ether_addr - Determine if give Ethernet address is all zeros.
* @addr: Pointer to a six-byte array containing the Ethernet address
*
* Return true if the address is all zeroes.
*/
static inline int is_zero_ether_addr(const u8 * addr)
{
return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
}
/**
* is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
* @addr: Pointer to a six-byte array containing the Ethernet address
*
* Return true if the address is a multicast address.
* By definition the broadcast address is also a multicast address.
*/
static inline int is_multicast_ether_addr(const u8 * addr)
{
return (0x01 & addr[0]);
}
/**
* is_valid_ether_addr - Determine if the given Ethernet address is valid
* @addr: Pointer to a six-byte array containing the Ethernet address
*
* Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not
* a multicast address, and is not FF:FF:FF:FF:FF:FF.
*
* Return true if the address is valid.
*/
static inline int is_valid_ether_addr(const u8 * addr)
{
/* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to
* explicitly check for it here. */
return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
}

123
board/bf537-stamp/flash-defines.h Normal file
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/*
* U-boot - flash-defines.h
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FLASHDEFINES_H__
#define __FLASHDEFINES_H__
#include <common.h>
#define V_ULONG(a) (*(volatile unsigned long *)( a ))
#define V_BYTE(a) (*(volatile unsigned char *)( a ))
#define TRUE 0x1
#define FALSE 0x0
#define BUFFER_SIZE 0x80000
#define NO_COMMAND 0
#define GET_CODES 1
#define RESET 2
#define WRITE 3
#define FILL 4
#define ERASE_ALL 5
#define ERASE_SECT 6
#define READ 7
#define GET_SECTNUM 8
#define FLASH_START_L 0x0000
#define FLASH_START_H 0x2000
#define FLASH_MAN_ST 2
#define RESET_VAL 0xF0
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
int get_codes(void);
int poll_toggle_bit(long lOffset);
void reset_flash(void);
int erase_flash(void);
int erase_block_flash(int);
void unlock_flash(long lOffset);
int write_data(long lStart, long lCount, uchar * pnData);
int read_flash(long nOffset, int *pnValue);
int write_flash(long nOffset, int nValue);
void get_sector_number(long lOffset, int *pnSector);
int GetSectorProtectionStatus(flash_info_t * info, int nSector);
int GetOffset(int nBlock);
int AFP_NumSectors = 71;
long AFP_SectorSize2 = 0x10000;
int AFP_SectorSize1 = 0x2000;
#define NUM_SECTORS 71
#define WRITESEQ1 0x0AAA
#define WRITESEQ2 0x0554
#define WRITESEQ3 0x0AAA
#define WRITESEQ4 0x0AAA
#define WRITESEQ5 0x0554
#define WRITESEQ6 0x0AAA
#define WRITEDATA1 0xaa
#define WRITEDATA2 0x55
#define WRITEDATA3 0x80
#define WRITEDATA4 0xaa
#define WRITEDATA5 0x55
#define WRITEDATA6 0x10
#define PriFlashABegin 0
#define SecFlashABegin 8
#define SecFlashBBegin 36
#define PriFlashAOff 0x0
#define PriFlashBOff 0x100000
#define SecFlashAOff 0x10000
#define SecFlashBOff 0x280000
#define INVALIDLOCNSTART 0x20270000
#define INVALIDLOCNEND 0x20280000
#define BlockEraseVal 0x30
#define UNLOCKDATA1 0xaa
#define UNLOCKDATA2 0x55
#define UNLOCKDATA3 0xa0
#define GETCODEDATA1 0xaa
#define GETCODEDATA2 0x55
#define GETCODEDATA3 0x90
#define SecFlashASec1Off 0x200000
#define SecFlashASec2Off 0x204000
#define SecFlashASec3Off 0x206000
#define SecFlashASec4Off 0x208000
#define SecFlashAEndOff 0x210000
#define SecFlashBSec1Off 0x280000
#define SecFlashBSec2Off 0x284000
#define SecFlashBSec3Off 0x286000
#define SecFlashBSec4Off 0x288000
#define SecFlashBEndOff 0x290000
#define SECT32 32
#define SECT33 33
#define SECT34 34
#define SECT35 35
#define SECT36 36
#define SECT37 37
#define SECT38 38
#define SECT39 39
#define FLASH_SUCCESS 0
#define FLASH_FAIL -1
#endif

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/*
* U-boot - flash.c Flash driver for PSD4256GV
*
* Copyright (c) 2005 blackfin.uclinux.org
* This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <malloc.h>
#include <config.h>
#include <asm/io.h>
#include "flash-defines.h"
void flash_reset(void)
{
reset_flash();
}
unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
{
int id = 0, i = 0;
static int FlagDev = 1;
id = get_codes();
if (FlagDev) {
FlagDev = 0;
}
info->flash_id = id;
switch (bank_flag) {
case 0:
for (i = PriFlashABegin; i < SecFlashABegin; i++)
info->start[i] = (baseaddr + (i * AFP_SectorSize1));
for (i = SecFlashABegin; i < NUM_SECTORS; i++)
info->start[i] =
(baseaddr + SecFlashAOff +
((i - SecFlashABegin) * AFP_SectorSize2));
info->size = 0x400000;
info->sector_count = NUM_SECTORS;
break;
case 1:
info->start[0] = baseaddr + SecFlashASec1Off;
info->start[1] = baseaddr + SecFlashASec2Off;
info->start[2] = baseaddr + SecFlashASec3Off;
info->start[3] = baseaddr + SecFlashASec4Off;
info->size = 0x10000;
info->sector_count = 4;
break;
case 2:
info->start[0] = baseaddr + SecFlashBSec1Off;
info->start[1] = baseaddr + SecFlashBSec2Off;
info->start[2] = baseaddr + SecFlashBSec3Off;
info->start[3] = baseaddr + SecFlashBSec4Off;
info->size = 0x10000;
info->sector_count = 4;
break;
}
return (info->size);
}
unsigned long flash_init(void)
{
unsigned long size_b;
int i;
size_b = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
size_b = flash_get_size(CFG_FLASH_BASE, &flash_info[0], 0);
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b == 0) {
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b, size_b >> 20);
}
/* flash_protect (int flag, ulong from, ulong to, flash_info_t *info) */
(void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,
(flash_info[0].start[2] - 1), &flash_info[0]);
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
(void)flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF,
&flash_info[0]);
#endif
return (size_b);
}
void flash_print_info(flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id) {
case (STM_ID_29W320EB & 0xFFFF):
case (STM_ID_29W320DB & 0xFFFF):
printf("ST Microelectronics ");
break;
default:
printf("Unknown Vendor: (0x%08X) ", info->flash_id);
break;
}
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s",
info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf("\n");
return;
}
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
int cnt = 0, i;
int prot, sect;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect])
prot++;
}
if (prot)
printf("- Warning: %d protected sectors will not be erased!\n",
prot);
else
printf("\n");
cnt = s_last - s_first + 1;
#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT)
printf("Erasing Flash locations, Please Wait\n");
for (i = s_first; i <= s_last; i++) {
if (info->protect[i] == 0) { /* not protected */
if (erase_block_flash(i) < 0) {
printf("Error Sector erasing \n");
return FLASH_FAIL;
}
}
}
#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
if (cnt == FLASH_TOT_SECT) {
printf("Erasing flash, Please Wait \n");
if (erase_flash() < 0) {
printf("Erasing flash failed \n");
return FLASH_FAIL;
}
} else {
printf("Erasing Flash locations, Please Wait\n");
for (i = s_first; i <= s_last; i++) {
if (info->protect[i] == 0) { /* not protected */
if (erase_block_flash(i) < 0) {
printf("Error Sector erasing \n");
return FLASH_FAIL;
}
}
}
}
#endif
printf("\n");
return FLASH_SUCCESS;
}
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int d;
if (addr % 2) {
read_flash(addr - 1 - CFG_FLASH_BASE, &d);
d = (int)((d & 0x00FF) | (*src++ << 8));
write_data(addr - 1, 2, (uchar *) & d);
write_data(addr + 1, cnt - 1, src);
} else
write_data(addr, cnt, src);
return FLASH_SUCCESS;
}
int write_data(long lStart, long lCount, uchar * pnData)
{
long i = 0;
unsigned long ulOffset = lStart - CFG_FLASH_BASE;
int d;
int nSector = 0;
int flag = 0;
if (lCount % 2) {
flag = 1;
lCount = lCount - 1;
}
for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset, &d);
if (d != 0xffff) {
printf
("Flash not erased at offset 0x%x Please erase to reprogram \n",
ulOffset);
return FLASH_FAIL;
}
unlock_flash(ulOffset);
d = (int)(pnData[i] | pnData[i + 1] << 8);
write_flash(ulOffset, d);
if (poll_toggle_bit(ulOffset) < 0) {
printf("Error programming the flash \n");
return FLASH_FAIL;
}
if ((i > 0) && (!(i % AFP_SectorSize2)))
printf(".");
}
if (flag) {
get_sector_number(ulOffset, &nSector);
read_flash(ulOffset, &d);
if (d != 0xffff) {
printf
("Flash not erased at offset 0x%x Please erase to reprogram \n",
ulOffset);
return FLASH_FAIL;
}
unlock_flash(ulOffset);
d = (int)(pnData[i] | (d & 0xFF00));
write_flash(ulOffset, d);
if (poll_toggle_bit(ulOffset) < 0) {
printf("Error programming the flash \n");
return FLASH_FAIL;
}
}
return FLASH_SUCCESS;
}
int write_flash(long nOffset, int nValue)
{
long addr;
addr = (CFG_FLASH_BASE + nOffset);
*(unsigned volatile short *)addr = nValue;
sync();
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
if (icache_status())
udelay(CONFIG_CCLK_HZ / 1000000);
#endif
return FLASH_SUCCESS;
}
int read_flash(long nOffset, int *pnValue)
{
unsigned short *pFlashAddr =
(unsigned short *)(CFG_FLASH_BASE + nOffset);
*pnValue = *pFlashAddr;
return TRUE;
}
int poll_toggle_bit(long lOffset)
{
unsigned int u1, u2;
volatile unsigned long *FB =
(volatile unsigned long *)(CFG_FLASH_BASE + lOffset);
while (1) {
u1 = *(volatile unsigned short *)FB;
u2 = *(volatile unsigned short *)FB;
u1 ^= u2;
if (!(u1 & 0x0040))
break;
if (!(u2 & 0x0020))
continue;
else {
u1 = *(volatile unsigned short *)FB;
u2 = *(volatile unsigned short *)FB;
u1 ^= u2;
if (!(u1 & 0x0040))
break;
else {
reset_flash();
return FLASH_FAIL;
}
}
}
return FLASH_SUCCESS;
}
void reset_flash(void)
{
write_flash(WRITESEQ1, RESET_VAL);
/* Wait for 10 micro seconds */
udelay(10);
}
int erase_flash(void)
{
write_flash(WRITESEQ1, WRITEDATA1);
write_flash(WRITESEQ2, WRITEDATA2);
write_flash(WRITESEQ3, WRITEDATA3);
write_flash(WRITESEQ4, WRITEDATA4);
write_flash(WRITESEQ5, WRITEDATA5);
write_flash(WRITESEQ6, WRITEDATA6);
if (poll_toggle_bit(0x0000) < 0)
return FLASH_FAIL;
return FLASH_SUCCESS;
}
int erase_block_flash(int nBlock)
{
long ulSectorOff = 0x0;
if ((nBlock < 0) || (nBlock > AFP_NumSectors))
return FALSE;
/* figure out the offset of the block in flash */
if ((nBlock >= 0) && (nBlock < SecFlashABegin))
ulSectorOff = nBlock * AFP_SectorSize1;
else if ((nBlock >= SecFlashABegin) && (nBlock < NUM_SECTORS))
ulSectorOff =
SecFlashAOff + (nBlock - SecFlashABegin) * AFP_SectorSize2;
/* no such sector */
else
return FLASH_FAIL;
write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
write_flash(ulSectorOff, BlockEraseVal);
if (poll_toggle_bit(ulSectorOff) < 0)
return FLASH_FAIL;
printf(".");
return FLASH_SUCCESS;
}
void unlock_flash(long ulOffset)
{
unsigned long ulOffsetAddr = ulOffset;
ulOffsetAddr &= 0xFFFF0000;
write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
}
int get_codes()
{
int dev_id = 0;
write_flash(WRITESEQ1, GETCODEDATA1);
write_flash(WRITESEQ2, GETCODEDATA2);
write_flash(WRITESEQ3, GETCODEDATA3);
read_flash(0x0402, &dev_id);
dev_id &= 0x0000FFFF;
reset_flash();
return dev_id;
}
void get_sector_number(long ulOffset, int *pnSector)
{
int nSector = 0;
long lMainEnd = 0x400000;
long lBootEnd = 0x10000;
/* sector numbers for the FLASH A boot sectors */
if (ulOffset < lBootEnd) {
nSector = (int)ulOffset / AFP_SectorSize1;
}
/* sector numbers for the FLASH B boot sectors */
else if ((ulOffset >= lBootEnd) && (ulOffset < lMainEnd)) {
nSector = ((ulOffset / (AFP_SectorSize2)) + 7);
}
/* if it is a valid sector, set it */
if ((nSector >= 0) && (nSector < AFP_NumSectors))
*pnSector = nSector;
}

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board/bf537-stamp/nand.c Normal file
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/*
* (C) Copyright 2006 Aubrey.Li, aubrey.li@analog.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <nand.h>
#define CONCAT(a,b,c,d) a ## b ## c ## d
#define PORT(a,b) CONCAT(pPORT,a,b,)
#ifndef CONFIG_NAND_GPIO_PORT
#define CONFIG_NAND_GPIO_PORT F
#endif
/*
* hardware specific access to control-lines
*/
static void bfin_hwcontrol(struct mtd_info *mtd, int cmd)
{
register struct nand_chip *this = mtd->priv;
switch (cmd) {
case NAND_CTL_SETCLE:
this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
break;
case NAND_CTL_CLRCLE:
this->IO_ADDR_W = CFG_NAND_BASE;
break;
case NAND_CTL_SETALE:
this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
break;
case NAND_CTL_CLRALE:
this->IO_ADDR_W = CFG_NAND_BASE;
break;
case NAND_CTL_SETNCE:
case NAND_CTL_CLRNCE:
break;
}
this->IO_ADDR_R = this->IO_ADDR_W;
/* Drain the writebuffer */
sync();
}
int bfin_device_ready(struct mtd_info *mtd)
{
int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0;
sync();
return ret;
}
/*
* Board-specific NAND initialization. The following members of the
* argument are board-specific (per include/linux/mtd/nand.h):
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
* - hwcontrol: hardwarespecific function for accesing control-lines
* - dev_ready: hardwarespecific function for accesing device ready/busy line
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
* only be provided if a hardware ECC is available
* - eccmode: mode of ecc, see defines
* - chip_delay: chip dependent delay for transfering data from array to
* read regs (tR)
* - options: various chip options. They can partly be set to inform
* nand_scan about special functionality. See the defines for further
* explanation
* Members with a "?" were not set in the merged testing-NAND branch,
* so they are not set here either.
*/
void board_nand_init(struct nand_chip *nand)
{
*PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY;
*PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
*PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
nand->hwcontrol = bfin_hwcontrol;
nand->eccmode = NAND_ECC_SOFT;
nand->dev_ready = bfin_device_ready;
nand->chip_delay = 30;
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */

322
board/bf537-stamp/post-memory.c Normal file
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#include <common.h>
#include <asm/io.h>
#ifdef CONFIG_POST
#include <post.h>
#include <watchdog.h>
#if CONFIG_POST & CFG_POST_MEMORY
#define CLKIN 25000000
#define PATTERN1 0x5A5A5A5A
#define PATTERN2 0xAAAAAAAA
#define CCLK_NUM 4
#define SCLK_NUM 3
void post_out_buff(char *buff);
int post_key_pressed(void);
void post_init_pll(int mult, int div);
int post_init_sdram(int sclk);
void post_init_uart(int sclk);
const int pll[CCLK_NUM][SCLK_NUM][2] = {
{{20, 4}, {20, 5}, {20, 10}}, /* CCLK = 500M */
{{16, 4}, {16, 5}, {16, 8}}, /* CCLK = 400M */
{{8, 2}, {8, 4}, {8, 5}}, /* CCLK = 200M */
{{4, 1}, {4, 2}, {4, 4}} /* CCLK = 100M */
};
const char *const log[CCLK_NUM][SCLK_NUM] = {
{"CCLK-500Mhz SCLK-125Mhz: Writing...\0",
"CCLK-500Mhz SCLK-100Mhz: Writing...\0",
"CCLK-500Mhz SCLK- 50Mhz: Writing...\0",},
{"CCLK-400Mhz SCLK-100Mhz: Writing...\0",
"CCLK-400Mhz SCLK- 80Mhz: Writing...\0",
"CCLK-400Mhz SCLK- 50Mhz: Writing...\0",},
{"CCLK-200Mhz SCLK-100Mhz: Writing...\0",
"CCLK-200Mhz SCLK- 50Mhz: Writing...\0",
"CCLK-200Mhz SCLK- 40Mhz: Writing...\0",},
{"CCLK-100Mhz SCLK-100Mhz: Writing...\0",
"CCLK-100Mhz SCLK- 50Mhz: Writing...\0",
"CCLK-100Mhz SCLK- 25Mhz: Writing...\0",},
};
int memory_post_test(int flags)
{
int addr;
int m, n;
int sclk, sclk_temp;
int ret = 1;
sclk_temp = CLKIN / 1000000;
sclk_temp = sclk_temp * CONFIG_VCO_MULT;
for (sclk = 0; sclk_temp > 0; sclk++)
sclk_temp -= CONFIG_SCLK_DIV;
sclk = sclk * 1000000;
post_init_uart(sclk);
if (post_key_pressed() == 0)
return 0;
for (m = 0; m < CCLK_NUM; m++) {
for (n = 0; n < SCLK_NUM; n++) {
/* Calculate the sclk */
sclk_temp = CLKIN / 1000000;
sclk_temp = sclk_temp * pll[m][n][0];
for (sclk = 0; sclk_temp > 0; sclk++)
sclk_temp -= pll[m][n][1];
sclk = sclk * 1000000;
post_init_pll(pll[m][n][0], pll[m][n][1]);
post_init_sdram(sclk);
post_init_uart(sclk);
post_out_buff("\n\r\0");
post_out_buff(log[m][n]);
for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4)
*(unsigned long *)addr = PATTERN1;
post_out_buff("Reading...\0");
for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4) {
if ((*(unsigned long *)addr) != PATTERN1) {
post_out_buff("Error\n\r\0");
ret = 0;
}
}
post_out_buff("OK\n\r\0");
}
}
if (ret)
post_out_buff("memory POST passed\n\r\0");
else
post_out_buff("memory POST failed\n\r\0");
post_out_buff("\n\r\n\r\0");
return 1;
}
void post_init_uart(int sclk)
{
int divisor;
for (divisor = 0; sclk > 0; divisor++)
sclk -= 57600 * 16;
*pPORTF_FER = 0x000F;
*pPORTH_FER = 0xFFFF;
*pUART_GCTL = 0x00;
*pUART_LCR = 0x83;
sync();
*pUART_DLL = (divisor & 0xFF);
sync();
*pUART_DLH = ((divisor >> 8) & 0xFF);
sync();
*pUART_LCR = 0x03;
sync();
*pUART_GCTL = 0x01;
sync();
}
void post_out_buff(char *buff)
{
int i = 0;
for (i = 0; i < 0x80000; i++) ;
i = 0;
while ((buff[i] != '\0') && (i != 100)) {
while (!(*pUART_LSR & 0x20)) ;
*pUART_THR = buff[i];
sync();
i++;
}
for (i = 0; i < 0x80000; i++) ;
}
/* Using sw10-PF5 as the hotkey */
#define KEY_LOOP 0x80000
#define KEY_DELAY 0x80
int post_key_pressed(void)
{
int i, n;
unsigned short value;
*pPORTF_FER &= ~PF5;
*pPORTFIO_DIR &= ~PF5;
*pPORTFIO_INEN |= PF5;
sync();
post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
for (i = 0; i < KEY_LOOP; i++) {
value = *pPORTFIO & PF5;
if (*pUART0_RBR == 0x0D) {
value = 0;
goto key_pressed;
}
if (value != 0) {
goto key_pressed;
}
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
post_out_buff("\b2\0");
for (i = 0; i < KEY_LOOP; i++) {
value = *pPORTFIO & PF5;
if (*pUART0_RBR == 0x0D) {
value = 0;
goto key_pressed;
}
if (value != 0) {
goto key_pressed;
}
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
post_out_buff("\b1\0");
for (i = 0; i < KEY_LOOP; i++) {
value = *pPORTFIO & PF5;
if (*pUART0_RBR == 0x0D) {
value = 0;
goto key_pressed;
}
if (value != 0) {
goto key_pressed;
}
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
key_pressed:
post_out_buff("\b0");
post_out_buff("\n\r\0");
if (value == 0)
return 0;
post_out_buff("Hotkey has been pressed, Enter POST . . . . . .\n\r\0");
return 1;
}
void post_init_pll(int mult, int div)
{
*pSIC_IWR = 0x01;
*pPLL_CTL = (mult << 9);
*pPLL_DIV = div;
asm("CLI R2;");
asm("IDLE;");
asm("STI R2;");
while (!(*pPLL_STAT & 0x20)) ;
}
int post_init_sdram(int sclk)
{
int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num, SDRAM_tRCD,
SDRAM_tWR;
int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE, SDRAM_WIDTH,
mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
if ((sclk > 119402985)) {
SDRAM_tRP = TRP_2;
SDRAM_tRP_num = 2;
SDRAM_tRAS = TRAS_7;
SDRAM_tRAS_num = 7;
SDRAM_tRCD = TRCD_2;
SDRAM_tWR = TWR_2;
} else if ((sclk > 104477612) && (sclk <= 119402985)) {
SDRAM_tRP = TRP_2;
SDRAM_tRP_num = 2;
SDRAM_tRAS = TRAS_6;
SDRAM_tRAS_num = 6;
SDRAM_tRCD = TRCD_2;
SDRAM_tWR = TWR_2;
} else if ((sclk > 89552239) && (sclk <= 104477612)) {
SDRAM_tRP = TRP_2;
SDRAM_tRP_num = 2;
SDRAM_tRAS = TRAS_5;
SDRAM_tRAS_num = 5;
SDRAM_tRCD = TRCD_2;
SDRAM_tWR = TWR_2;
} else if ((sclk > 74626866) && (sclk <= 89552239)) {
SDRAM_tRP = TRP_2;
SDRAM_tRP_num = 2;
SDRAM_tRAS = TRAS_4;
SDRAM_tRAS_num = 4;
SDRAM_tRCD = TRCD_2;
SDRAM_tWR = TWR_2;
} else if ((sclk > 66666667) && (sclk <= 74626866)) {
SDRAM_tRP = TRP_2;
SDRAM_tRP_num = 2;
SDRAM_tRAS = TRAS_3;
SDRAM_tRAS_num = 3;
SDRAM_tRCD = TRCD_2;
SDRAM_tWR = TWR_2;
} else if ((sclk > 59701493) && (sclk <= 66666667)) {
SDRAM_tRP = TRP_1;
SDRAM_tRP_num = 1;
SDRAM_tRAS = TRAS_4;
SDRAM_tRAS_num = 4;
SDRAM_tRCD = TRCD_1;
SDRAM_tWR = TWR_2;
} else if ((sclk > 44776119) && (sclk <= 59701493)) {
SDRAM_tRP = TRP_1;
SDRAM_tRP_num = 1;
SDRAM_tRAS = TRAS_3;
SDRAM_tRAS_num = 3;
SDRAM_tRCD = TRCD_1;
SDRAM_tWR = TWR_2;
} else if ((sclk > 29850746) && (sclk <= 44776119)) {
SDRAM_tRP = TRP_1;
SDRAM_tRP_num = 1;
SDRAM_tRAS = TRAS_2;
SDRAM_tRAS_num = 2;
SDRAM_tRCD = TRCD_1;
SDRAM_tWR = TWR_2;
} else if (sclk <= 29850746) {
SDRAM_tRP = TRP_1;
SDRAM_tRP_num = 1;
SDRAM_tRAS = TRAS_1;
SDRAM_tRAS_num = 1;
SDRAM_tRCD = TRCD_1;
SDRAM_tWR = TWR_2;
} else {
SDRAM_tRP = TRP_1;
SDRAM_tRP_num = 1;
SDRAM_tRAS = TRAS_1;
SDRAM_tRAS_num = 1;
SDRAM_tRCD = TRCD_1;
SDRAM_tWR = TWR_2;
}
/*SDRAM INFORMATION: */
SDRAM_Tref = 64; /* Refresh period in milliseconds */
SDRAM_NRA = 4096; /* Number of row addresses in SDRAM */
SDRAM_CL = CL_3; /* 2 */
SDRAM_SIZE = EBSZ_64;
SDRAM_WIDTH = EBCAW_10;
mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
/* Equation from section 17 (p17-46) of BF533 HRM */
mem_SDRRC =
(((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) -
(SDRAM_tRAS_num + SDRAM_tRP_num);
/* Enable SCLK Out */
mem_SDGCTL =
(SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
| PSS);
sync();
*pEBIU_SDGCTL |= 0x1000000;
/* Set the SDRAM Refresh Rate control register based on SSCLK value */
*pEBIU_SDRRC = mem_SDRRC;
/* SDRAM Memory Bank Control Register */
*pEBIU_SDBCTL = mem_SDBCTL;
/* SDRAM Memory Global Control Register */
*pEBIU_SDGCTL = mem_SDGCTL;
sync();
return mem_SDRRC;
}
#endif /* CONFIG_POST & CFG_POST_MEMORY */
#endif /* CONFIG_POST */

515
board/bf537-stamp/stm_m25p64.c Normal file
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@ -0,0 +1,515 @@
/****************************************************************************
* SPI flash driver for M25P64
****************************************************************************/
#include <common.h>
#include <linux/ctype.h>
#include <asm/io.h>
#if defined(CONFIG_SPI)
/* Application definitions */
#define NUM_SECTORS 128 /* number of sectors */
#define SECTOR_SIZE 0x10000
#define NOP_NUM 1000
#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) /* Settings to the SPI_CTL */
#define TIMOD01 (0x01) /* stes the SPI to work with core instructions */
/* Flash commands */
#define SPI_WREN (0x06) /*Set Write Enable Latch */
#define SPI_WRDI (0x04) /*Reset Write Enable Latch */
#define SPI_RDSR (0x05) /*Read Status Register */
#define SPI_WRSR (0x01) /*Write Status Register */
#define SPI_READ (0x03) /*Read data from memory */
#define SPI_FAST_READ (0x0B) /*Read data from memory */
#define SPI_PP (0x02) /*Program Data into memory */
#define SPI_SE (0xD8) /*Erase one sector in memory */
#define SPI_BE (0xC7) /*Erase all memory */
#define WIP (0x1) /*Check the write in progress bit of the SPI status register */
#define WEL (0x2) /*Check the write enable bit of the SPI status register */
#define TIMEOUT 350000000
typedef enum {
NO_ERR,
POLL_TIMEOUT,
INVALID_SECTOR,
INVALID_BLOCK,
} ERROR_CODE;
void spi_init_f(void);
void spi_init_r(void);
ssize_t spi_read(uchar *, int, uchar *, int);
ssize_t spi_write(uchar *, int, uchar *, int);
char ReadStatusRegister(void);
void Wait_For_SPIF(void);
void SetupSPI(const int spi_setting);
void SPI_OFF(void);
void SendSingleCommand(const int iCommand);
ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector);
ERROR_CODE EraseBlock(int nBlock);
ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData);
ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData);
ERROR_CODE Wait_For_Status(char Statusbit);
ERROR_CODE Wait_For_WEL(void);
/*
* Function: spi_init_f
* Description: Init SPI-Controller (ROM part)
* return: ---
*/
void spi_init_f(void)
{
}
/*
* Function: spi_init_r
* Description: Init SPI-Controller (RAM part) -
* The malloc engine is ready and we can move our buffers to
* normal RAM
* return: ---
*/
void spi_init_r(void)
{
return;
}
/*
* Function: spi_write
*/
ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len)
{
unsigned long offset;
int start_block, end_block;
int start_byte, end_byte;
ERROR_CODE result = NO_ERR;
uchar temp[SECTOR_SIZE];
int i, num;
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
/* Get the start block number */
result = GetSectorNumber(offset, &start_block);
if (result == INVALID_SECTOR) {
printf("Invalid sector! ");
return 0;
}
/* Get the end block number */
result = GetSectorNumber(offset + len - 1, &end_block);
if (result == INVALID_SECTOR) {
printf("Invalid sector! ");
return 0;
}
for (num = start_block; num <= end_block; num++) {
ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
start_byte = num * SECTOR_SIZE;
end_byte = (num + 1) * SECTOR_SIZE - 1;
if (start_byte < offset)
start_byte = offset;
if (end_byte > (offset + len))
end_byte = (offset + len - 1);
for (i = start_byte; i <= end_byte; i++)
temp[i - num * SECTOR_SIZE] = buffer[i - offset];
EraseBlock(num);
result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
if (result != NO_ERR)
return 0;
printf(".");
}
return len;
}
/*
* Function: spi_read
*/
ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len)
{
unsigned long offset;
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
ReadData(offset, len, (int *)buffer);
return len;
}
void SendSingleCommand(const int iCommand)
{
unsigned short dummy;
/* turns on the SPI in single write mode */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
/* sends the actual command to the SPI TX register */
*pSPI_TDBR = iCommand;
sync();
/* The SPI status register will be polled to check the SPIF bit */
Wait_For_SPIF();
dummy = *pSPI_RDBR;
/* The SPI will be turned off */
SPI_OFF();
}
void SetupSPI(const int spi_setting)
{
if (icache_status() || dcache_status())
udelay(CONFIG_CCLK_HZ / 50000000);
/*sets up the PF10 to be the slave select of the SPI */
*pPORTF_FER |= (PF10 | PF11 | PF12 | PF13);
*pSPI_FLG = 0xFF02;
*pSPI_BAUD = CONFIG_SPI_BAUD;
*pSPI_CTL = spi_setting;
sync();
*pSPI_FLG = 0xFD02;
sync();
}
void SPI_OFF(void)
{
*pSPI_CTL = 0x0400; /* disable SPI */
*pSPI_FLG = 0;
*pSPI_BAUD = 0;
sync();
udelay(CONFIG_CCLK_HZ / 50000000);
}
void Wait_For_SPIF(void)
{
unsigned short dummyread;
while ((*pSPI_STAT & TXS)) ;
while (!(*pSPI_STAT & SPIF)) ;
while (!(*pSPI_STAT & RXS)) ;
/* Read dummy to empty the receive register */
dummyread = *pSPI_RDBR;
}
ERROR_CODE Wait_For_WEL(void)
{
int i;
char status_register = 0;
ERROR_CODE ErrorCode = NO_ERR;
for (i = 0; i < TIMEOUT; i++) {
status_register = ReadStatusRegister();
if ((status_register & WEL)) {
ErrorCode = NO_ERR;
break;
}
ErrorCode = POLL_TIMEOUT; /* Time out error */
};
return ErrorCode;
}
ERROR_CODE Wait_For_Status(char Statusbit)
{
int i;
char status_register = 0xFF;
ERROR_CODE ErrorCode = NO_ERR;
for (i = 0; i < TIMEOUT; i++) {
status_register = ReadStatusRegister();
if (!(status_register & Statusbit)) {
ErrorCode = NO_ERR;
break;
}
ErrorCode = POLL_TIMEOUT; /* Time out error */
};
return ErrorCode;
}
char ReadStatusRegister(void)
{
char status_register = 0;
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */
*pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
sync();
Wait_For_SPIF(); /*wait until the instruction has been sent */
*pSPI_TDBR = 0; /*send dummy to receive the status register */
sync();
Wait_For_SPIF(); /*wait until the data has been sent */
status_register = *pSPI_RDBR; /*read the status register */
SPI_OFF(); /* Turn off the SPI */
return status_register;
}
ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector)
{
int nSector = 0;
ERROR_CODE ErrorCode = NO_ERR;
if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) {
ErrorCode = INVALID_SECTOR;
return ErrorCode;
}
nSector = (int)ulOffset / 0x10000;
*pnSector = nSector;
return ErrorCode;
}
ERROR_CODE EraseBlock(int nBlock)
{
unsigned long ulSectorOff = 0x0, ShiftValue;
ERROR_CODE ErrorCode = NO_ERR;
/* if the block is invalid just return */
if ((nBlock < 0) || (nBlock > NUM_SECTORS)) {
ErrorCode = INVALID_BLOCK;
return ErrorCode;
}
/* figure out the offset of the block in flash */
if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) {
ulSectorOff = (nBlock * SECTOR_SIZE);
} else {
ErrorCode = INVALID_BLOCK;
return ErrorCode;
}
/* A write enable instruction must previously have been executed */
SendSingleCommand(SPI_WREN);
/* The status register will be polled to check the write enable latch "WREN" */
ErrorCode = Wait_For_WEL();
if (POLL_TIMEOUT == ErrorCode) {
printf("SPI Erase block error\n");
return ErrorCode;
} else
/* Turn on the SPI to send single commands */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
/*
* Send the erase block command to the flash followed by the 24 address
* to point to the start of a sector
*/
*pSPI_TDBR = SPI_SE;
sync();
Wait_For_SPIF();
/* Send the highest byte of the 24 bit address at first */
ShiftValue = (ulSectorOff >> 16);
*pSPI_TDBR = ShiftValue;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the middle byte of the 24 bit address at second */
ShiftValue = (ulSectorOff >> 8);
*pSPI_TDBR = ShiftValue;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the lowest byte of the 24 bit address finally */
*pSPI_TDBR = ulSectorOff;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Turns off the SPI */
SPI_OFF();
/* Poll the status register to check the Write in Progress bit */
/* Sector erase takes time */
ErrorCode = Wait_For_Status(WIP);
/* block erase should be complete */
return ErrorCode;
}
/*
* ERROR_CODE ReadData()
* Read a value from flash for verify purpose
* Inputs: unsigned long ulStart - holds the SPI start address
* int pnData - pointer to store value read from flash
* long lCount - number of elements to read
*/
ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
{
unsigned long ShiftValue;
char *cnData;
int i;
/* Pointer cast to be able to increment byte wise */
cnData = (char *)pnData;
/* Start SPI interface */
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
#ifdef CONFIG_SPI_FLASH_FAST_READ
/* Send the read command to SPI device */
*pSPI_TDBR = SPI_FAST_READ;
#else
/* Send the read command to SPI device */
*pSPI_TDBR = SPI_READ;
#endif
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the highest byte of the 24 bit address at first */
ShiftValue = (ulStart >> 16);
/* Send the byte to the SPI device */
*pSPI_TDBR = ShiftValue;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the middle byte of the 24 bit address at second */
ShiftValue = (ulStart >> 8);
/* Send the byte to the SPI device */
*pSPI_TDBR = ShiftValue;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
/* Send the lowest byte of the 24 bit address finally */
*pSPI_TDBR = ulStart;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
#ifdef CONFIG_SPI_FLASH_FAST_READ
/* Send dummy for FAST_READ */
*pSPI_TDBR = 0;
sync();
/* Wait until the instruction has been sent */
Wait_For_SPIF();
#endif
/* After the SPI device address has been placed on the MOSI pin the data can be */
/* received on the MISO pin. */
for (i = 0; i < lCount; i++) {
*pSPI_TDBR = 0;
sync();
while (!(*pSPI_STAT & RXS)) ;
*cnData++ = *pSPI_RDBR;
if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0))
printf(".");
}
/* Turn off the SPI */
SPI_OFF();
return NO_ERR;
}
ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
int *iDataSource, long *lWriteCount)
{
unsigned long ulWAddr;
long lWTransferCount = 0;
int i;
char iData;
char *temp = (char *)iDataSource;
ERROR_CODE ErrorCode = NO_ERR;
/* First, a Write Enable Command must be sent to the SPI. */
SendSingleCommand(SPI_WREN);
/*
* Second, the SPI Status Register will be tested whether the
* Write Enable Bit has been set
*/
ErrorCode = Wait_For_WEL();
if (POLL_TIMEOUT == ErrorCode) {
printf("SPI Write Time Out\n");
return ErrorCode;
} else
/* Third, the 24 bit address will be shifted out
* the SPI MOSI bytewise.
* Turns the SPI on
*/
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
*pSPI_TDBR = SPI_PP;
sync();
/*wait until the instruction has been sent */
Wait_For_SPIF();
ulWAddr = (ulStartAddr >> 16);
*pSPI_TDBR = ulWAddr;
sync();
/*wait until the instruction has been sent */
Wait_For_SPIF();
ulWAddr = (ulStartAddr >> 8);
*pSPI_TDBR = ulWAddr;
sync();
/*wait until the instruction has been sent */
Wait_For_SPIF();
ulWAddr = ulStartAddr;
*pSPI_TDBR = ulWAddr;
sync();
/*wait until the instruction has been sent */
Wait_For_SPIF();
/*
* Fourth, maximum number of 256 bytes will be taken from the Buffer
* and sent to the SPI device.
*/
for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
iData = *temp;
*pSPI_TDBR = iData;
sync();
/*wait until the instruction has been sent */
Wait_For_SPIF();
temp++;
}
/* Turns the SPI off */
SPI_OFF();
/*
* Sixth, the SPI Write in Progress Bit must be toggled to ensure the
* programming is done before start of next transfer
*/
ErrorCode = Wait_For_Status(WIP);
if (POLL_TIMEOUT == ErrorCode) {
printf("SPI Program Time out!\n");
return ErrorCode;
} else
*lWriteCount = lWTransferCount;
return ErrorCode;
}
ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData)
{
unsigned long ulWStart = ulStart;
long lWCount = lCount, lWriteCount;
long *pnWriteCount = &lWriteCount;
ERROR_CODE ErrorCode = NO_ERR;
while (lWCount != 0) {
ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
/*
* After each function call of WriteFlash the counter
* must be adjusted
*/
lWCount -= *pnWriteCount;
/* Also, both address pointers must be recalculated. */
ulWStart += *pnWriteCount;
pnData += *pnWriteCount / 4;
}
/* return the appropriate error code */
return ErrorCode;
}
#endif /* CONFIG_SPI */

190
board/bf537-stamp/u-boot.lds.S Normal file
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@ -0,0 +1,190 @@
/*
* U-boot - u-boot.lds.S
*
* Copyright (c) 2005-2007 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
OUTPUT_ARCH(bfin)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
MEMORY
{
ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000
l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS; /*0x1000;*/
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
. = CFG_MONITOR_BASE;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector before the environment sector. If it throws */
/* an error during compilation remove an object here to get */
/* it linked after the configuration sector. */
cpu/bf537/start.o (.text)
cpu/bf537/start1.o (.text)
cpu/bf537/traps.o (.text)
cpu/bf537/interrupt.o (.text)
cpu/bf537/serial.o (.text)
common/dlmalloc.o (.text)
/* lib_blackfin/bf533_string.o (.text) */
/* lib_generic/vsprintf.o (.text) */
lib_generic/crc32.o (.text)
/* lib_generic/zlib.o (.text) */
/* board/bf537-stamp/bf537-stamp.o (.text) */
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .text)
*(.fixup)
*(.got1)
} > ram
_etext = .;
PROVIDE (etext = .);
.text_l1 :
{
. = ALIGN(4) ;
_text_l1 = .;
PROVIDE (text_l1 = .);
board/bf537-stamp/post-memory.o (.text)
. = ALIGN(4) ;
_etext_l1 = .;
PROVIDE (etext_l1 = .);
} > l1_code AT > ram
.rodata :
{
. = ALIGN(4);
*(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata)
*(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata1)
*(EXCLUDE_FILE (board/bf537-stamp/post-memory.o) .rodata.str1.4)
*(.eh_frame)
. = ALIGN(4);
} > ram
. = ALIGN(4);
_erodata = .;
PROVIDE (erodata = .);
.rodata_l1 :
{
. = ALIGN(4) ;
_rodata_l1 = .;
PROVIDE (rodata_l1 = .);
board/bf537-stamp/post-memory.o (.rodata)
board/bf537-stamp/post-memory.o (.rodata1)
board/bf537-stamp/post-memory.o (.rodata.str1.4)
. = ALIGN(4) ;
_erodata_l1 = .;
PROVIDE(erodata_l1 = .);
} > l1_data AT > ram
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
} > ram
_edata = .;
PROVIDE (edata = .);
___u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) } > ram
___u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
.bss :
{
__bss_start = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
} > ram
_end = . ;
PROVIDE (end = .);
}

18
board/ezkit533/Makefile → board/bf561-ezkit/Makefile
View file

@ -1,7 +1,7 @@
#
# U-boot - Makefile
#
# Copyright (c) 2005 blackfin.uclinux.org
# Copyright (c) 2005-2007 Analog Device Inc.
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -29,14 +29,24 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ezkit533.o
COBJS := $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################

73
board/bf561-ezkit/bf561-ezkit.c Normal file
View file

@ -0,0 +1,73 @@
/*
* U-boot - ezkit561.c
*
* Copyright (c) 2005 Bas Vermeulen <bas@buyways.nl>
* Copyright (c) 2005 blackfin.uclinux.org
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
int checkboard(void)
{
printf("CPU: ADSP BF561\n");
printf("Board: ADI BF561 EZ-Kit Lite board\n");
printf(" Support: http://blackfin.uclinux.org/\n");
return 0;
}
long int initdram(int board_type)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef DEBUG
int brate;
char *tmp = getenv("baudrate");
brate = simple_strtoul(tmp, NULL, 16);
printf("Serial Port initialized with Baud rate = %x\n", brate);
printf("SDRAM attributes:\n");
printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
"tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
3, 3, 6, 2, 3);
printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
#endif
gd->bd->bi_memstart = CFG_SDRAM_BASE;
gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
return CFG_MAX_RAM_SIZE;
}
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
int misc_init_r(void)
{
/* Keep PF12 low to be able to drive the USB-LAN Extender */
*pFIO0_DIR = 0x0000;
*pFIO0_FLAG_C = 0x1000; /* Clear PF12 */
sync();
*pFIO0_POLAR = 0x0000;
sync();
return 0;
}
#endif

25
board/bf561-ezkit/config.mk Normal file
View file

@ -0,0 +1,25 @@
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
TEXT_BASE = 0x03FC0000

153
board/bf561-ezkit/u-boot.lds.S Normal file
View file

@ -0,0 +1,153 @@
/*
* U-boot - u-boot.lds.S
*
* Copyright (c) 2005-2007 Analog Device Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
OUTPUT_ARCH(bfin)
OUTPUT_ARCH(bfin)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
. = CFG_MONITOR_BASE;
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector before the environment sector. If it throws */
/* an error during compilation remove an object here to get */
/* it linked after the configuration sector. */
cpu/bf561/start.o (.text)
cpu/bf561/start1.o (.text)
cpu/bf561/traps.o (.text)
cpu/bf561/interrupt.o (.text)
cpu/bf561/serial.o (.text)
common/dlmalloc.o (.text)
/* lib_blackfin/bf533_string.o (.text) */
/* lib_generic/vsprintf.o (.text) */
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
board/bf561-ezkit/bf561-ezkit.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
___u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
___u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

2
board/mpc8641hpcn/u-boot.lds
View file

@ -120,10 +120,12 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;

16
board/sc3/Makefile
View file

@ -23,13 +23,17 @@
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
LIB = $(obj)lib$(BOARD).a
OBJS = $(BOARD).o sc3nand.o
COBJS = $(BOARD).o sc3nand.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
@ -39,9 +43,9 @@ distclean: clean
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude .depend
sinclude $(obj).depend
#########################################################################

2
board/tqm8272/tqm8272.c
View file

@ -768,7 +768,7 @@ int analyse_hwib (void)
p +=1;
p +=1; /* connector */
if (*p != '0') {
hw->eeprom = 0x100 << (*p - 'A');
hw->eeprom = 0x1000 << (*p - 'A');
}
p++;

35
common/cmd_bootm.c
View file

@ -242,26 +242,26 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
len_ptr = (ulong *)data;
#if defined(__PPC__)
if (hdr->ih_arch != IH_CPU_PPC)
#elif defined(__ARM__)
#if defined(__ARM__)
if (hdr->ih_arch != IH_CPU_ARM)
#elif defined(__avr32__)
if (hdr->ih_arch != IH_CPU_AVR32)
#elif defined(__bfin__)
if (hdr->ih_arch != IH_CPU_BLACKFIN)
#elif defined(__I386__)
if (hdr->ih_arch != IH_CPU_I386)
#elif defined(__mips__)
if (hdr->ih_arch != IH_CPU_MIPS)
#elif defined(__nios__)
if (hdr->ih_arch != IH_CPU_NIOS)
#elif defined(__M68K__)
if (hdr->ih_arch != IH_CPU_M68K)
#elif defined(__microblaze__)
if (hdr->ih_arch != IH_CPU_MICROBLAZE)
#elif defined(__mips__)
if (hdr->ih_arch != IH_CPU_MIPS)
#elif defined(__nios__)
if (hdr->ih_arch != IH_CPU_NIOS)
#elif defined(__nios2__)
if (hdr->ih_arch != IH_CPU_NIOS2)
#elif defined(__blackfin__)
if (hdr->ih_arch != IH_CPU_BLACKFIN)
#elif defined(__avr32__)
if (hdr->ih_arch != IH_CPU_AVR32)
#elif defined(__PPC__)
if (hdr->ih_arch != IH_CPU_PPC)
#else
# error Unknown CPU type
#endif
@ -1354,19 +1354,20 @@ print_type (image_header_t *hdr)
case IH_CPU_ALPHA: arch = "Alpha"; break;
case IH_CPU_ARM: arch = "ARM"; break;
case IH_CPU_AVR32: arch = "AVR32"; break;
case IH_CPU_BLACKFIN: arch = "Blackfin"; break;
case IH_CPU_I386: arch = "Intel x86"; break;
case IH_CPU_IA64: arch = "IA64"; break;
case IH_CPU_MIPS: arch = "MIPS"; break;
case IH_CPU_M68K: arch = "M68K"; break;
case IH_CPU_MICROBLAZE: arch = "Microblaze"; break;
case IH_CPU_MIPS64: arch = "MIPS 64 Bit"; break;
case IH_CPU_MIPS: arch = "MIPS"; break;
case IH_CPU_NIOS2: arch = "Nios-II"; break;
case IH_CPU_NIOS: arch = "Nios"; break;
case IH_CPU_PPC: arch = "PowerPC"; break;
case IH_CPU_S390: arch = "IBM S390"; break;
case IH_CPU_SH: arch = "SuperH"; break;
case IH_CPU_SPARC: arch = "SPARC"; break;
case IH_CPU_SPARC64: arch = "SPARC 64 Bit"; break;
case IH_CPU_M68K: arch = "M68K"; break;
case IH_CPU_MICROBLAZE: arch = "Microblaze"; break;
case IH_CPU_NIOS: arch = "Nios"; break;
case IH_CPU_NIOS2: arch = "Nios-II"; break;
case IH_CPU_SPARC: arch = "SPARC"; break;
default: arch = "Unknown Architecture"; break;
}

2
config.mk
View file

@ -70,7 +70,7 @@ endif
endif
ifeq ($(ARCH),blackfin)
PLATFORM_CPPFLAGS+= -D__BLACKFIN__ -mno-underscore
PLATFORM_CPPFLAGS+= -D__BLACKFIN__
endif
ifdef ARCH

10
cpu/bf533/Makefile
View file

@ -28,14 +28,16 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o start1.o interrupt.o cache.o cplbhdlr.o cplbmgr.o flush.o
COBJS = cpu.o traps.o ints.o serial.o interrupts.o
START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o
EXTRA = init_sdram_bootrom_initblock.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)

3
cpu/bf533/bf533_serial.h
View file

@ -63,8 +63,7 @@ int serial_getc(void);
void serial_puts(const char *s);
static void local_put_char(char ch);
extern int get_clock(void);
int baud_table[5] = {9600, 19200, 38400, 57600, 115200};
int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
struct {
unsigned char dl_high;

65
cpu/bf533/cache.S
View file

@ -1,12 +1,11 @@
#define ASSEMBLY
#include <asm/linkage.h>
#include <asm/cpu/def_LPBlackfin.h>
#include <config.h>
#include <asm/blackfin.h>
.text
.align 2
ENTRY(blackfin_icache_flush_range)
ENTRY(_blackfin_icache_flush_range)
R2 = -32;
R2 = R0 & R2;
P0 = R2;
@ -20,7 +19,7 @@ ENTRY(blackfin_icache_flush_range)
SSYNC;
RTS;
ENTRY(blackfin_dcache_flush_range)
ENTRY(_blackfin_dcache_flush_range)
R2 = -32;
R2 = R0 & R2;
P0 = R2;
@ -35,19 +34,21 @@ ENTRY(blackfin_dcache_flush_range)
RTS;
ENTRY(_icache_invalidate)
ENTRY(invalidate_entire_icache)
[--SP] = ( R7:5);
ENTRY(_invalidate_entire_icache)
[--SP] = (R7:5);
P0.L = (IMEM_CONTROL & 0xFFFF);
P0.H = (IMEM_CONTROL >> 16);
R7 = [P0];
R7 =[P0];
/* Clear the IMC bit , All valid bits in the instruction
/*
* Clear the IMC bit , All valid bits in the instruction
* cache are set to the invalid state
*/
BITCLR(R7,IMC_P);
BITCLR(R7, IMC_P);
CLI R6;
SSYNC; /* SSYNC required before invalidating cache. */
/* SSYNC required before invalidating cache. */
SSYNC;
.align 8;
[P0] = R7;
SSYNC;
@ -58,54 +59,55 @@ ENTRY(invalidate_entire_icache)
R7 = R7 | R6;
CLI R6;
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
SSYNC;
.align 8;
[P0] = R7;
SSYNC;
STI R6;
( R7:5) = [SP++];
(R7:5) =[SP++];
RTS;
/* Invalidate the Entire Data cache by
/*
* Invalidate the Entire Data cache by
* clearing DMC[1:0] bits
*/
ENTRY(invalidate_entire_dcache)
ENTRY(_invalidate_entire_dcache)
ENTRY(_dcache_invalidate)
[--SP] = ( R7:6);
[--SP] = (R7:6);
P0.L = (DMEM_CONTROL & 0xFFFF);
P0.H = (DMEM_CONTROL >> 16);
R7 = [P0];
R7 =[P0];
/* Clear the DMC[1:0] bits, All valid bits in the data
/*
* Clear the DMC[1:0] bits, All valid bits in the data
* cache are set to the invalid state
*/
BITCLR(R7,DMC0_P);
BITCLR(R7,DMC1_P);
BITCLR(R7, DMC0_P);
BITCLR(R7, DMC1_P);
CLI R6;
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
SSYNC;
.align 8;
[P0] = R7;
SSYNC;
STI R6;
/* Configures the data cache again */
R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
R7 = R7 | R6;
CLI R6;
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
SSYNC;
.align 8;
[P0] = R7;
SSYNC;
STI R6;
( R7:6) = [SP++];
(R7:6) =[SP++];
RTS;
ENTRY(blackfin_dcache_invalidate_range)
ENTRY(_blackfin_dcache_invalidate_range)
R2 = -32;
R2 = R0 & R2;
P0 = R2;
@ -113,13 +115,14 @@ ENTRY(blackfin_dcache_invalidate_range)
CSYNC;
1:
FLUSHINV[P0++];
CC = P0 < P1 (iu);
IF CC JUMP 1b (bp);
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
/* If the data crosses a cache line, then we'll be pointing to
** the last cache line, but won't have flushed/invalidated it yet, so do
** one more.
*/
/*
* If the data crosses a cache line, then we'll be pointing to
* the last cache line, but won't have flushed/invalidated it yet, so do
* one more.
*/
FLUSHINV[P0];
SSYNC;
RTS;

2
cpu/bf533/config.mk
View file

@ -24,4 +24,4 @@
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -ffixed-P5
PLATFORM_RELFLAGS += -mcpu=bf533 -ffixed-P5

193
cpu/bf533/cplbhdlr.S
View file

@ -1,193 +0,0 @@
/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
*
* This file is subject to the terms and conditions of the GNU General Public
* License.
*
* Blackfin BF533/2.6 support : LG Soft India
*/
/* Include an exception handler to invoke the CPLB manager
*/
#include <asm-blackfin/linkage.h>
#include <asm/cplb.h>
#include <asm/entry.h>
.text
.globl _cplb_hdr;
.type _cplb_hdr, STT_FUNC;
.extern _cplb_mgr;
.type _cplb_mgr, STT_FUNC;
.extern __unknown_exception_occurred;
.type __unknown_exception_occurred, STT_FUNC;
.extern __cplb_miss_all_locked;
.type __cplb_miss_all_locked, STT_FUNC;
.extern __cplb_miss_without_replacement;
.type __cplb_miss_without_replacement, STT_FUNC;
.extern __cplb_protection_violation;
.type __cplb_protection_violation, STT_FUNC;
.extern panic_pv;
.align 2;
ENTRY(_cplb_hdr)
SSYNC;
[--SP] = ( R7:0, P5:0 );
[--SP] = ASTAT;
[--SP] = SEQSTAT;
[--SP] = I0;
[--SP] = I1;
[--SP] = I2;
[--SP] = I3;
[--SP] = LT0;
[--SP] = LB0;
[--SP] = LC0;
[--SP] = LT1;
[--SP] = LB1;
[--SP] = LC1;
R2 = SEQSTAT;
/*Mask the contents of SEQSTAT and leave only EXCAUSE in R2*/
R2 <<= 26;
R2 >>= 26;
R1 = 0x23; /* Data access CPLB protection violation */
CC = R2 == R1;
IF !CC JUMP not_data_write;
R0 = 2; /* is a write to data space*/
JUMP is_icplb_miss;
not_data_write:
R1 = 0x2C; /* CPLB miss on an instruction fetch */
CC = R2 == R1;
R0 = 0; /* is_data_miss == False*/
IF CC JUMP is_icplb_miss;
R1 = 0x26;
CC = R2 == R1;
IF !CC JUMP unknown;
R0 = 1; /* is_data_miss == True*/
is_icplb_miss:
#if ( defined (CONFIG_BLKFIN_CACHE) || defined (CONFIG_BLKFIN_DCACHE))
#if ( defined (CONFIG_BLKFIN_CACHE) && !defined (CONFIG_BLKFIN_DCACHE))
R1 = CPLB_ENABLE_ICACHE;
#endif
#if ( !defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
R1 = CPLB_ENABLE_DCACHE;
#endif
#if ( defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
#endif
#else
R1 = 0;
#endif
[--SP] = RETS;
CALL _cplb_mgr;
RETS = [SP++];
CC = R0 == 0;
IF !CC JUMP not_replaced;
LC1 = [SP++];
LB1 = [SP++];
LT1 = [SP++];
LC0 = [SP++];
LB0 = [SP++];
LT0 = [SP++];
I3 = [SP++];
I2 = [SP++];
I1 = [SP++];
I0 = [SP++];
SEQSTAT = [SP++];
ASTAT = [SP++];
( R7:0, P5:0 ) = [SP++];
RTS;
unknown:
[--SP] = RETS;
CALL __unknown_exception_occurred;
RETS = [SP++];
JUMP unknown;
not_replaced:
CC = R0 == CPLB_NO_UNLOCKED;
IF !CC JUMP next_check;
[--SP] = RETS;
CALL __cplb_miss_all_locked;
RETS = [SP++];
next_check:
CC = R0 == CPLB_NO_ADDR_MATCH;
IF !CC JUMP next_check2;
[--SP] = RETS;
CALL __cplb_miss_without_replacement;
RETS = [SP++];
JUMP not_replaced;
next_check2:
CC = R0 == CPLB_PROT_VIOL;
IF !CC JUMP strange_return_from_cplb_mgr;
[--SP] = RETS;
CALL __cplb_protection_violation;
RETS = [SP++];
JUMP not_replaced;
strange_return_from_cplb_mgr:
IDLE;
CSYNC;
JUMP strange_return_from_cplb_mgr;
/************************************
* Diagnostic exception handlers
*/
__cplb_miss_all_locked:
sp += -12;
R0 = CPLB_NO_UNLOCKED;
call panic_bfin;
SP += 12;
RTS;
__cplb_miss_without_replacement:
sp += -12;
R0 = CPLB_NO_ADDR_MATCH;
call panic_bfin;
SP += 12;
RTS;
__cplb_protection_violation:
sp += -12;
R0 = CPLB_PROT_VIOL;
call panic_bfin;
SP += 12;
RTS;
__unknown_exception_occurred:
/* This function is invoked by the default exception
* handler, if it does not recognise the kind of
* exception that has occurred. In other words, the
* default handler only handles some of the system's
* exception types, and it does not expect any others
* to occur. If your application is going to be using
* other kinds of exceptions, you must replace the
* default handler with your own, that handles all the
* exceptions you will use.
*
* Since there's nothing we can do, we just loop here
* at what we hope is a suitably informative label.
*/
IDLE;
do_not_know_what_to_do:
CSYNC;
JUMP __unknown_exception_occurred;
RTS;
.__unknown_exception_occurred.end:
.global __unknown_exception_occurred;
.type __unknown_exception_occurred, STT_FUNC;
panic_bfin:
RTS;

601
cpu/bf533/cplbmgr.S
View file

@ -1,601 +0,0 @@
/*This file is subject to the terms and conditions of the GNU General Public
* License.
*
* Blackfin BF533/2.6 support : LG Soft India
* Modification: Dec 07 2004
* 1. Correction in icheck_lock. Valid lock entries were
* geting victimized, for instruction cplb replacement.
* 2. Setup loop's are modified as now toolchain support's P Indexed
* addressing
* :LG Soft India
*
*/
/* Usage: int _cplb_mgr(is_data_miss,int enable_cache)
* is_data_miss==2 => Mark as Dirty, write to the clean data page
* is_data_miss==1 => Replace a data CPLB.
* is_data_miss==0 => Replace an instruction CPLB.
*
* Returns:
* CPLB_RELOADED => Successfully updated CPLB table.
* CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted.This indicates
* that the CPLBs in the configuration tablei are badly
* configured, as this should never occur.
* CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the exception,
* is not covered by any of the CPLBs in the configuration
* table. The application isi presumably misbehaving.
* CPLB_PROT_VIOL => The address being accessed, that triggered thei exception,
* was not a first-write to a clean Write Back Data page,
* and so presumably is a genuine violation of the page's
* protection attributes. The application is misbehaving.
*/
#define ASSEMBLY
#include <asm-blackfin/linkage.h>
#include <asm-blackfin/blackfin.h>
#include <asm-blackfin/cplbtab.h>
#include <asm-blackfin/cplb.h>
.text
.align 2;
ENTRY(_cplb_mgr)
[--SP]=( R7:0,P5:0 );
CC = R0 == 2;
IF CC JUMP dcplb_write;
CC = R0 == 0;
IF !CC JUMP dcplb_miss_compare;
/* ICPLB Miss Exception. We need to choose one of the
* currently-installed CPLBs, and replace it with one
* from the configuration table.
*/
P4.L = (ICPLB_FAULT_ADDR & 0xFFFF);
P4.H = (ICPLB_FAULT_ADDR >> 16);
P1 = 16;
P5.L = page_size_table;
P5.H = page_size_table;
P0.L = (ICPLB_DATA0 & 0xFFFF);
P0.H = (ICPLB_DATA0 >> 16);
R4 = [P4]; /* Get faulting address*/
R6 = 64; /* Advance past the fault address, which*/
R6 = R6 + R4; /* we'll use if we find a match*/
R3 = ((16 << 8) | 2); /* Extract mask, bits 16 and 17.*/
R5 = 0;
isearch:
R1 = [P0-0x100]; /* Address for this CPLB */
R0 = [P0++]; /* Info for this CPLB*/
CC = BITTST(R0,0); /* Is the CPLB valid?*/
IF !CC JUMP nomatch; /* Skip it, if not.*/
CC = R4 < R1(IU); /* If fault address less than page start*/
IF CC JUMP nomatch; /* then skip this one.*/
R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/
P1 = R2;
P1 = P5 + (P1<<2); /* index into page-size table*/
R2 = [P1]; /* Get the page size*/
R1 = R1 + R2; /* and add to page start, to get page end*/
CC = R4 < R1(IU); /* and see whether fault addr is in page.*/
IF !CC R4 = R6; /* If so, advance the address and finish loop.*/
IF !CC JUMP isearch_done;
nomatch:
/* Go around again*/
R5 += 1;
CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/
IF !CC JUMP isearch;
isearch_done:
I0 = R4; /* Fault address we'll search for*/
/* set up pointers */
P0.L = (ICPLB_DATA0 & 0xFFFF);
P0.H = (ICPLB_DATA0 >> 16);
/* The replacement procedure for ICPLBs */
P4.L = (IMEM_CONTROL & 0xFFFF);
P4.H = (IMEM_CONTROL >> 16);
/* disable cplbs */
R5 = [P4]; /* Control Register*/
BITCLR(R5,ENICPLB_P);
CLI R1;
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
.align 8;
[P4] = R5;
SSYNC;
STI R1;
R1 = -1; /* end point comparison */
R3 = 16; /* counter */
/* Search through CPLBs for first non-locked entry */
/* Overwrite it by moving everyone else up by 1 */
icheck_lock:
R0 = [P0++];
R3 = R3 + R1;
CC = R3 == R1;
IF CC JUMP all_locked;
CC = BITTST(R0, 0); /* an invalid entry is good */
IF !CC JUMP ifound_victim;
CC = BITTST(R0,1); /* but a locked entry isn't */
IF CC JUMP icheck_lock;
ifound_victim:
#ifdef CONFIG_CPLB_INFO
R7 = [P0 - 0x104];
P2.L = ipdt_table;
P2.H = ipdt_table;
P3.L = ipdt_swapcount_table;
P3.H = ipdt_swapcount_table;
P3 += -4;
icount:
R2 = [P2]; /* address from config table */
P2 += 8;
P3 += 8;
CC = R2==-1;
IF CC JUMP icount_done;
CC = R7==R2;
IF !CC JUMP icount;
R7 = [P3];
R7 += 1;
[P3] = R7;
CSYNC;
icount_done:
#endif
LC0=R3;
LSETUP(is_move,ie_move) LC0;
is_move:
R0 = [P0];
[P0 - 4] = R0;
R0 = [P0 - 0x100];
[P0-0x104] = R0;
ie_move:P0+=4;
/* We've made space in the ICPLB table, so that ICPLB15
* is now free to be overwritten. Next, we have to determine
* which CPLB we need to install, from the configuration
* table. This is a matter of getting the start-of-page
* addresses and page-lengths from the config table, and
* determining whether the fault address falls within that
* range.
*/
P2.L = ipdt_table;
P2.H = ipdt_table;
#ifdef CONFIG_CPLB_INFO
P3.L = ipdt_swapcount_table;
P3.H = ipdt_swapcount_table;
P3 += -8;
#endif
P0.L = page_size_table;
P0.H = page_size_table;
/* Retrieve our fault address (which may have been advanced
* because the faulting instruction crossed a page boundary).
*/
R0 = I0;
/* An extraction pattern, to get the page-size bits from
* the CPLB data entry. Bits 16-17, so two bits at posn 16.
*/
R1 = ((16<<8)|2);
inext: R4 = [P2++]; /* address from config table */
R2 = [P2++]; /* data from config table */
#ifdef CONFIG_CPLB_INFO
P3 += 8;
#endif
CC = R4 == -1; /* End of config table*/
IF CC JUMP no_page_in_table;
/* See if failed address > start address */
CC = R4 <= R0(IU);
IF !CC JUMP inext;
/* extract page size (17:16)*/
R3 = EXTRACT(R2, R1.L) (Z);
/* add page size to addr to get range */
P5 = R3;
P5 = P0 + (P5 << 2); /* scaled, for int access*/
R3 = [P5];
R3 = R3 + R4;
/* See if failed address < (start address + page size) */
CC = R0 < R3(IU);
IF !CC JUMP inext;
/* We've found a CPLB in the config table that covers
* the faulting address, so install this CPLB into the
* last entry of the table.
*/
P1.L = (ICPLB_DATA15 & 0xFFFF); /*ICPLB_DATA15*/
P1.H = (ICPLB_DATA15 >> 16);
[P1] = R2;
[P1-0x100] = R4;
#ifdef CONFIG_CPLB_INFO
R3 = [P3];
R3 += 1;
[P3] = R3;
#endif
/* P4 points to IMEM_CONTROL, and R5 contains its old
* value, after we disabled ICPLBS. Re-enable them.
*/
BITSET(R5,ENICPLB_P);
CLI R2;
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
.align 8;
[P4] = R5;
SSYNC;
STI R2;
( R7:0,P5:0 ) = [SP++];
R0 = CPLB_RELOADED;
RTS;
/* FAILED CASES*/
no_page_in_table:
( R7:0,P5:0 ) = [SP++];
R0 = CPLB_NO_ADDR_MATCH;
RTS;
all_locked:
( R7:0,P5:0 ) = [SP++];
R0 = CPLB_NO_UNLOCKED;
RTS;
prot_violation:
( R7:0,P5:0 ) = [SP++];
R0 = CPLB_PROT_VIOL;
RTS;
dcplb_write:
/* if a DCPLB is marked as write-back (CPLB_WT==0), and
* it is clean (CPLB_DIRTY==0), then a write to the
* CPLB's page triggers a protection violation. We have to
* mark the CPLB as dirty, to indicate that there are
* pending writes associated with the CPLB.
*/
P4.L = (DCPLB_STATUS & 0xFFFF);
P4.H = (DCPLB_STATUS >> 16);
P3.L = (DCPLB_DATA0 & 0xFFFF);
P3.H = (DCPLB_DATA0 >> 16);
R5 = [P4];
/* A protection violation can be caused by more than just writes
* to a clean WB page, so we have to ensure that:
* - It's a write
* - to a clean WB page
* - and is allowed in the mode the access occurred.
*/
CC = BITTST(R5, 16); /* ensure it was a write*/
IF !CC JUMP prot_violation;
/* to check the rest, we have to retrieve the DCPLB.*/
/* The low half of DCPLB_STATUS is a bit mask*/
R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/
R3 = 30; /* so we can use this to determine the offset*/
R2.L = SIGNBITS R2;
R2 = R2.L (Z); /* into the DCPLB table.*/
R3 = R3 - R2;
P4 = R3;
P3 = P3 + (P4<<2);
R3 = [P3]; /* Retrieve the CPLB*/
/* Now we can check whether it's a clean WB page*/
CC = BITTST(R3, 14); /* 0==WB, 1==WT*/
IF CC JUMP prot_violation;
CC = BITTST(R3, 7); /* 0 == clean, 1 == dirty*/
IF CC JUMP prot_violation;
/* Check whether the write is allowed in the mode that was active.*/
R2 = 1<<3; /* checking write in user mode*/
CC = BITTST(R5, 17); /* 0==was user, 1==was super*/
R5 = CC;
R2 <<= R5; /* if was super, check write in super mode*/
R2 = R3 & R2;
CC = R2 == 0;
IF CC JUMP prot_violation;
/* It's a genuine write-to-clean-page.*/
BITSET(R3, 7); /* mark as dirty*/
[P3] = R3; /* and write back.*/
CSYNC;
( R7:0,P5:0 ) = [SP++];
R0 = CPLB_RELOADED;
RTS;
dcplb_miss_compare:
/* Data CPLB Miss event. We need to choose a CPLB to
* evict, and then locate a new CPLB to install from the
* config table, that covers the faulting address.
*/
P1.L = (DCPLB_DATA15 & 0xFFFF);
P1.H = (DCPLB_DATA15 >> 16);
P4.L = (DCPLB_FAULT_ADDR & 0xFFFF);
P4.H = (DCPLB_FAULT_ADDR >> 16);
R4 = [P4];
I0 = R4;
/* The replacement procedure for DCPLBs*/
R6 = R1; /* Save for later*/
/* Turn off CPLBs while we work.*/
P4.L = (DMEM_CONTROL & 0xFFFF);
P4.H = (DMEM_CONTROL >> 16);
R5 = [P4];
BITCLR(R5,ENDCPLB_P);
CLI R0;
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
.align 8;
[P4] = R5;
SSYNC;
STI R0;
/* Start looking for a CPLB to evict. Our order of preference
* is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs
* are no good.
*/
I1.L = (DCPLB_DATA0 & 0xFFFF);
I1.H = (DCPLB_DATA0 >> 16);
P1 = 3;
P2 = 16;
I2.L = dcplb_preference;
I2.H = dcplb_preference;
LSETUP(sdsearch1, edsearch1) LC0 = P1;
sdsearch1:
R0 = [I2++]; /* Get the bits we're interested in*/
P0 = I1; /* Go back to start of table*/
LSETUP (sdsearch2, edsearch2) LC1 = P2;
sdsearch2:
R1 = [P0++]; /* Fetch each installed CPLB in turn*/
R2 = R1 & R0; /* and test for interesting bits.*/
CC = R2 == 0; /* If none are set, it'll do.*/
IF !CC JUMP skip_stack_check;
R2 = [P0 - 0x104]; /* R2 - PageStart */
P3.L = page_size_table; /* retrive end address */
P3.H = page_size_table; /* retrive end address */
R3 = 0x2; /* 0th - position, 2 bits -length */
nop; /*Anamoly 05000209*/
R7 = EXTRACT(R1,R3.l);
R7 = R7 << 2; /* Page size index offset */
P5 = R7;
P3 = P3 + P5;
R7 = [P3]; /* page size in 1K bytes */
R7 = R7 << 0xA; /* in bytes * 1024*/
R7 = R2 + R7; /* R7 - PageEnd */
R4 = SP; /* Test SP is in range */
CC = R7 < R4; /* if PageEnd < SP */
IF CC JUMP dfound_victim;
R3 = 0x284; /* stack length from start of trap till the point */
/* 20 stack locations for future modifications */
R4 = R4 + R3;
CC = R4 < R2; /* if SP + stacklen < PageStart */
IF CC JUMP dfound_victim;
skip_stack_check:
edsearch2: NOP;
edsearch1: NOP;
/* If we got here, we didn't find a DCPLB we considered
* replacable, which means all of them were locked.
*/
JUMP all_locked;
dfound_victim:
#ifdef CONFIG_CPLB_INFO
R1 = [P0 - 0x104];
P2.L = dpdt_table;
P2.H = dpdt_table;
P3.L = dpdt_swapcount_table;
P3.H = dpdt_swapcount_table;
P3 += -4;
dicount:
R2 = [P2];
P2 += 8;
P3 += 8;
CC = R2==-1;
IF CC JUMP dicount_done;
CC = R1==R2;
IF !CC JUMP dicount;
R1 = [P3];
R1 += 1;
[P3] = R1;
CSYNC;
dicount_done:
#endif
/* Clean down the hardware loops*/
R2 = 0;
LC1 = R2;
LC0 = R2;
/* There's a suitable victim in [P0-4] (because we've
* advanced already). If it's a valid dirty write-back
* CPLB, we need to flush the pending writes first.
*/
CC = BITTST(R1, 0); /* Is it valid?*/
IF !CC JUMP Ddoverwrite;/* nope.*/
CC = BITTST(R1, 7); /* Is it dirty?*/
IF !CC JUMP Ddoverwrite (BP); /* Nope.*/
CC = BITTST(R1, 14); /* Is it Write-Through?*/
IF CC JUMP Ddoverwrite; /* Yep*/
/* This is a dirty page, so we need to flush all writes
* that are pending on the page.
*/
/* Retrieve the page start address*/
R0 = [P0 - 0x104];
[--sp] = rets;
CALL dcplb_flush; /* R0==CPLB addr, R1==CPLB data*/
rets = [sp++];
Ddoverwrite:
/* [P0-4] is a suitable victim CPLB, so we want to
* overwrite it by moving all the following CPLBs
* one space closer to the start.
*/
R1.L = ((DCPLB_DATA15+4) & 0xFFFF); /*DCPLB_DATA15+4*/
R1.H = ((DCPLB_DATA15+4) >> 16);
R0 = P0;
/* If the victim happens to be in DCPLB15,
* we don't need to move anything.
*/
CC = R1 == R0;
IF CC JUMP de_moved;
R1 = R1 - R0;
R1 >>= 2;
P1 = R1;
LSETUP(ds_move, de_move) LC0=P1;
ds_move:
R0 = [P0++]; /* move data */
[P0 - 8] = R0;
R0 = [P0-0x104] /* move address */
de_move: [P0-0x108] = R0;
/* We've now made space in DCPLB15 for the new CPLB to be
* installed. The next stage is to locate a CPLB in the
* config table that covers the faulting address.
*/
de_moved:NOP;
R0 = I0; /* Our faulting address */
P2.L = dpdt_table;
P2.H = dpdt_table;
#ifdef CONFIG_CPLB_INFO
P3.L = dpdt_swapcount_table;
P3.H = dpdt_swapcount_table;
P3 += -8;
#endif
P1.L = page_size_table;
P1.H = page_size_table;
/* An extraction pattern, to retrieve bits 17:16.*/
R1 = (16<<8)|2;
dnext: R4 = [P2++]; /* address */
R2 = [P2++]; /* data */
#ifdef CONFIG_CPLB_INFO
P3 += 8;
#endif
CC = R4 == -1;
IF CC JUMP no_page_in_table;
/* See if failed address > start address */
CC = R4 <= R0(IU);
IF !CC JUMP dnext;
/* extract page size (17:16)*/
R3 = EXTRACT(R2, R1.L) (Z);
/* add page size to addr to get range */
P5 = R3;
P5 = P1 + (P5 << 2);
R3 = [P5];
R3 = R3 + R4;
/* See if failed address < (start address + page size) */
CC = R0 < R3(IU);
IF !CC JUMP dnext;
/* We've found the CPLB that should be installed, so
* write it into CPLB15, masking off any caching bits
* if necessary.
*/
P1.L = (DCPLB_DATA15 & 0xFFFF);
P1.H = (DCPLB_DATA15 >> 16);
/* If the DCPLB has cache bits set, but caching hasn't
* been enabled, then we want to mask off the cache-in-L1
* bit before installing. Moreover, if caching is off, we
* also want to ensure that the DCPLB has WT mode set, rather
* than WB, since WB pages still trigger first-write exceptions
* even when not caching is off, and the page isn't marked as
* cachable. Finally, we could mark the page as clean, not dirty,
* but we choose to leave that decision to the user; if the user
* chooses to have a CPLB pre-defined as dirty, then they always
* pay the cost of flushing during eviction, but don't pay the
* cost of first-write exceptions to mark the page as dirty.
*/
#ifdef CONFIG_BLKFIN_WT
BITSET(R6, 14); /* Set WT*/
#endif
[P1] = R2;
[P1-0x100] = R4;
#ifdef CONFIG_CPLB_INFO
R3 = [P3];
R3 += 1;
[P3] = R3;
#endif
/* We've installed the CPLB, so re-enable CPLBs. P4
* points to DMEM_CONTROL, and R5 is the value we
* last wrote to it, when we were disabling CPLBs.
*/
BITSET(R5,ENDCPLB_P);
CLI R2;
.align 8;
[P4] = R5;
SSYNC;
STI R2;
( R7:0,P5:0 ) = [SP++];
R0 = CPLB_RELOADED;
RTS;
.data
.align 4;
page_size_table:
.byte4 0x00000400; /* 1K */
.byte4 0x00001000; /* 4K */
.byte4 0x00100000; /* 1M */
.byte4 0x00400000; /* 4M */
.align 4;
dcplb_preference:
.byte4 0x00000001; /* valid bit */
.byte4 0x00000082; /* dirty+lock bits */
.byte4 0x00000002; /* lock bit */

196
cpu/bf533/cpu.c
View file

@ -29,72 +29,19 @@
#include <asm/blackfin.h>
#include <command.h>
#include <asm/entry.h>
#include <asm/cplb.h>
#include <asm/io.h>
#define SSYNC() asm("ssync;")
#define CACHE_ON 1
#define CACHE_OFF 0
/* Data Attibutes*/
extern unsigned int icplb_table[page_descriptor_table_size][2];
extern unsigned int dcplb_table[page_descriptor_table_size][2];
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
#define ANOMALY_05000158 0x200
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
static unsigned int icplb_table[16][2]={
{0xFFA00000, L1_IMEMORY},
{0x00000000, SDRAM_IKERNEL}, /*SDRAM_Page1*/
{0x00400000, SDRAM_IKERNEL}, /*SDRAM_Page1*/
{0x07C00000, SDRAM_IKERNEL}, /*SDRAM_Page14*/
{0x00800000, SDRAM_IGENERIC}, /*SDRAM_Page2*/
{0x00C00000, SDRAM_IGENERIC}, /*SDRAM_Page2*/
{0x01000000, SDRAM_IGENERIC}, /*SDRAM_Page4*/
{0x01400000, SDRAM_IGENERIC}, /*SDRAM_Page5*/
{0x01800000, SDRAM_IGENERIC}, /*SDRAM_Page6*/
{0x01C00000, SDRAM_IGENERIC}, /*SDRAM_Page7*/
{0x02000000, SDRAM_IGENERIC}, /*SDRAM_Page8*/
{0x02400000, SDRAM_IGENERIC}, /*SDRAM_Page9*/
{0x02800000, SDRAM_IGENERIC}, /*SDRAM_Page10*/
{0x02C00000, SDRAM_IGENERIC}, /*SDRAM_Page11*/
{0x03000000, SDRAM_IGENERIC}, /*SDRAM_Page12*/
{0x03400000, SDRAM_IGENERIC}, /*SDRAM_Page13*/
};
static unsigned int dcplb_table[16][2]={
{0xFFA00000,L1_DMEMORY},
{0x00000000,SDRAM_DKERNEL}, /*SDRAM_Page1*/
{0x00400000,SDRAM_DKERNEL}, /*SDRAM_Page1*/
{0x07C00000,SDRAM_DKERNEL}, /*SDRAM_Page15*/
{0x00800000,SDRAM_DGENERIC}, /*SDRAM_Page2*/
{0x00C00000,SDRAM_DGENERIC}, /*SDRAM_Page3*/
{0x01000000,SDRAM_DGENERIC}, /*SDRAM_Page4*/
{0x01400000,SDRAM_DGENERIC}, /*SDRAM_Page5*/
{0x01800000,SDRAM_DGENERIC}, /*SDRAM_Page6*/
{0x01C00000,SDRAM_DGENERIC}, /*SDRAM_Page7*/
{0x02000000,SDRAM_DGENERIC}, /*SDRAM_Page8*/
{0x02400000,SDRAM_DGENERIC}, /*SDRAM_Page9*/
{0x02800000,SDRAM_DGENERIC}, /*SDRAM_Page10*/
{0x02C00000,SDRAM_DGENERIC}, /*SDRAM_Page11*/
{0x03000000,SDRAM_DGENERIC}, /*SDRAM_Page12*/
{0x20000000,SDRAM_EBIU}, /*For Network */
};
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
__asm__ __volatile__
("cli r3;"
"P0 = %0;"
"JUMP (P0);"
:
: "r" (L1_ISRAM)
);
__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
);
return 0;
}
@ -112,29 +59,62 @@ int cleanup_before_linux(void)
void icache_enable(void)
{
unsigned int *I0,*I1;
int i;
unsigned int *I0, *I1;
int i, j = 0;
/* Before enable icache, disable it first */
icache_disable();
I0 = (unsigned int *)ICPLB_ADDR0;
I1 = (unsigned int *)ICPLB_DATA0;
for(i=0;i<16;i++){
*I0++ = icplb_table[i][0];
*I1++ = icplb_table[i][1];
/* make sure the locked ones go in first */
for (i = 0; i < page_descriptor_table_size; i++) {
if (CPLB_LOCK & icplb_table[i][1]) {
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
icplb_table[i][0], icplb_table[i][1]);
*I0++ = icplb_table[i][0];
*I1++ = icplb_table[i][1];
j++;
}
}
for (i = 0; i < page_descriptor_table_size; i++) {
if (!(CPLB_LOCK & icplb_table[i][1])) {
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
icplb_table[i][0], icplb_table[i][1]);
*I0++ = icplb_table[i][0];
*I1++ = icplb_table[i][1];
j++;
if (j == 16) {
break;
}
}
}
/* Fill the rest with invalid entry */
if (j <= 15) {
for (; j <= 16; j++) {
debug("filling %i with 0", j);
*I1++ = 0x0;
}
}
cli();
SSYNC();
sync();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
SSYNC();
sync();
sti();
}
void icache_disable(void)
{
cli();
SSYNC();
sync();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
SSYNC();
sync();
sti();
}
@ -143,7 +123,7 @@ int icache_status(void)
unsigned int value;
value = *(unsigned int *)IMEM_CONTROL;
if( value & (IMC|ENICPLB) )
if (value & (IMC | ENICPLB))
return CACHE_ON;
else
return CACHE_OFF;
@ -151,38 +131,90 @@ int icache_status(void)
void dcache_enable(void)
{
unsigned int *I0,*I1;
unsigned int *I0, *I1;
unsigned int temp;
int i;
int i, j = 0;
/* Before enable dcache, disable it first */
dcache_disable();
I0 = (unsigned int *)DCPLB_ADDR0;
I1 = (unsigned int *)DCPLB_DATA0;
for(i=0;i<16;i++){
*I0++ = dcplb_table[i][0];
*I1++ = dcplb_table[i][1];
/* make sure the locked ones go in first */
for (i = 0; i < page_descriptor_table_size; i++) {
if (CPLB_LOCK & dcplb_table[i][1]) {
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
dcplb_table[i][0], dcplb_table[i][1]);
*I0++ = dcplb_table[i][0];
*I1++ = dcplb_table[i][1];
j++;
} else {
debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
dcplb_table[i][0], dcplb_table[i][1]);
}
}
for (i = 0; i < page_descriptor_table_size; i++) {
if (!(CPLB_LOCK & dcplb_table[i][1])) {
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
dcplb_table[i][0], dcplb_table[i][1]);
*I0++ = dcplb_table[i][0];
*I1++ = dcplb_table[i][1];
j++;
if (j == 16) {
break;
}
}
}
/* Fill the rest with invalid entry */
if (j <= 15) {
for (; j <= 16; j++) {
debug("filling %i with 0", j);
*I1++ = 0x0;
}
}
cli();
temp = *(unsigned int *)DMEM_CONTROL;
SSYNC();
*(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE |ENDCPLB |PORT_PREF0|temp;
SSYNC();
sync();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL =
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
sync();
sti();
}
void dcache_disable(void)
{
unsigned int *I0, *I1;
int i;
cli();
SSYNC();
*(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE |ENDCPLB |PORT_PREF0);
SSYNC();
sync();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL &=
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
sync();
sti();
/* after disable dcache,
* clear it so we don't confuse the next application
*/
I0 = (unsigned int *)DCPLB_ADDR0;
I1 = (unsigned int *)DCPLB_DATA0;
for (i = 0; i < 16; i++) {
*I0++ = 0x0;
*I1++ = 0x0;
}
}
int dcache_status(void)
{
unsigned int value;
value = *(unsigned int *)DMEM_CONTROL;
if( value & (ENDCPLB))
if (value & (ENDCPLB))
return CACHE_ON;
else
return CACHE_OFF;

15
cpu/bf533/cpu.h
View file

@ -32,8 +32,8 @@
#define DEF_INTERRUPT_FLAGS 1
#define MAX_TIM_LOAD 0xFFFFFFFF
void blackfin_irq_panic(int reason, struct pt_regs * reg);
extern void dump(struct pt_regs * regs);
void blackfin_irq_panic(int reason, struct pt_regs *reg);
extern void dump(struct pt_regs *regs);
void display_excp(void);
asmlinkage void evt_nmi(void);
asmlinkage void evt_exception(void);
@ -50,16 +50,17 @@ asmlinkage void evt_evt12(void);
asmlinkage void evt_evt13(void);
asmlinkage void evt_soft_int1(void);
asmlinkage void evt_system_call(void);
void blackfin_irq_panic(int reason, struct pt_regs * regs);
void blackfin_irq_panic(int reason, struct pt_regs *regs);
void blackfin_free_irq(unsigned int irq, void *dev_id);
void call_isr(int irq, struct pt_regs * fp);
void call_isr(int irq, struct pt_regs *fp);
void blackfin_do_irq(int vec, struct pt_regs *fp);
void blackfin_init_IRQ(void);
void blackfin_enable_irq(unsigned int irq);
void blackfin_disable_irq(unsigned int irq);
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
int blackfin_request_irq(unsigned int irq,
void (*handler)(int, void *, struct pt_regs *),
unsigned long flags,const char *devname,void *dev_id);
void (*handler) (int, void *, struct pt_regs *),
unsigned long flags, const char *devname,
void *dev_id);
void timer_init(void);
#endif

37
cpu/bf533/flush.S
View file

@ -3,13 +3,12 @@
*
* This file is subject to the terms and conditions of the GNU General Public
* License.
*
* Blackfin BF533/2.6 support : LG Soft India
*/
#define ASSEMBLY
#include <asm/linkage.h>
#include <asm/cplb.h>
#include <config.h>
#include <asm/blackfin.h>
.text
@ -20,7 +19,7 @@
* in the instruction cache.
*/
ENTRY(flush_instruction_cache)
ENTRY(_flush_instruction_cache)
[--SP] = ( R7:6, P5:4 );
LINK 12;
SP += -12;
@ -33,7 +32,7 @@ ENTRY(flush_instruction_cache)
inext: R0 = [P5++];
R1 = [P4++];
[--SP] = RETS;
CALL icplb_flush; /* R0 = page, R1 = data*/
CALL _icplb_flush; /* R0 = page, R1 = data*/
RETS = [SP++];
iskip: R6 += -1;
CC = R6;
@ -52,7 +51,7 @@ iskip: R6 += -1;
*/
.align 2
ENTRY(icplb_flush)
ENTRY(_icplb_flush)
[--SP] = ( R7:0, P5:0 );
[--SP] = LC0;
[--SP] = LT0;
@ -86,16 +85,17 @@ ENTRY(icplb_flush)
*/
R3 = ((12<<8)|2); /* Extraction pattern */
nop; /*Anamoly 05000209*/
R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/
nop; /* Anamoly 05000209 */
R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits */
/* Save in extraction pattern for later deposit. */
R3.H = R4.L << 0;
/* So:
* R0 = Page start
* R1 = Page length (actually, offset into size/prefix tables)
* R3 = sub-bank deposit values
*
*
* The cache has 2 Ways, and 64 sets, so we iterate through
* the sets, accessing the tag for each Way, for our Bank and
* sub-bank, looking for dirty, valid tags that match our
@ -180,8 +180,10 @@ iflush_whole_page:
SSYNC;
IFLUSH [P0++]; /* because CSYNC can't end loops.*/
LSETUP (isall, ieall) LC0 = P1;
isall:IFLUSH [P0++];
ieall: NOP;
isall:
IFLUSH [P0++];
ieall:
NOP;
SSYNC;
JUMP ifinished;
@ -191,7 +193,7 @@ ieall: NOP;
* in the data cache.
*/
ENTRY(flush_data_cache)
ENTRY(_flush_data_cache)
[--SP] = ( R7:6, P5:4 );
LINK 12;
SP += -12;
@ -209,7 +211,7 @@ next: R0 = [P5++];
CC = R2;
IF !CC JUMP skip; /* If not, ignore it.*/
[--SP] = RETS;
CALL dcplb_flush; /* R0 = page, R1 = data*/
CALL _dcplb_flush; /* R0 = page, R1 = data*/
RETS = [SP++];
skip: R6 += -1;
CC = R6;
@ -228,7 +230,7 @@ skip: R6 += -1;
*/
.align 2
ENTRY(dcplb_flush)
ENTRY(_dcplb_flush)
[--SP] = ( R7:0, P5:0 );
[--SP] = LC0;
[--SP] = LT0;
@ -290,14 +292,15 @@ bank_chosen:
R3 = ((12<<8)|2); /* Extraction pattern */
nop; /*Anamoly 05000209*/
R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/
/* Save in extraction pattern for later deposit.*/
R3.H = R4.L << 0;
/* So:
* R0 = Page start
* R1 = Page length (actually, offset into size/prefix tables)
* R2 = Bank select mask
* R3 = sub-bank deposit values
*
*
* The cache has 2 Ways, and 64 sets, so we iterate through
* the sets, accessing the tag for each Way, for our Bank and
* sub-bank, looking for dirty, valid tags that match our
@ -386,7 +389,7 @@ dflush_whole_page:
CC = BITTST(R1, 16); /* Whether 1K or 4K*/
IF CC P1 = P2;
P1 += -1; /* Unroll one iteration*/
SSYNC;
SSYNC;
FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
LSETUP (eall, eall) LC0 = P1;
eall: FLUSHINV [P0++];

179
cpu/bf533/init_sdram.S Normal file
View file

@ -0,0 +1,179 @@
#define ASSEMBLY
#include <linux/config.h>
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mem_init.h>
.global init_sdram;
#if (CONFIG_CCLK_DIV == 1)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
#endif
#if (CONFIG_CCLK_DIV == 2)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
#endif
#if (CONFIG_CCLK_DIV == 4)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
#endif
#if (CONFIG_CCLK_DIV == 8)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
#endif
#ifndef CONFIG_CCLK_ACT_DIV
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
#endif
init_sdram:
[--SP] = ASTAT;
[--SP] = RETS;
[--SP] = (R7:0);
[--SP] = (P5:0);
#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
p0.h = hi(SPI_BAUD);
p0.l = lo(SPI_BAUD);
r0.l = CONFIG_SPI_BAUD;
w[p0] = r0.l;
SSYNC;
#endif
/*
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
*/
p0.h = hi(PLL_LOCKCNT);
p0.l = lo(PLL_LOCKCNT);
r0 = 0x300(Z);
w[p0] = r0.l;
ssync;
/*
* Put SDRAM in self-refresh, incase anything is running
*/
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITSET (R0, 24);
[P2] = R0;
SSYNC;
/*
* Set PLL_CTL with the value that we calculate in R0
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
* - [7] = output delay (add 200ps of delay to mem signals)
* - [6] = input delay (add 200ps of input delay to mem signals)
* - [5] = PDWN : 1=All Clocks off
* - [3] = STOPCK : 1=Core Clock off
* - [1] = PLL_OFF : 1=Disable Power to PLL
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
* all other bits set to zero
*/
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over, */
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
r0 = r1 | r0;
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */
cli r2; /* Disable interrupts */
ssync;
w[p0] = r0.l; /* Set the value */
idle; /* Wait for the PLL to stablize */
sti r2; /* Enable interrupts */
check_again:
p0.h = hi(PLL_STAT);
p0.l = lo(PLL_STAT);
R0 = W[P0](Z);
CC = BITTST(R0,5);
if ! CC jump check_again;
/* Configure SCLK & CCLK Dividers */
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
p0.h = hi(PLL_DIV);
p0.l = lo(PLL_DIV);
w[p0] = r0.l;
ssync;
/*
* We now are running at speed, time to set the Async mem bank wait states
* This will speed up execution, since we are normally running from FLASH.
*/
p2.h = (EBIU_AMBCTL1 >> 16);
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
r0.h = (AMBCTL1VAL >> 16);
r0.l = (AMBCTL1VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMBCTL0 >> 16);
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
r0.h = (AMBCTL0VAL >> 16);
r0.l = (AMBCTL0VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMGCTL >> 16);
p2.l = (EBIU_AMGCTL & 0xffff);
r0 = AMGCTLVAL;
w[p2] = r0;
ssync;
/*
* Now, Initialize the SDRAM,
* start with the SDRAM Refresh Rate Control Register
*/
p0.l = lo(EBIU_SDRRC);
p0.h = hi(EBIU_SDRRC);
r0 = mem_SDRRC;
w[p0] = r0.l;
ssync;
/*
* SDRAM Memory Bank Control Register - bank specific parameters
*/
p0.l = (EBIU_SDBCTL & 0xFFFF);
p0.h = (EBIU_SDBCTL >> 16);
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
/*
* SDRAM Global Control Register - global programmable parameters
* Disable self-refresh
*/
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITCLR (R0, 24);
/*
* Check if SDRAM is already powered up, if it is, enable self-refresh
*/
p0.h = hi(EBIU_SDSTAT);
p0.l = lo(EBIU_SDSTAT);
r2.l = w[p0];
cc = bittst(r2,3);
if !cc jump skip;
NOP;
BITSET (R0, 23);
skip:
[P2] = R0;
SSYNC;
/* Write in the new value in the register */
R0.L = lo(mem_SDGCTL);
R0.H = hi(mem_SDGCTL);
[P2] = R0;
SSYNC;
nop;
(P5:0) = [SP++];
(R7:0) = [SP++];
RETS = [SP++];
ASTAT = [SP++];
RTS;

179
cpu/bf533/init_sdram_bootrom_initblock.S Normal file
View file

@ -0,0 +1,179 @@
#define ASSEMBLY
#include <linux/config.h>
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mem_init.h>
.global init_sdram;
#if (CONFIG_CCLK_DIV == 1)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
#endif
#if (CONFIG_CCLK_DIV == 2)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
#endif
#if (CONFIG_CCLK_DIV == 4)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
#endif
#if (CONFIG_CCLK_DIV == 8)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
#endif
#ifndef CONFIG_CCLK_ACT_DIV
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
#endif
init_sdram:
[--SP] = ASTAT;
[--SP] = RETS;
[--SP] = (R7:0);
[--SP] = (P5:0);
#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
p0.h = hi(SPI_BAUD);
p0.l = lo(SPI_BAUD);
r0.l = CONFIG_SPI_BAUD_INITBLOCK;
w[p0] = r0.l;
SSYNC;
#endif
/*
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
*/
p0.h = hi(PLL_LOCKCNT);
p0.l = lo(PLL_LOCKCNT);
r0 = 0x300(Z);
w[p0] = r0.l;
ssync;
/*
* Put SDRAM in self-refresh, incase anything is running
*/
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITSET (R0, 24);
[P2] = R0;
SSYNC;
/*
* Set PLL_CTL with the value that we calculate in R0
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
* - [7] = output delay (add 200ps of delay to mem signals)
* - [6] = input delay (add 200ps of input delay to mem signals)
* - [5] = PDWN : 1=All Clocks off
* - [3] = STOPCK : 1=Core Clock off
* - [1] = PLL_OFF : 1=Disable Power to PLL
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
* all other bits set to zero
*/
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over, */
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
r0 = r1 | r0;
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */
cli r2; /* Disable interrupts */
ssync;
w[p0] = r0.l; /* Set the value */
idle; /* Wait for the PLL to stablize */
sti r2; /* Enable interrupts */
check_again:
p0.h = hi(PLL_STAT);
p0.l = lo(PLL_STAT);
R0 = W[P0](Z);
CC = BITTST(R0,5);
if ! CC jump check_again;
/* Configure SCLK & CCLK Dividers */
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
p0.h = hi(PLL_DIV);
p0.l = lo(PLL_DIV);
w[p0] = r0.l;
ssync;
/*
* We now are running at speed, time to set the Async mem bank wait states
* This will speed up execution, since we are normally running from FLASH.
*/
p2.h = (EBIU_AMBCTL1 >> 16);
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
r0.h = (AMBCTL1VAL >> 16);
r0.l = (AMBCTL1VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMBCTL0 >> 16);
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
r0.h = (AMBCTL0VAL >> 16);
r0.l = (AMBCTL0VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMGCTL >> 16);
p2.l = (EBIU_AMGCTL & 0xffff);
r0 = AMGCTLVAL;
w[p2] = r0;
ssync;
/*
* Now, Initialize the SDRAM,
* start with the SDRAM Refresh Rate Control Register
*/
p0.l = lo(EBIU_SDRRC);
p0.h = hi(EBIU_SDRRC);
r0 = mem_SDRRC;
w[p0] = r0.l;
ssync;
/*
* SDRAM Memory Bank Control Register - bank specific parameters
*/
p0.l = (EBIU_SDBCTL & 0xFFFF);
p0.h = (EBIU_SDBCTL >> 16);
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
/*
* SDRAM Global Control Register - global programmable parameters
* Disable self-refresh
*/
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITCLR (R0, 24);
/*
* Check if SDRAM is already powered up, if it is, enable self-refresh
*/
p0.h = hi(EBIU_SDSTAT);
p0.l = lo(EBIU_SDSTAT);
r2.l = w[p0];
cc = bittst(r2,3);
if !cc jump skip;
NOP;
BITSET (R0, 23);
skip:
[P2] = R0;
SSYNC;
/* Write in the new value in the register */
R0.L = lo(mem_SDGCTL);
R0.H = hi(mem_SDGCTL);
[P2] = R0;
SSYNC;
nop;
(P5:0) = [SP++];
(R7:0) = [SP++];
RETS = [SP++];
ASTAT = [SP++];
RTS;

251
cpu/bf533/interrupt.S
View file

@ -40,203 +40,58 @@
*/
#define ASSEMBLY
#include <config.h>
#include <asm/blackfin.h>
#include <asm/hw_irq.h>
#include <asm/entry.h>
#include <asm/blackfin_defs.h>
#include <asm/cpu/bf533_irq.h>
.global blackfin_irq_panic;
.global _blackfin_irq_panic;
.text
.align 2
#ifndef CONFIG_KGDB
.global evt_emulation
evt_emulation:
.global _evt_emulation
_evt_emulation:
SAVE_CONTEXT
r0 = IRQ_EMU;
r1 = seqstat;
sp += -12;
call blackfin_irq_panic;
call _blackfin_irq_panic;
sp += 12;
rte;
#endif
.global evt_nmi
evt_nmi:
.global _evt_nmi
_evt_nmi:
SAVE_CONTEXT
r0 = IRQ_NMI;
r1 = RETN;
sp += -12;
call blackfin_irq_panic;
call _blackfin_irq_panic;
sp += 12;
_evt_nmi_exit:
rtn;
.global trap
trap:
[--sp] = r0;
[--sp] = r1;
[--sp] = p0;
[--sp] = p1;
[--sp] = astat;
r0 = seqstat;
R0 <<= 26;
R0 >>= 26;
p0 = r0;
p1.l = EVTABLE;
p1.h = EVTABLE;
p0 = p1 + (p0 << 1);
r1 = W[p0] (Z);
p1 = r1;
jump (pc + p1);
.global _trap
_trap:
SAVE_ALL_SYS
r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
sp += -12;
call _trap_c
sp += 12;
RESTORE_ALL_SYS
rtx;
.global _EVENT1
_EVENT1:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT2
_EVENT2:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT3
_EVENT3:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT4
_EVENT4:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT5
_EVENT5:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT6
_EVENT6:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT7
_EVENT7:
RAISE 15;
JUMP.S _EXIT;
.global _EVENT8
_EVENT8:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT9
_EVENT9:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT10
_EVENT10:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT11
_EVENT11:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT12
_EVENT12:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT13
_EVENT13:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT14
_EVENT14:
/* RAISE 14; */
CALL _cplb_hdr;
JUMP.S _EXIT;
.global _EVENT19
_EVENT19:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT20
_EVENT20:
RAISE 14;
JUMP.S _EXIT;
.global _EVENT21
_EVENT21:
RAISE 14;
JUMP.S _EXIT;
.global _EXIT
_EXIT:
ASTAT = [sp++];
p1 = [sp++];
p0 = [sp++];
r1 = [sp++];
r0 = [sp++];
RTX;
EVTABLE:
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x0000;
.byte2 0x003E;
.byte2 0x0042;
.byte4 0x0000;
.byte4 0x0000;
.byte4 0x0000;
.byte4 0x0000;
.byte4 0x0000;
.byte4 0x0000;
.byte4 0x0000;
.byte2 0x0000;
.byte2 0x001E;
.byte2 0x0022;
.byte2 0x0032;
.byte2 0x002e;
.byte2 0x0002;
.byte2 0x0036;
.byte2 0x002A;
.byte2 0x001A;
.byte2 0x0016;
.byte2 0x000A;
.byte2 0x000E;
.byte2 0x0012;
.byte2 0x0006;
.byte2 0x0026;
.global evt_rst
evt_rst:
.global _evt_rst
_evt_rst:
SAVE_CONTEXT
r0 = IRQ_RST;
r1 = RETN;
sp += -12;
call do_reset;
call _do_reset;
sp += 12;
_evt_rst_exit:
@ -246,19 +101,19 @@ irq_panic:
r0 = IRQ_EVX;
r1 = sp;
sp += -12;
call blackfin_irq_panic;
call _blackfin_irq_panic;
sp += 12;
.global evt_ivhw
evt_ivhw:
.global _evt_ivhw
_evt_ivhw:
SAVE_CONTEXT
RAISE 14;
_evt_ivhw_exit:
rti;
.global evt_timer
evt_timer:
.global _evt_timer
_evt_timer:
SAVE_CONTEXT
r0 = IRQ_CORETMR;
sp += -12;
@ -269,91 +124,91 @@ evt_timer:
rti;
nop;
.global evt_evt7
evt_evt7:
.global _evt_evt7
_evt_evt7:
SAVE_CONTEXT
r0 = 7;
sp += -12;
call process_int;
call _process_int;
sp += 12;
evt_evt7_exit:
RESTORE_CONTEXT
rti;
.global evt_evt8
evt_evt8:
.global _evt_evt8
_evt_evt8:
SAVE_CONTEXT
r0 = 8;
sp += -12;
call process_int;
call _process_int;
sp += 12;
evt_evt8_exit:
RESTORE_CONTEXT
rti;
.global evt_evt9
evt_evt9:
.global _evt_evt9
_evt_evt9:
SAVE_CONTEXT
r0 = 9;
sp += -12;
call process_int;
call _process_int;
sp += 12;
evt_evt9_exit:
RESTORE_CONTEXT
rti;
.global evt_evt10
evt_evt10:
.global _evt_evt10
_evt_evt10:
SAVE_CONTEXT
r0 = 10;
sp += -12;
call process_int;
call _process_int;
sp += 12;
evt_evt10_exit:
RESTORE_CONTEXT
rti;
.global evt_evt11
evt_evt11:
.global _evt_evt11
_evt_evt11:
SAVE_CONTEXT
r0 = 11;
sp += -12;
call process_int;
call _process_int;
sp += 12;
evt_evt11_exit:
RESTORE_CONTEXT
rti;
.global evt_evt12
evt_evt12:
.global _evt_evt12
_evt_evt12:
SAVE_CONTEXT
r0 = 12;
sp += -12;
call process_int;
call _process_int;
sp += 12;
evt_evt12_exit:
RESTORE_CONTEXT
rti;
.global evt_evt13
evt_evt13:
.global _evt_evt13
_evt_evt13:
SAVE_CONTEXT
r0 = 13;
sp += -12;
call process_int;
call _process_int;
sp += 12;
evt_evt13_exit:
RESTORE_CONTEXT
rti;
.global evt_system_call
evt_system_call:
.global _evt_system_call
_evt_system_call:
[--sp] = r0;
[--SP] = RETI;
r0 = [sp++];
@ -363,7 +218,7 @@ evt_system_call:
r0 = [SP++];
SAVE_CONTEXT
sp += -12;
call display_excp;
call _exception_handle;
sp += 12;
RESTORE_CONTEXT
RTI;
@ -371,8 +226,8 @@ evt_system_call:
evt_system_call_exit:
rti;
.global evt_soft_int1
evt_soft_int1:
.global _evt_soft_int1
_evt_soft_int1:
[--sp] = r0;
[--SP] = RETI;
r0 = [sp++];
@ -382,7 +237,7 @@ evt_soft_int1:
r0 = [SP++];
SAVE_CONTEXT
sp += -12;
call display_excp;
call _exception_handle;
sp += 12;
RESTORE_CONTEXT
RTI;

50
cpu/bf533/interrupts.c
View file

@ -10,7 +10,7 @@
* Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
* Copyright 2003 Metrowerks/Motorola
* Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
* BuyWays B.V. (www.buyways.nl)
* BuyWays B.V. (www.buyways.nl)
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -37,14 +37,15 @@
#include <common.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <asm/cpu/defBF533.h>
#include <config.h>
#include <asm/blackfin.h>
#include "cpu.h"
static ulong timestamp;
static ulong last_time;
static int int_flag;
int irq_flags; /* needed by asm-blackfin/system.h */
int irq_flags; /* needed by asm-blackfin/system.h */
/* Functions just to satisfy the linker */
@ -61,7 +62,7 @@ unsigned long long get_ticks(void)
* This function is derived from PowerPC code (timebase clock frequency).
* On BF533 it returns the number of timer ticks per second.
*/
ulong get_tbclk (void)
ulong get_tbclk(void)
{
ulong tbclk;
@ -91,22 +92,22 @@ void udelay(unsigned long usec)
unsigned long cclk;
cclk = (CONFIG_CCLK_HZ);
while ( usec > 1 ) {
/*
* how many clock ticks to delay?
* - request(in useconds) * clock_ticks(Hz) / useconds/second
*/
while (usec > 1) {
/*
* how many clock ticks to delay?
* - request(in useconds) * clock_ticks(Hz) / useconds/second
*/
if (usec < 1000) {
delay = (usec * (cclk/244)) >> 12 ;
delay = (usec * (cclk / 244)) >> 12;
usec = 0;
} else {
delay = (1000 * (cclk/244)) >> 12 ;
delay = (1000 * (cclk / 244)) >> 12;
usec -= 1000;
}
asm volatile (" %0 = CYCLES;": "=g"(start));
asm volatile (" %0 = CYCLES;":"=r" (start));
do {
asm volatile (" %0 = CYCLES; ": "=g"(stop));
asm volatile (" %0 = CYCLES; ":"=r" (stop));
} while (stop - start < delay);
}
@ -117,7 +118,7 @@ void timer_init(void)
{
*pTCNTL = 0x1;
*pTSCALE = 0x0;
*pTCOUNT = MAX_TIM_LOAD;
*pTCOUNT = MAX_TIM_LOAD;
*pTPERIOD = MAX_TIM_LOAD;
*pTCNTL = 0x7;
asm("CSYNC;");
@ -146,20 +147,23 @@ ulong get_timer(ulong base)
/* Number of clocks elapsed */
ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
/* Find if the TCOUNT is reset
timestamp gives the number of times
TCOUNT got reset */
if(clocks < last_time)
/**
* Find if the TCOUNT is reset
* timestamp gives the number of times
* TCOUNT got reset
*/
if (clocks < last_time)
timestamp++;
last_time = clocks;
/* Get the number of milliseconds */
milisec = clocks/(CONFIG_CCLK_HZ / 1000);
milisec = clocks / (CONFIG_CCLK_HZ / 1000);
/* Find the number of millisonds
that got elapsed before this TCOUNT
cycle */
milisec += timestamp * (MAX_TIM_LOAD/(CONFIG_CCLK_HZ / 1000));
/**
* Find the number of millisonds
* that got elapsed before this TCOUNT cycle
*/
milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
return (milisec - base);
}

80
cpu/bf533/ints.c
View file

@ -51,9 +51,9 @@
void blackfin_irq_panic(int reason, struct pt_regs *regs)
{
printf("\n\nException: IRQ 0x%x entered\n", reason);
printf("code=[0x%x], ", (unsigned int) (regs->seqstat & 0x3f));
printf("stack frame=0x%x, ", (unsigned int) regs);
printf("bad PC=0x%04x\n", (unsigned int) regs->pc);
printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
printf("stack frame=0x%x, ", (unsigned int)regs);
printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
dump(regs);
printf("Unhandled IRQ or exceptions!\n");
printf("Please reset the board \n");
@ -61,46 +61,56 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs)
void blackfin_init_IRQ(void)
{
*(unsigned volatile long *) (SIC_IMASK) = SIC_UNMASK_ALL;
*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
cli();
#ifndef CONFIG_KGDB
*(unsigned volatile long *) (EVT_EMULATION_ADDR) = 0x0;
*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
#endif
*(unsigned volatile long *) (EVT_NMI_ADDR) =
(unsigned volatile long) evt_nmi;
*(unsigned volatile long *) (EVT_EXCEPTION_ADDR) =
(unsigned volatile long) trap;
*(unsigned volatile long *) (EVT_HARDWARE_ERROR_ADDR) =
(unsigned volatile long) evt_ivhw;
*(unsigned volatile long *) (EVT_RESET_ADDR) =
(unsigned volatile long) evt_rst;
*(unsigned volatile long *) (EVT_TIMER_ADDR) =
(unsigned volatile long) evt_timer;
*(unsigned volatile long *) (EVT_IVG7_ADDR) =
(unsigned volatile long) evt_evt7;
*(unsigned volatile long *) (EVT_IVG8_ADDR) =
(unsigned volatile long) evt_evt8;
*(unsigned volatile long *) (EVT_IVG9_ADDR) =
(unsigned volatile long) evt_evt9;
*(unsigned volatile long *) (EVT_IVG10_ADDR) =
(unsigned volatile long) evt_evt10;
*(unsigned volatile long *) (EVT_IVG11_ADDR) =
(unsigned volatile long) evt_evt11;
*(unsigned volatile long *) (EVT_IVG12_ADDR) =
(unsigned volatile long) evt_evt12;
*(unsigned volatile long *) (EVT_IVG13_ADDR) =
(unsigned volatile long) evt_evt13;
*(unsigned volatile long *) (EVT_IVG14_ADDR) =
(unsigned volatile long) evt_system_call;
*(unsigned volatile long *) (EVT_IVG15_ADDR) =
(unsigned volatile long) evt_soft_int1;
*(volatile unsigned long *) ILAT = 0;
*(unsigned volatile long *)(EVT_NMI_ADDR) =
(unsigned volatile long)evt_nmi;
*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
(unsigned volatile long)trap;
*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
(unsigned volatile long)evt_ivhw;
*(unsigned volatile long *)(EVT_RESET_ADDR) =
(unsigned volatile long)evt_rst;
*(unsigned volatile long *)(EVT_TIMER_ADDR) =
(unsigned volatile long)evt_timer;
*(unsigned volatile long *)(EVT_IVG7_ADDR) =
(unsigned volatile long)evt_evt7;
*(unsigned volatile long *)(EVT_IVG8_ADDR) =
(unsigned volatile long)evt_evt8;
*(unsigned volatile long *)(EVT_IVG9_ADDR) =
(unsigned volatile long)evt_evt9;
*(unsigned volatile long *)(EVT_IVG10_ADDR) =
(unsigned volatile long)evt_evt10;
*(unsigned volatile long *)(EVT_IVG11_ADDR) =
(unsigned volatile long)evt_evt11;
*(unsigned volatile long *)(EVT_IVG12_ADDR) =
(unsigned volatile long)evt_evt12;
*(unsigned volatile long *)(EVT_IVG13_ADDR) =
(unsigned volatile long)evt_evt13;
*(unsigned volatile long *)(EVT_IVG14_ADDR) =
(unsigned volatile long)evt_system_call;
*(unsigned volatile long *)(EVT_IVG15_ADDR) =
(unsigned volatile long)evt_soft_int1;
*(volatile unsigned long *)ILAT = 0;
asm("csync;");
sti();
*(volatile unsigned long *) IMASK = 0xffbf;
*(volatile unsigned long *)IMASK = 0xffbf;
asm("csync;");
}
void exception_handle(void)
{
#if defined (CONFIG_PANIC_HANG)
display_excp();
#else
udelay(100000); /* allow messages to go out */
do_reset(NULL, 0, 0, NULL);
#endif
}
void display_excp(void)
{
printf("Exception!\n");

49
cpu/bf533/serial.c
View file

@ -49,6 +49,7 @@
#include <asm/bitops.h>
#include <asm/delay.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include "bf533_serial.h"
DECLARE_GLOBAL_DATA_PTR;
@ -58,15 +59,16 @@ unsigned long pll_div_fact;
void calc_baud(void)
{
unsigned char i;
int temp;
int temp;
u_long sclk = get_sclk();
for(i = 0; i < sizeof(baud_table)/sizeof(int); i++) {
temp = CONFIG_SCLK_HZ/(baud_table[i]*8);
if ( temp && 0x1 == 1 ) {
for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
temp = sclk / (baud_table[i] * 8);
if ((temp & 0x1) == 1) {
temp++;
}
temp = temp/2;
hw_baud_table[i].dl_high = (temp >> 8)& 0xFF;
temp = temp / 2;
hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
hw_baud_table[i].dl_low = (temp) & 0xFF;
}
}
@ -74,6 +76,7 @@ void calc_baud(void)
void serial_setbrg(void)
{
int i;
DECLARE_GLOBAL_DATA_PTR;
calc_baud();
@ -84,29 +87,29 @@ void serial_setbrg(void)
/* Enable UART */
*pUART_GCTL |= UART_GCTL_UCEN;
asm("ssync;");
sync();
/* Set DLAB in LCR to Access DLL and DLH */
ACCESS_LATCH;
asm("ssync;");
sync();
*pUART_DLL = hw_baud_table[i].dl_low;
asm("ssync;");
sync();
*pUART_DLH = hw_baud_table[i].dl_high;
asm("ssync;");
sync();
/* Clear DLAB in LCR to Access THR RBR IER */
ACCESS_PORT_IER;
asm("ssync;");
sync();
/* Enable ERBFI and ELSI interrupts
* to poll SIC_ISR register*/
* to poll SIC_ISR register*/
*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
asm("ssync;");
sync();
/* Set LCR to Word Lengh 8-bit word select */
*pUART_LCR = UART_LCR_WLS8;
asm("ssync;");
sync();
return;
}
@ -119,8 +122,7 @@ int serial_init(void)
void serial_putc(const char c)
{
if ((*pUART_LSR) & UART_LSR_TEMT)
{
if ((*pUART_LSR) & UART_LSR_TEMT) {
if (c == '\n')
serial_putc('\r');
@ -148,17 +150,16 @@ int serial_getc(void)
int ret;
/* Poll for RX Interrupt */
while (!((isr_val = *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT));
while (!((isr_val =
*(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
asm("csync;");
uart_lsr_val = *pUART_LSR; /* Clear status bit */
uart_rbr_val = *pUART_RBR; /* getc() */
if (isr_val & IRQ_UART_ERROR_BIT) {
ret = -1;
}
else
{
ret = -1;
} else {
ret = uart_rbr_val & 0xff;
}
@ -180,10 +181,10 @@ static void local_put_char(char ch)
save_and_cli(flags);
/* Poll for TX Interruput */
while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT));
while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
asm("csync;");
*pUART_THR = ch; /* putc() */
*pUART_THR = ch; /* putc() */
if (isr_val & IRQ_UART_ERROR_BIT) {
printf("?");
@ -191,5 +192,5 @@ static void local_put_char(char ch)
restore_flags(flags);
return ;
return;
}

249
cpu/bf533/start.S
View file

@ -1,5 +1,5 @@
/*
* U-boot - start.S Startup file of u-boot for BF533
* U-boot - start.S Startup file of u-boot for BF533/BF561
*
* Copyright (c) 2005 blackfin.uclinux.org
*
@ -38,9 +38,23 @@
#define ASSEMBLY
#include <linux/config.h>
#include <asm/blackfin.h>
#include <config.h>
#include <asm/mem_init.h>
#include <asm/blackfin.h>
.global _stext;
.global __bss_start;
.global start;
.global _start;
.global _rambase;
.global _ramstart;
.global _ramend;
.global _bf533_data_dest;
.global _bf533_data_size;
.global edata;
.global _initialize;
.global _exit;
.global flashdataend;
.global init_sdram;
#if (CONFIG_CCLK_DIV == 1)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
@ -58,26 +72,12 @@
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
#endif
.global _stext;
.global __bss_start;
.global start;
.global _start;
.global _rambase;
.global _ramstart;
.global _ramend;
.global _bf533_data_dest;
.global _bf533_data_size;
.global edata;
.global _initialize;
.global _exit;
.global flashdataend;
.text
_start:
start:
_stext:
R0 = 0x30;
R0 = 0x32;
SYSCFG = R0;
SSYNC;
@ -120,8 +120,9 @@ _stext:
/* Set loop counters to zero, to make sure that
* hw loops are disabled.
*/
lc0 = 0;
lc1 = 0;
r0 = 0;
lc0 = r0;
lc1 = r0;
SSYNC;
@ -150,105 +151,40 @@ no_soft_reset:
LSETUP(4,4) lc0 = p1;
[ p0 ++ ] = r1;
/*
* Set PLL_CTL
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
* - [7] = output delay (add 200ps of delay to mem signals)
* - [6] = input delay (add 200ps of input delay to mem signals)
* - [5] = PDWN : 1=All Clocks off
* - [3] = STOPCK : 1=Core Clock off
* - [1] = PLL_OFF : 1=Disable Power to PLL
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
* all other bits set to zero
*/
r0 = CONFIG_VCO_MULT; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over */
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */
r0 = r1 | r0;
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
p0.h = (PLL_CTL >> 16);
p0.l = (PLL_CTL & 0xFFFF); /* Load the address */
cli r2; /* Disable interrupts */
w[p0] = r0; /* Set the value */
idle; /* Wait for the PLL to stablize */
sti r2; /* Enable interrupts */
ssync;
/*
* Turn on the CYCLES COUNTER
*/
r2 = SYSCFG;
BITSET (r2,1);
SYSCFG = r2;
/* Configure SCLK & CCLK Dividers */
r0 = CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV;
p0.h = (PLL_DIV >> 16);
p0.l = (PLL_DIV & 0xFFFF);
w[p0] = r0;
ssync;
wait_for_pll_stab:
p0.h = (PLL_STAT >> 16);
p0.l = (PLL_STAT & 0xFFFF);
r0.l = w[p0];
cc = bittst(r0,5);
if !cc jump wait_for_pll_stab;
/* Configure SDRAM if SDRAM is already not enabled */
p0.l = (EBIU_SDSTAT & 0xFFFF);
p0.h = (EBIU_SDSTAT >> 16);
r0.l = w[p0];
cc = bittst(r0, 3);
if !cc jump skip_sdram_enable;
/* SDRAM initialization */
p0.l = (EBIU_SDGCTL & 0xFFFF);
p0.h = (EBIU_SDGCTL >> 16); /* SDRAM Memory Global Control Register */
r0.h = (mem_SDGCTL >> 16);
r0.l = (mem_SDGCTL & 0xFFFF);
[p0] = r0;
ssync;
p0.l = (EBIU_SDBCTL & 0xFFFF);
p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
r0 = mem_SDBCTL;
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
r0.l = 0x1;
w[p0] = r0.l;
ssync;
SSYNC;
p0.l = (EBIU_SDRRC & 0xFFFF);
p0.h = (EBIU_SDRRC >> 16); /* SDRAM Refresh Rate Control Register */
r0 = mem_SDRRC;
w[p0] = r0.l;
ssync;
sp.l = (0xffb01000 & 0xFFFF);
sp.h = (0xffb01000 >> 16);
skip_sdram_enable:
nop;
call init_sdram;
#ifndef CFG_NO_FLASH
/* relocate into to RAM */
p1.l = (CFG_FLASH_BASE & 0xffff);
p1.h = (CFG_FLASH_BASE >> 16);
call get_pc;
offset:
r2.l = offset;
r2.h = offset;
r3.l = start;
r3.h = start;
r1 = r2 - r3;
r0 = r0 - r1;
p1 = r0;
p2.l = (CFG_MONITOR_BASE & 0xffff);
p2.h = (CFG_MONITOR_BASE >> 16);
r0.l = (CFG_MONITOR_LEN & 0xffff);
r0.h = (CFG_MONITOR_LEN >> 16);
p3 = 0x04;
p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
loop1:
r1 = [p1];
[p2] = r1;
p3=0x4;
p1=p1+p3;
p2=p2+p3;
r2=0x4;
r0=r0-r2;
cc=r0==0x0;
r1 = [p1 ++ p3];
[p2 ++ p3] = r1;
cc=p2==p4;
if !cc jump loop1;
#endif
/*
* configure STACK
*/
@ -273,7 +209,8 @@ loop1:
p0.l = (IMASK & 0xFFFF);
p0.h = (IMASK >> 16);
r0 = IVG15_POS;
r0.l = LO(IVG15_POS);
r0.h = HI(IVG15_POS);
[p0] = r0;
raise 15;
p0.l = WAIT_HERE;
@ -288,37 +225,10 @@ WAIT_HERE:
_real_start:
[ -- sp ] = reti;
#ifdef CONFIG_EZKIT533
p0.l = (WDOG_CTL & 0xFFFF);
p0.h = (WDOG_CTL >> 16);
r0 = WATCHDOG_DISABLE(z);
w[p0] = r0;
#endif
/* Code for initializing Async mem banks */
p2.h = (EBIU_AMBCTL1 >> 16);
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
r0.h = (AMBCTL1VAL >> 16);
r0.l = (AMBCTL1VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMBCTL0 >> 16);
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
r0.h = (AMBCTL0VAL >> 16);
r0.l = (AMBCTL0VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMGCTL >> 16);
p2.l = (EBIU_AMGCTL & 0xffff);
r0 = AMGCTLVAL;
w[p2] = r0;
ssync;
/* DMA reset code to Hi of L1 SRAM */
copy:
P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
/* P1 Points to the beginning of SYSTEM MMR Space */
P1.H = hi(SYSMMR_BASE);
P1.L = lo(SYSMMR_BASE);
R0.H = reset_start; /* Source Address (high) */
@ -329,7 +239,8 @@ copy:
R1.H = hi(L1_ISRAM); /* Destination Address (high) */
R1.L = lo(L1_ISRAM); /* Destination Address (low) */
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
/* Destination DMAConfig Value (8-bit words) */
R4.L = (DI_EN | WNR | DMAEN);
DMA:
R6 = 0x1 (Z);
@ -342,57 +253,24 @@ DMA:
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
/* Set Destination Base Address */
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
/* Set Destination DMAConfig = DMA Enable,
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
IDLE; /* Wait for DMA to Complete */
WAIT_DMA_DONE:
p0.h = hi(MDMA_D0_IRQ_STATUS);
p0.l = lo(MDMA_D0_IRQ_STATUS);
R0 = W[P0](Z);
CC = BITTST(R0, 0);
if ! CC jump WAIT_DMA_DONE
R0 = 0x1;
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
/* DMA reset code to DATA BANK A which uses this port
* to avoid following problem
* " Data from a Data Cache fill can be corrupoted after or during
* instruction DMA if certain core stalls exist"
*/
copy_as_data:
R0.H = reset_start; /* Source Address (high) */
R0.L = reset_start; /* Source Address (low) */
R1.H = reset_end;
R1.L = reset_end;
R2 = R1 - R0; /* Count */
R1.H = hi(DATA_BANKA_SRAM); /* Destination Address (high) */
R1.L = lo(DATA_BANKA_SRAM); /* Destination Address (low) */
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
DMA_DATA:
R6 = 0x1 (Z);
W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
/* Set Source DMAConfig = DMA Enable,
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
/* Set Destination DMAConfig = DMA Enable,
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
IDLE; /* Wait for DMA to Complete */
R0 = 0x1;
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
copy_end: nop;
/* Write 1 to clear DMA interrupt */
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;
/* Initialize BSS Section with 0 s */
p1.l = __bss_start;
@ -433,3 +311,6 @@ reset_end: nop;
_exit:
jump.s _exit;
get_pc:
r0 = rets;
rts;

4
cpu/bf533/start1.S
View file

@ -24,8 +24,8 @@
#define ASSEMBLY
#include <linux/config.h>
#include <asm/blackfin.h>
#include <config.h>
#include <asm/blackfin.h>
.global start1;
.global _start1;
@ -34,5 +34,5 @@
_start1:
start1:
sp += -12;
call board_init_f;
call _board_init_f;
sp += 12;

195
cpu/bf533/traps.c
View file

@ -42,6 +42,9 @@
#include <asm/page.h>
#include <asm/machdep.h>
#include "cpu.h"
#include <asm/arch/anomaly.h>
#include <asm/cplb.h>
#include <asm/io.h>
void init_IRQ(void)
{
@ -51,23 +54,187 @@ void init_IRQ(void)
void process_int(unsigned long vec, struct pt_regs *fp)
{
printf("interrupt\n");
return;
}
extern unsigned int icplb_table[page_descriptor_table_size][2];
extern unsigned int dcplb_table[page_descriptor_table_size][2];
unsigned long last_cplb_fault_retx;
static unsigned int cplb_sizes[4] =
{ 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
void trap_c(struct pt_regs *regs)
{
unsigned int addr;
unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
unsigned int i, j, size, *I0, *I1;
unsigned short data = 0;
switch (trapnr) {
/* 0x26 - Data CPLB Miss */
case VEC_CPLB_M:
#ifdef ANOMALY_05000261
/*
* Work around an anomaly: if we see a new DCPLB fault,
* return without doing anything. Then,
* if we get the same fault again, handle it.
*/
addr = last_cplb_fault_retx;
last_cplb_fault_retx = regs->retx;
printf("this time, curr = 0x%08x last = 0x%08x\n",
addr, last_cplb_fault_retx);
if (addr != last_cplb_fault_retx)
goto trap_c_return;
#endif
data = 1;
case VEC_CPLB_I_M:
if (data) {
addr = *(unsigned int *)pDCPLB_FAULT_ADDR;
} else {
addr = *(unsigned int *)pICPLB_FAULT_ADDR;
}
for (i = 0; i < page_descriptor_table_size; i++) {
if (data) {
size = cplb_sizes[dcplb_table[i][1] >> 16];
j = dcplb_table[i][0];
} else {
size = cplb_sizes[icplb_table[i][1] >> 16];
j = icplb_table[i][0];
}
if ((j <= addr) && ((j + size) > addr)) {
debug("found %i 0x%08x\n", i, j);
break;
}
}
if (i == page_descriptor_table_size) {
printf("something is really wrong\n");
do_reset(NULL, 0, 0, NULL);
}
/* Turn the cache off */
if (data) {
sync();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL &=
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
sync();
} else {
sync();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
sync();
}
if (data) {
I0 = (unsigned int *)DCPLB_ADDR0;
I1 = (unsigned int *)DCPLB_DATA0;
} else {
I0 = (unsigned int *)ICPLB_ADDR0;
I1 = (unsigned int *)ICPLB_DATA0;
}
j = 0;
while (*I1 & CPLB_LOCK) {
debug("skipping %i %08p - %08x\n", j, I1, *I1);
*I0++;
*I1++;
j++;
}
debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
for (; j < 15; j++) {
debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
*I0++ = *(I0 + 1);
*I1++ = *(I1 + 1);
}
if (data) {
*I0 = dcplb_table[i][0];
*I1 = dcplb_table[i][1];
I0 = (unsigned int *)DCPLB_ADDR0;
I1 = (unsigned int *)DCPLB_DATA0;
} else {
*I0 = icplb_table[i][0];
*I1 = icplb_table[i][1];
I0 = (unsigned int *)ICPLB_ADDR0;
I1 = (unsigned int *)ICPLB_DATA0;
}
for (j = 0; j < 16; j++) {
debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
}
/* Turn the cache back on */
if (data) {
j = *(unsigned int *)DMEM_CONTROL;
sync();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL =
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
sync();
} else {
sync();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
sync();
}
break;
default:
/* All traps come here */
printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
printf("stack frame=0x%x, ", (unsigned int)regs);
printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
dump(regs);
printf("\n\n");
printf("Unhandled IRQ or exceptions!\n");
printf("Please reset the board \n");
do_reset(NULL, 0, 0, NULL);
}
return;
}
void dump(struct pt_regs *fp)
{
printf("PC: %08lx\n", fp->pc);
printf("SEQSTAT: %08lx SP: %08lx\n", (long) fp->seqstat,
(long) fp);
printf("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
fp->r0, fp->r1, fp->r2, fp->r3);
printf("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
fp->r4, fp->r5, fp->r6, fp->r7);
printf("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
fp->p0, fp->p1, fp->p2, fp->p3);
printf("P4: %08lx P5: %08lx FP: %08lx\n", fp->p4, fp->p5,
fp->fp);
printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
fp->a0w, fp->a0x, fp->a1w, fp->a1x);
printf("\n");
debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n",
fp->rete, fp->retn, fp->retx, fp->rets);
debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
fp->r0, fp->r1, fp->r2, fp->r3);
debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
fp->r4, fp->r5, fp->r6, fp->r7);
debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
fp->p0, fp->p1, fp->p2, fp->p3);
debug("P4: %08lx P5: %08lx FP: %08lx\n",
fp->p4, fp->p5, fp->fp);
debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
fp->a0w, fp->a0x, fp->a1w, fp->a1x);
debug("LB0: %08lx LT0: %08lx LC0: %08lx\n",
fp->lb0, fp->lt0, fp->lc0);
debug("LB1: %08lx LT1: %08lx LC1: %08lx\n",
fp->lb1, fp->lt1, fp->lc1);
debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n",
fp->b0, fp->l0, fp->m0, fp->i0);
debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n",
fp->b1, fp->l1, fp->m1, fp->i1);
debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n",
fp->b2, fp->l2, fp->m2, fp->i2);
debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n",
fp->b3, fp->l3, fp->m3, fp->i3);
debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
}

194
cpu/bf533/video.c Normal file
View file

@ -0,0 +1,194 @@
/*
* (C) Copyright 2000
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
* (C) Copyright 2002
* Wolfgang Denk, wd@denx.de
* (C) Copyright 2006
* Aubrey Li, aubrey.li@analog.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <stdarg.h>
#include <common.h>
#include <config.h>
#include <asm/blackfin.h>
#include <i2c.h>
#include <linux/types.h>
#include <devices.h>
#ifdef CONFIG_VIDEO
#define NTSC_FRAME_ADDR 0x06000000
#include "video.h"
/* NTSC OUTPUT SIZE 720 * 240 */
#define VERTICAL 2
#define HORIZONTAL 4
int is_vblank_line(const int line)
{
/*
* This array contains a single bit for each line in
* an NTSC frame.
*/
if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
return true;
return false;
}
int NTSC_framebuffer_init(char *base_address)
{
const int NTSC_frames = 1;
const int NTSC_lines = 525;
char *dest = base_address;
int frame_num, line_num;
for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
unsigned int code;
int offset = 0;
int i;
if (is_vblank_line(line_num))
offset++;
if (line_num > 266 || line_num < 3)
offset += 2;
/* Output EAV code */
code = SystemCodeMap[offset].EAV;
write_dest_byte((char)(code >> 24) & 0xff);
write_dest_byte((char)(code >> 16) & 0xff);
write_dest_byte((char)(code >> 8) & 0xff);
write_dest_byte((char)(code) & 0xff);
/* Output horizontal blanking */
for (i = 0; i < 67 * 2; ++i) {
write_dest_byte(0x80);
write_dest_byte(0x10);
}
/* Output SAV */
code = SystemCodeMap[offset].SAV;
write_dest_byte((char)(code >> 24) & 0xff);
write_dest_byte((char)(code >> 16) & 0xff);
write_dest_byte((char)(code >> 8) & 0xff);
write_dest_byte((char)(code) & 0xff);
/* Output empty horizontal data */
for (i = 0; i < 360 * 2; ++i) {
write_dest_byte(0x80);
write_dest_byte(0x10);
}
}
}
return dest - base_address;
}
void fill_frame(char *Frame, int Value)
{
int *OddPtr32;
int OddLine;
int *EvenPtr32;
int EvenLine;
int i;
int *data;
int m, n;
/* fill odd and even frames */
for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
*OddPtr32 = Value;
*EvenPtr32 = Value;
}
}
for (m = 0; m < VERTICAL; m++) {
data = (int *)u_boot_logo.data;
for (OddLine = (22 + m), EvenLine = (285 + m);
OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
OddLine += VERTICAL, EvenLine += VERTICAL) {
OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
EvenPtr32 =
(int *)((Frame + ((EvenLine) * 1716)) + 276);
for (i = 0; i < u_boot_logo.width / 2; i++) {
/* enlarge one pixel to m x n */
for (n = 0; n < HORIZONTAL; n++) {
*OddPtr32++ = *data;
*EvenPtr32++ = *data;
}
data++;
}
}
}
}
void video_putc(const char c)
{
}
void video_puts(const char *s)
{
}
static int video_init(void)
{
char *NTSCFrame;
NTSCFrame = (char *)NTSC_FRAME_ADDR;
NTSC_framebuffer_init(NTSCFrame);
fill_frame(NTSCFrame, BLUE);
*pPPI_CONTROL = 0x0082;
*pPPI_FRAME = 0x020D;
*pDMA0_START_ADDR = NTSCFrame;
*pDMA0_X_COUNT = 0x035A;
*pDMA0_X_MODIFY = 0x0002;
*pDMA0_Y_COUNT = 0x020D;
*pDMA0_Y_MODIFY = 0x0002;
*pDMA0_CONFIG = 0x1015;
*pPPI_CONTROL = 0x0083;
return 0;
}
int drv_video_init(void)
{
int error, devices = 1;
device_t videodev;
video_init(); /* Video initialization */
memset(&videodev, 0, sizeof(videodev));
strcpy(videodev.name, "video");
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */
videodev.putc = video_putc; /* 'putc' function */
videodev.puts = video_puts; /* 'puts' function */
error = device_register(&videodev);
return (error == 0) ? devices : error;
}
#endif

25
cpu/bf533/video.h Normal file
View file

@ -0,0 +1,25 @@
#include <video_logo.h>
#define write_dest_byte(val) {*dest++=val;}
#define BLACK (0x01800180) /* black pixel pattern */
#define BLUE (0x296E29F0) /* blue pixel pattern */
#define RED (0x51F0515A) /* red pixel pattern */
#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */
#define GREEN (0x91229136) /* green pixel pattern */
#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
#define YELLOW (0xD292D210) /* yellow pixel pattern */
#define WHITE (0xFE80FE80) /* white pixel pattern */
#define true 1
#define false 0
typedef struct {
unsigned int SAV;
unsigned int EAV;
} SystemCodeType;
const SystemCodeType SystemCodeMap[4] = {
{0xFF000080, 0xFF00009D},
{0xFF0000AB, 0xFF0000B6},
{0xFF0000C7, 0xFF0000DA},
{0xFF0000EC, 0xFF0000F1}
};

52
cpu/bf537/Makefile Normal file
View file

@ -0,0 +1,52 @@
# U-boot - Makefile
#
# Copyright (c) 2005 blackfin.uclinux.org
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o i2c.o
EXTRA = init_sdram_bootrom_initblock.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

128
cpu/bf537/cache.S Normal file
View file

@ -0,0 +1,128 @@
#define ASSEMBLY
#include <asm/linkage.h>
#include <config.h>
#include <asm/blackfin.h>
.text
.align 2
ENTRY(_blackfin_icache_flush_range)
R2 = -32;
R2 = R0 & R2;
P0 = R2;
P1 = R1;
CSYNC;
1:
IFLUSH[P0++];
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
IFLUSH[P0];
SSYNC;
RTS;
ENTRY(_blackfin_dcache_flush_range)
R2 = -32;
R2 = R0 & R2;
P0 = R2;
P1 = R1;
CSYNC;
1:
FLUSH[P0++];
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
FLUSH[P0];
SSYNC;
RTS;
ENTRY(_icache_invalidate)
ENTRY(_invalidate_entire_icache)
[--SP] = (R7:5);
P0.L = (IMEM_CONTROL & 0xFFFF);
P0.H = (IMEM_CONTROL >> 16);
R7 =[P0];
/*
* Clear the IMC bit , All valid bits in the instruction
* cache are set to the invalid state
*/
BITCLR(R7, IMC_P);
CLI R6;
/* SSYNC required before invalidating cache. */
SSYNC;
.align 8;
[P0] = R7;
SSYNC;
STI R6;
/* Configures the instruction cache agian */
R6 = (IMC | ENICPLB);
R7 = R7 | R6;
CLI R6;
SSYNC;
.align 8;
[P0] = R7;
SSYNC;
STI R6;
(R7:5) =[SP++];
RTS;
/*
* Invalidate the Entire Data cache by
* clearing DMC[1:0] bits
*/
ENTRY(_invalidate_entire_dcache)
ENTRY(_dcache_invalidate)
[--SP] = (R7:6);
P0.L = (DMEM_CONTROL & 0xFFFF);
P0.H = (DMEM_CONTROL >> 16);
R7 =[P0];
/*
* Clear the DMC[1:0] bits, All valid bits in the data
* cache are set to the invalid state
*/
BITCLR(R7, DMC0_P);
BITCLR(R7, DMC1_P);
CLI R6;
SSYNC;
.align 8;
[P0] = R7;
SSYNC;
STI R6;
/* Configures the data cache again */
R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
R7 = R7 | R6;
CLI R6;
SSYNC;
.align 8;
[P0] = R7;
SSYNC;
STI R6;
(R7:6) =[SP++];
RTS;
ENTRY(_blackfin_dcache_invalidate_range)
R2 = -32;
R2 = R0 & R2;
P0 = R2;
P1 = R1;
CSYNC;
1:
FLUSHINV[P0++];
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
/*
* If the data crosses a cache line, then we'll be pointing to
* the last cache line, but won't have flushed/invalidated it yet, so do
* one more.
*/
FLUSHINV[P0];
SSYNC;
RTS;

16
post/cpu/Makefile → cpu/bf537/config.mk
View file

@ -1,5 +1,8 @@
# U-boot - config.mk
#
# (C) Copyright 2002-2006
# Copyright (c) 2005 blackfin.uclinux.org
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -21,13 +24,4 @@
# MA 02111-1307 USA
#
SUBDIRS =
LIB = libcpu.a
AOBJS = asm.o
COBJS = cmp.o cmpi.o two.o twox.o three.o threex.o
COBJS += threei.o andi.o srawi.o rlwnm.o rlwinm.o rlwimi.o
COBJS += store.o load.o cr.o b.o multi.o string.o complex.o
include $(TOPDIR)/post/rules.mk
PLATFORM_RELFLAGS += -mcpu=bf537 -ffixed-P5

227
cpu/bf537/cpu.c Normal file
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@ -0,0 +1,227 @@
/*
* U-boot - cpu.c CPU specific functions
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/blackfin.h>
#include <command.h>
#include <asm/entry.h>
#include <asm/cplb.h>
#include <asm/io.h>
#define CACHE_ON 1
#define CACHE_OFF 0
extern unsigned int icplb_table[page_descriptor_table_size][2];
extern unsigned int dcplb_table[page_descriptor_table_size][2];
int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
);
return 0;
}
/* These functions are just used to satisfy the linker */
int cpu_init(void)
{
return 0;
}
int cleanup_before_linux(void)
{
return 0;
}
void icache_enable(void)
{
unsigned int *I0, *I1;
int i, j = 0;
if ((*pCHIPID >> 28) < 2)
return;
/* Before enable icache, disable it first */
icache_disable();
I0 = (unsigned int *)ICPLB_ADDR0;
I1 = (unsigned int *)ICPLB_DATA0;
/* make sure the locked ones go in first */
for (i = 0; i < page_descriptor_table_size; i++) {
if (CPLB_LOCK & icplb_table[i][1]) {
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
icplb_table[i][0], icplb_table[i][1]);
*I0++ = icplb_table[i][0];
*I1++ = icplb_table[i][1];
j++;
}
}
for (i = 0; i < page_descriptor_table_size; i++) {
if (!(CPLB_LOCK & icplb_table[i][1])) {
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
icplb_table[i][0], icplb_table[i][1]);
*I0++ = icplb_table[i][0];
*I1++ = icplb_table[i][1];
j++;
if (j == 16) {
break;
}
}
}
/* Fill the rest with invalid entry */
if (j <= 15) {
for (; j < 16; j++) {
debug("filling %i with 0", j);
*I1++ = 0x0;
}
}
cli();
sync();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
sync();
sti();
}
void icache_disable(void)
{
if ((*pCHIPID >> 28) < 2)
return;
cli();
sync();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
sync();
sti();
}
int icache_status(void)
{
unsigned int value;
value = *(unsigned int *)IMEM_CONTROL;
if (value & (IMC | ENICPLB))
return CACHE_ON;
else
return CACHE_OFF;
}
void dcache_enable(void)
{
unsigned int *I0, *I1;
unsigned int temp;
int i, j = 0;
/* Before enable dcache, disable it first */
dcache_disable();
I0 = (unsigned int *)DCPLB_ADDR0;
I1 = (unsigned int *)DCPLB_DATA0;
/* make sure the locked ones go in first */
for (i = 0; i < page_descriptor_table_size; i++) {
if (CPLB_LOCK & dcplb_table[i][1]) {
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
dcplb_table[i][0], dcplb_table[i][1]);
*I0++ = dcplb_table[i][0];
*I1++ = dcplb_table[i][1];
j++;
} else {
debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
dcplb_table[i][0], dcplb_table[i][1]);
}
}
for (i = 0; i < page_descriptor_table_size; i++) {
if (!(CPLB_LOCK & dcplb_table[i][1])) {
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
dcplb_table[i][0], dcplb_table[i][1]);
*I0++ = dcplb_table[i][0];
*I1++ = dcplb_table[i][1];
j++;
if (j == 16) {
break;
}
}
}
/* Fill the rest with invalid entry */
if (j <= 15) {
for (; j < 16; j++) {
debug("filling %i with 0", j);
*I1++ = 0x0;
}
}
cli();
temp = *(unsigned int *)DMEM_CONTROL;
sync();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL =
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
sync();
sti();
}
void dcache_disable(void)
{
unsigned int *I0, *I1;
int i;
cli();
sync();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL &=
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
sync();
sti();
/* after disable dcache,
* clear it so we don't confuse the next application
*/
I0 = (unsigned int *)DCPLB_ADDR0;
I1 = (unsigned int *)DCPLB_DATA0;
for (i = 0; i < 16; i++) {
*I0++ = 0x0;
*I1++ = 0x0;
}
}
int dcache_status(void)
{
unsigned int value;
value = *(unsigned int *)DMEM_CONTROL;
if (value & (ENDCPLB))
return CACHE_ON;
else
return CACHE_OFF;
}

66
cpu/bf537/cpu.h Normal file
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@ -0,0 +1,66 @@
/*
* U-boot - cpu.h
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _CPU_H_
#define _CPU_H_
#include <command.h>
#define INTERNAL_IRQS (32)
#define NUM_IRQ_NODES 16
#define DEF_INTERRUPT_FLAGS 1
#define MAX_TIM_LOAD 0xFFFFFFFF
void blackfin_irq_panic(int reason, struct pt_regs *reg);
extern void dump(struct pt_regs *regs);
void display_excp(void);
asmlinkage void evt_nmi(void);
asmlinkage void evt_exception(void);
asmlinkage void trap(void);
asmlinkage void evt_ivhw(void);
asmlinkage void evt_rst(void);
asmlinkage void evt_timer(void);
asmlinkage void evt_evt7(void);
asmlinkage void evt_evt8(void);
asmlinkage void evt_evt9(void);
asmlinkage void evt_evt10(void);
asmlinkage void evt_evt11(void);
asmlinkage void evt_evt12(void);
asmlinkage void evt_evt13(void);
asmlinkage void evt_soft_int1(void);
asmlinkage void evt_system_call(void);
void blackfin_irq_panic(int reason, struct pt_regs *regs);
void blackfin_free_irq(unsigned int irq, void *dev_id);
void call_isr(int irq, struct pt_regs *fp);
void blackfin_do_irq(int vec, struct pt_regs *fp);
void blackfin_init_IRQ(void);
void blackfin_enable_irq(unsigned int irq);
void blackfin_disable_irq(unsigned int irq);
extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
int blackfin_request_irq(unsigned int irq,
void (*handler) (int, void *, struct pt_regs *),
unsigned long flags, const char *devname,
void *dev_id);
void timer_init(void);
#endif

403
cpu/bf537/flush.S Normal file
View file

@ -0,0 +1,403 @@
/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
* Copyright (C) 2004 LG SOft India. All Rights Reserved.
*
* This file is subject to the terms and conditions of the GNU General Public
* License.
*/
#define ASSEMBLY
#include <asm/linkage.h>
#include <asm/cplb.h>
#include <config.h>
#include <asm/blackfin.h>
.text
/* This is an external function being called by the user
* application through __flush_cache_all. Currently this function
* serves the purpose of flushing all the pending writes in
* in the instruction cache.
*/
ENTRY(_flush_instruction_cache)
[--SP] = ( R7:6, P5:4 );
LINK 12;
SP += -12;
P5.H = (ICPLB_ADDR0 >> 16);
P5.L = (ICPLB_ADDR0 & 0xFFFF);
P4.H = (ICPLB_DATA0 >> 16);
P4.L = (ICPLB_DATA0 & 0xFFFF);
R7 = CPLB_VALID | CPLB_L1_CHBL;
R6 = 16;
inext: R0 = [P5++];
R1 = [P4++];
[--SP] = RETS;
CALL _icplb_flush; /* R0 = page, R1 = data*/
RETS = [SP++];
iskip: R6 += -1;
CC = R6;
IF CC JUMP inext;
SSYNC;
SP += 12;
UNLINK;
( R7:6, P5:4 ) = [SP++];
RTS;
/* This is an internal function to flush all pending
* writes in the cache associated with a particular ICPLB.
*
* R0 - page's start address
* R1 - CPLB's data field.
*/
.align 2
ENTRY(_icplb_flush)
[--SP] = ( R7:0, P5:0 );
[--SP] = LC0;
[--SP] = LT0;
[--SP] = LB0;
[--SP] = LC1;
[--SP] = LT1;
[--SP] = LB1;
/* If it's a 1K or 4K page, then it's quickest to
* just systematically flush all the addresses in
* the page, regardless of whether they're in the
* cache, or dirty. If it's a 1M or 4M page, there
* are too many addresses, and we have to search the
* cache for lines corresponding to the page.
*/
CC = BITTST(R1, 17); /* 1MB or 4MB */
IF !CC JUMP iflush_whole_page;
/* We're only interested in the page's size, so extract
* this from the CPLB (bits 17:16), and scale to give an
* offset into the page_size and page_prefix tables.
*/
R1 <<= 14;
R1 >>= 30;
R1 <<= 2;
/* We can also determine the sub-bank used, because this is
* taken from bits 13:12 of the address.
*/
R3 = ((12<<8)|2); /* Extraction pattern */
nop; /* Anamoly 05000209 */
R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits */
/* Save in extraction pattern for later deposit. */
R3.H = R4.L << 0;
/* So:
* R0 = Page start
* R1 = Page length (actually, offset into size/prefix tables)
* R3 = sub-bank deposit values
*
* The cache has 2 Ways, and 64 sets, so we iterate through
* the sets, accessing the tag for each Way, for our Bank and
* sub-bank, looking for dirty, valid tags that match our
* address prefix.
*/
P5.L = (ITEST_COMMAND & 0xFFFF);
P5.H = (ITEST_COMMAND >> 16);
P4.L = (ITEST_DATA0 & 0xFFFF);
P4.H = (ITEST_DATA0 >> 16);
P0.L = page_prefix_table;
P0.H = page_prefix_table;
P1 = R1;
R5 = 0; /* Set counter*/
P0 = P1 + P0;
R4 = [P0]; /* This is the address prefix*/
/* We're reading (bit 1==0) the tag (bit 2==0), and we
* don't care about which double-word, since we're only
* fetching tags, so we only have to set Set, Bank,
* Sub-bank and Way.
*/
P2 = 4;
LSETUP (ifs1, ife1) LC1 = P2;
ifs1: P0 = 32; /* iterate over all sets*/
LSETUP (ifs0, ife0) LC0 = P0;
ifs0: R6 = R5 << 5; /* Combine set*/
R6.H = R3.H << 0 ; /* and sub-bank*/
[P5] = R6; /* Issue Command*/
SSYNC; /* CSYNC will not work here :(*/
R7 = [P4]; /* and read Tag.*/
CC = BITTST(R7, 0); /* Check if valid*/
IF !CC JUMP ifskip; /* and skip if not.*/
/* Compare against the page address. First, plant bits 13:12
* into the tag, since those aren't part of the returned data.
*/
R7 = DEPOSIT(R7, R3); /* set 13:12*/
R1 = R7 & R4; /* Mask off lower bits*/
CC = R1 == R0; /* Compare against page start.*/
IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/
/* Tag address matches against page, so this is an entry
* we must flush.
*/
R7 >>= 10; /* Mask off the non-address bits*/
R7 <<= 10;
P3 = R7;
IFLUSH [P3]; /* And flush the entry*/
ifskip:
ife0: R5 += 1; /* Advance to next Set*/
ife1: NOP;
ifinished:
SSYNC; /* Ensure the data gets out to mem.*/
/*Finished. Restore context.*/
LB1 = [SP++];
LT1 = [SP++];
LC1 = [SP++];
LB0 = [SP++];
LT0 = [SP++];
LC0 = [SP++];
( R7:0, P5:0 ) = [SP++];
RTS;
iflush_whole_page:
/* It's a 1K or 4K page, so quicker to just flush the
* entire page.
*/
P1 = 32; /* For 1K pages*/
P2 = P1 << 2; /* For 4K pages*/
P0 = R0; /* Start of page*/
CC = BITTST(R1, 16); /* Whether 1K or 4K*/
IF CC P1 = P2;
P1 += -1; /* Unroll one iteration*/
SSYNC;
IFLUSH [P0++]; /* because CSYNC can't end loops.*/
LSETUP (isall, ieall) LC0 = P1;
isall:IFLUSH [P0++];
ieall: NOP;
SSYNC;
JUMP ifinished;
/* This is an external function being called by the user
* application through __flush_cache_all. Currently this function
* serves the purpose of flushing all the pending writes in
* in the data cache.
*/
ENTRY(_flush_data_cache)
[--SP] = ( R7:6, P5:4 );
LINK 12;
SP += -12;
P5.H = (DCPLB_ADDR0 >> 16);
P5.L = (DCPLB_ADDR0 & 0xFFFF);
P4.H = (DCPLB_DATA0 >> 16);
P4.L = (DCPLB_DATA0 & 0xFFFF);
R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
R6 = 16;
next: R0 = [P5++];
R1 = [P4++];
CC = BITTST(R1, 14); /* Is it write-through?*/
IF CC JUMP skip; /* If so, ignore it.*/
R2 = R1 & R7; /* Is it a dirty, cached page?*/
CC = R2;
IF !CC JUMP skip; /* If not, ignore it.*/
[--SP] = RETS;
CALL _dcplb_flush; /* R0 = page, R1 = data*/
RETS = [SP++];
skip: R6 += -1;
CC = R6;
IF CC JUMP next;
SSYNC;
SP += 12;
UNLINK;
( R7:6, P5:4 ) = [SP++];
RTS;
/* This is an internal function to flush all pending
* writes in the cache associated with a particular DCPLB.
*
* R0 - page's start address
* R1 - CPLB's data field.
*/
.align 2
ENTRY(_dcplb_flush)
[--SP] = ( R7:0, P5:0 );
[--SP] = LC0;
[--SP] = LT0;
[--SP] = LB0;
[--SP] = LC1;
[--SP] = LT1;
[--SP] = LB1;
/* If it's a 1K or 4K page, then it's quickest to
* just systematically flush all the addresses in
* the page, regardless of whether they're in the
* cache, or dirty. If it's a 1M or 4M page, there
* are too many addresses, and we have to search the
* cache for lines corresponding to the page.
*/
CC = BITTST(R1, 17); /* 1MB or 4MB */
IF !CC JUMP dflush_whole_page;
/* We're only interested in the page's size, so extract
* this from the CPLB (bits 17:16), and scale to give an
* offset into the page_size and page_prefix tables.
*/
R1 <<= 14;
R1 >>= 30;
R1 <<= 2;
/* The page could be mapped into Bank A or Bank B, depending
* on (a) whether both banks are configured as cache, and
* (b) on whether address bit A[x] is set. x is determined
* by DCBS in DMEM_CONTROL
*/
R2 = 0; /* Default to Bank A (Bank B would be 1)*/
P0.L = (DMEM_CONTROL & 0xFFFF);
P0.H = (DMEM_CONTROL >> 16);
R3 = [P0]; /* If Bank B is not enabled as cache*/
CC = BITTST(R3, 2); /* then Bank A is our only option.*/
IF CC JUMP bank_chosen;
R4 = 1<<14; /* If DCBS==0, use A[14].*/
R5 = R4 << 7; /* If DCBS==1, use A[23];*/
CC = BITTST(R3, 4);
IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
R5 = R0 & R4; /* Use it to test the Page address*/
CC = R5; /* and if that bit is set, we use Bank B,*/
R2 = CC; /* else we use Bank A.*/
R2 <<= 23; /* The Bank selection's at posn 23.*/
bank_chosen:
/* We can also determine the sub-bank used, because this is
* taken from bits 13:12 of the address.
*/
R3 = ((12<<8)|2); /* Extraction pattern */
nop; /*Anamoly 05000209*/
R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
/* Save in extraction pattern for later deposit.*/
R3.H = R4.L << 0;
/* So:
* R0 = Page start
* R1 = Page length (actually, offset into size/prefix tables)
* R2 = Bank select mask
* R3 = sub-bank deposit values
*
* The cache has 2 Ways, and 64 sets, so we iterate through
* the sets, accessing the tag for each Way, for our Bank and
* sub-bank, looking for dirty, valid tags that match our
* address prefix.
*/
P5.L = (DTEST_COMMAND & 0xFFFF);
P5.H = (DTEST_COMMAND >> 16);
P4.L = (DTEST_DATA0 & 0xFFFF);
P4.H = (DTEST_DATA0 >> 16);
P0.L = page_prefix_table;
P0.H = page_prefix_table;
P1 = R1;
R5 = 0; /* Set counter*/
P0 = P1 + P0;
R4 = [P0]; /* This is the address prefix*/
/* We're reading (bit 1==0) the tag (bit 2==0), and we
* don't care about which double-word, since we're only
* fetching tags, so we only have to set Set, Bank,
* Sub-bank and Way.
*/
P2 = 2;
LSETUP (fs1, fe1) LC1 = P2;
fs1: P0 = 64; /* iterate over all sets*/
LSETUP (fs0, fe0) LC0 = P0;
fs0: R6 = R5 << 5; /* Combine set*/
R6.H = R3.H << 0 ; /* and sub-bank*/
R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
BITSET(R6,14);
[P5] = R6; /* Issue Command*/
SSYNC;
R7 = [P4]; /* and read Tag.*/
CC = BITTST(R7, 0); /* Check if valid*/
IF !CC JUMP fskip; /* and skip if not.*/
CC = BITTST(R7, 1); /* Check if dirty*/
IF !CC JUMP fskip; /* and skip if not.*/
/* Compare against the page address. First, plant bits 13:12
* into the tag, since those aren't part of the returned data.
*/
R7 = DEPOSIT(R7, R3); /* set 13:12*/
R1 = R7 & R4; /* Mask off lower bits*/
CC = R1 == R0; /* Compare against page start.*/
IF !CC JUMP fskip; /* Skip it if it doesn't match.*/
/* Tag address matches against page, so this is an entry
* we must flush.
*/
R7 >>= 10; /* Mask off the non-address bits*/
R7 <<= 10;
P3 = R7;
SSYNC;
FLUSHINV [P3]; /* And flush the entry*/
fskip:
fe0: R5 += 1; /* Advance to next Set*/
fe1: BITSET(R2, 26); /* Go to next Way.*/
dfinished:
SSYNC; /* Ensure the data gets out to mem.*/
/*Finished. Restore context.*/
LB1 = [SP++];
LT1 = [SP++];
LC1 = [SP++];
LB0 = [SP++];
LT0 = [SP++];
LC0 = [SP++];
( R7:0, P5:0 ) = [SP++];
RTS;
dflush_whole_page:
/* It's a 1K or 4K page, so quicker to just flush the
* entire page.
*/
P1 = 32; /* For 1K pages*/
P2 = P1 << 2; /* For 4K pages*/
P0 = R0; /* Start of page*/
CC = BITTST(R1, 16); /* Whether 1K or 4K*/
IF CC P1 = P2;
P1 += -1; /* Unroll one iteration*/
SSYNC;
FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
LSETUP (eall, eall) LC0 = P1;
eall: FLUSHINV [P0++];
SSYNC;
JUMP dfinished;
.align 4;
page_prefix_table:
.byte4 0xFFFFFC00; /* 1K */
.byte4 0xFFFFF000; /* 4K */
.byte4 0xFFF00000; /* 1M */
.byte4 0xFFC00000; /* 4M */
.page_prefix_table.end:

460
cpu/bf537/i2c.c Normal file
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@ -0,0 +1,460 @@
/****************************************************************
* $ID: i2c.c 24 Oct 2006 12:00:00 +0800 $ *
* *
* Description: *
* *
* Maintainer: sonicz <sonic.zhang@analog.com> *
* *
* CopyRight (c) 2006 Analog Device *
* All rights reserved. *
* *
* This file is free software; *
* you are free to modify and/or redistribute it *
* under the terms of the GNU General Public Licence (GPL).*
* *
****************************************************************/
#include <common.h>
#ifdef CONFIG_HARD_I2C
#include <asm/blackfin.h>
#include <i2c.h>
#include <asm/io.h>
#define bfin_read16(addr) ({ unsigned __v; \
__asm__ __volatile__ (\
"%0 = w[%1] (z);\n\t"\
: "=d"(__v) : "a"(addr)); (unsigned short)__v; })
#define bfin_write16(addr,val) ({\
__asm__ __volatile__ (\
"w[%0] = %1;\n\t"\
: : "a"(addr) , "d"(val) : "memory");})
/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val)
#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val)
#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val)
#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val)
#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val)
#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val)
#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val)
#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val)
#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val)
#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val)
#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val)
#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val)
#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val)
#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val)
#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val)
#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val)
#ifdef DEBUG_I2C
#define PRINTD(fmt,args...) do { \
DECLARE_GLOBAL_DATA_PTR; \
if (gd->have_console) \
printf(fmt ,##args); \
} while (0)
#else
#define PRINTD(fmt,args...)
#endif
#ifndef CONFIG_TWICLK_KHZ
#define CONFIG_TWICLK_KHZ 50
#endif
/* All transfers are described by this data structure */
struct i2c_msg {
u16 addr; /* slave address */
u16 flags;
#define I2C_M_STOP 0x2
#define I2C_M_RD 0x1
u16 len; /* msg length */
u8 *buf; /* pointer to msg data */
};
/**
* i2c_reset: - reset the host controller
*
*/
static void i2c_reset(void)
{
/* Disable TWI */
bfin_write_TWI_CONTROL(0);
sync();
/* Set TWI internal clock as 10MHz */
bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
/* Set Twi interface clock as specified */
if (CONFIG_TWICLK_KHZ > 400)
bfin_write_TWI_CLKDIV(((5 * 1024 / 400) << 8) | ((5 * 1024 /
400) & 0xFF));
else
bfin_write_TWI_CLKDIV(((5 * 1024 /
CONFIG_TWICLK_KHZ) << 8) | ((5 * 1024 /
CONFIG_TWICLK_KHZ)
& 0xFF));
/* Enable TWI */
bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA);
sync();
}
int wait_for_completion(struct i2c_msg *msg, int timeout_count)
{
unsigned short twi_int_stat;
unsigned short mast_stat;
int i;
for (i = 0; i < timeout_count; i++) {
twi_int_stat = bfin_read_TWI_INT_STAT();
mast_stat = bfin_read_TWI_MASTER_STAT();
if (XMTSERV & twi_int_stat) {
/* Transmit next data */
if (msg->len > 0) {
bfin_write_TWI_XMT_DATA8(*(msg->buf++));
msg->len--;
} else if (msg->flags & I2C_M_STOP)
bfin_write_TWI_MASTER_CTL
(bfin_read_TWI_MASTER_CTL() | STOP);
sync();
/* Clear status */
bfin_write_TWI_INT_STAT(XMTSERV);
sync();
i = 0;
}
if (RCVSERV & twi_int_stat) {
if (msg->len > 0) {
/* Receive next data */
*(msg->buf++) = bfin_read_TWI_RCV_DATA8();
msg->len--;
} else if (msg->flags & I2C_M_STOP) {
bfin_write_TWI_MASTER_CTL
(bfin_read_TWI_MASTER_CTL() | STOP);
sync();
}
/* Clear interrupt source */
bfin_write_TWI_INT_STAT(RCVSERV);
sync();
i = 0;
}
if (MERR & twi_int_stat) {
bfin_write_TWI_INT_STAT(MERR);
bfin_write_TWI_INT_MASK(0);
bfin_write_TWI_MASTER_STAT(0x3e);
bfin_write_TWI_MASTER_CTL(0);
sync();
/*
* if both err and complete int stats are set,
* return proper results.
*/
if (MCOMP & twi_int_stat) {
bfin_write_TWI_INT_STAT(MCOMP);
bfin_write_TWI_INT_MASK(0);
bfin_write_TWI_MASTER_CTL(0);
sync();
/*
* If it is a quick transfer,
* only address bug no data, not an err.
*/
if (msg->len == 0 && mast_stat & BUFRDERR)
return 0;
/*
* If address not acknowledged return -3,
* else return 0.
*/
else if (!(mast_stat & ANAK))
return 0;
else
return -3;
}
return -1;
}
if (MCOMP & twi_int_stat) {
bfin_write_TWI_INT_STAT(MCOMP);
sync();
bfin_write_TWI_INT_MASK(0);
bfin_write_TWI_MASTER_CTL(0);
sync();
return 0;
}
}
if (msg->flags & I2C_M_RD)
return -4;
else
return -2;
}
/**
* i2c_transfer: - Transfer one byte over the i2c bus
*
* This function can tranfer a byte over the i2c bus in both directions.
* It is used by the public API functions.
*
* @return: 0: transfer successful
* -1: transfer fail
* -2: transmit timeout
* -3: ACK missing
* -4: receive timeout
* -5: controller not ready
*/
int i2c_transfer(struct i2c_msg *msg)
{
int ret = 0;
int timeout_count = 10000;
int len = msg->len;
if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) {
ret = -5;
goto transfer_error;
}
while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) ;
/* Set Transmit device address */
bfin_write_TWI_MASTER_ADDR(msg->addr);
/*
* FIFO Initiation.
* Data in FIFO should be discarded before start a new operation.
*/
bfin_write_TWI_FIFO_CTL(0x3);
sync();
bfin_write_TWI_FIFO_CTL(0);
sync();
if (!(msg->flags & I2C_M_RD)) {
/* Transmit first data */
if (msg->len > 0) {
PRINTD("1 in i2c_transfer: buf=%d, len=%d\n", *msg->buf,
len);
bfin_write_TWI_XMT_DATA8(*(msg->buf++));
msg->len--;
sync();
}
}
/* clear int stat */
bfin_write_TWI_INT_STAT(MERR | MCOMP | XMTSERV | RCVSERV);
/* Interrupt mask . Enable XMT, RCV interrupt */
bfin_write_TWI_INT_MASK(MCOMP | MERR |
((msg->flags & I2C_M_RD) ? RCVSERV : XMTSERV));
sync();
if (len > 0 && len <= 255)
bfin_write_TWI_MASTER_CTL((len << 6));
else if (msg->len > 255) {
bfin_write_TWI_MASTER_CTL((0xff << 6));
msg->flags &= I2C_M_STOP;
} else
bfin_write_TWI_MASTER_CTL(0);
/* Master enable */
bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN |
((msg->flags & I2C_M_RD)
? MDIR : 0) | ((CONFIG_TWICLK_KHZ >
100) ? FAST : 0));
sync();
ret = wait_for_completion(msg, timeout_count);
PRINTD("3 in i2c_transfer: ret=%d\n", ret);
transfer_error:
switch (ret) {
case 1:
PRINTD(("i2c_transfer: error: transfer fail\n"));
break;
case 2:
PRINTD(("i2c_transfer: error: transmit timeout\n"));
break;
case 3:
PRINTD(("i2c_transfer: error: ACK missing\n"));
break;
case 4:
PRINTD(("i2c_transfer: error: receive timeout\n"));
break;
case 5:
PRINTD(("i2c_transfer: error: controller not ready\n"));
i2c_reset();
break;
default:
break;
}
return ret;
}
/* ---------------------------------------------------------------------*/
/* API Functions */
/* ---------------------------------------------------------------------*/
void i2c_init(int speed, int slaveaddr)
{
i2c_reset();
}
/**
* i2c_probe: - Test if a chip answers for a given i2c address
*
* @chip: address of the chip which is searched for
* @return: 0 if a chip was found, -1 otherwhise
*/
int i2c_probe(uchar chip)
{
struct i2c_msg msg;
u8 probebuf;
i2c_reset();
probebuf = 0;
msg.addr = chip;
msg.flags = 0;
msg.len = 1;
msg.buf = &probebuf;
if (i2c_transfer(&msg))
return -1;
msg.addr = chip;
msg.flags = I2C_M_RD;
msg.len = 1;
msg.buf = &probebuf;
if (i2c_transfer(&msg))
return -1;
return 0;
}
/**
* i2c_read: - Read multiple bytes from an i2c device
*
* chip: I2C chip address, range 0..127
* addr: Memory (register) address within the chip
* alen: Number of bytes to use for addr (typically 1, 2 for larger
* memories, 0 for register type devices with only one
* register)
* buffer: Where to read/write the data
* len: How many bytes to read/write
*
* Returns: 0 on success, not 0 on failure
*/
int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
{
struct i2c_msg msg;
u8 addr_bytes[3]; /* lowest...highest byte of data address */
PRINTD("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x\n", chip,
addr, alen, len);
if (alen > 0) {
addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
msg.addr = chip;
msg.flags = 0;
msg.len = alen;
msg.buf = addr_bytes;
if (i2c_transfer(&msg))
return -1;
}
/* start read sequence */
PRINTD(("i2c_read: start read sequence\n"));
msg.addr = chip;
msg.flags = I2C_M_RD;
msg.len = len;
msg.buf = buffer;
if (i2c_transfer(&msg))
return -1;
return 0;
}
/**
* i2c_write: - Write multiple bytes to an i2c device
*
* chip: I2C chip address, range 0..127
* addr: Memory (register) address within the chip
* alen: Number of bytes to use for addr (typically 1, 2 for larger
* memories, 0 for register type devices with only one
* register)
* buffer: Where to read/write the data
* len: How many bytes to read/write
*
* Returns: 0 on success, not 0 on failure
*/
int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
{
struct i2c_msg msg;
u8 addr_bytes[3]; /* lowest...highest byte of data address */
PRINTD
("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x, buf0=0x%x\n",
chip, addr, alen, len, buffer[0]);
/* chip address write */
if (alen > 0) {
addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF);
addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF);
addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF);
msg.addr = chip;
msg.flags = 0;
msg.len = alen;
msg.buf = addr_bytes;
if (i2c_transfer(&msg))
return -1;
}
/* start read sequence */
PRINTD(("i2c_write: start write sequence\n"));
msg.addr = chip;
msg.flags = 0;
msg.len = len;
msg.buf = buffer;
if (i2c_transfer(&msg))
return -1;
return 0;
}
uchar i2c_reg_read(uchar chip, uchar reg)
{
uchar buf;
PRINTD("i2c_reg_read: chip=0x%02x, reg=0x%02x\n", chip, reg);
i2c_read(chip, reg, 0, &buf, 1);
return (buf);
}
void i2c_reg_write(uchar chip, uchar reg, uchar val)
{
PRINTD("i2c_reg_write: chip=0x%02x, reg=0x%02x, val=0x%02x\n", chip,
reg, val);
i2c_write(chip, reg, 0, &val, 1);
}
#endif /* CONFIG_HARD_I2C */

174
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#define ASSEMBLY
#include <linux/config.h>
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mem_init.h>
.global init_sdram;
#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
#if (CONFIG_CCLK_DIV == 1)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
#endif
#if (CONFIG_CCLK_DIV == 2)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
#endif
#if (CONFIG_CCLK_DIV == 4)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
#endif
#if (CONFIG_CCLK_DIV == 8)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
#endif
#ifndef CONFIG_CCLK_ACT_DIV
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
#endif
#endif
init_sdram:
[--SP] = ASTAT;
[--SP] = RETS;
[--SP] = (R7:0);
[--SP] = (P5:0);
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
r0.l = 0x1;
w[p0] = r0.l;
SSYNC;
p0.h = hi(SPI_BAUD);
p0.l = lo(SPI_BAUD);
r0.l = CONFIG_SPI_BAUD;
w[p0] = r0.l;
SSYNC;
#endif
#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
#ifdef CONFIG_BF537
/* Enable PHY CLK buffer output */
p0.h = hi(VR_CTL);
p0.l = lo(VR_CTL);
r0.l = w[p0];
bitset(r0, 14);
w[p0] = r0.l;
ssync;
#endif
/*
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
*/
p0.h = hi(PLL_LOCKCNT);
p0.l = lo(PLL_LOCKCNT);
r0 = 0x300(Z);
w[p0] = r0.l;
ssync;
/*
* Put SDRAM in self-refresh, incase anything is running
*/
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITSET (R0, 24);
[P2] = R0;
SSYNC;
/*
* Set PLL_CTL with the value that we calculate in R0
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
* - [7] = output delay (add 200ps of delay to mem signals)
* - [6] = input delay (add 200ps of input delay to mem signals)
* - [5] = PDWN : 1=All Clocks off
* - [3] = STOPCK : 1=Core Clock off
* - [1] = PLL_OFF : 1=Disable Power to PLL
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
* all other bits set to zero
*/
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over */
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
r0 = r1 | r0;
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */
cli r2; /* Disable interrupts */
ssync;
w[p0] = r0.l; /* Set the value */
idle; /* Wait for the PLL to stablize */
sti r2; /* Enable interrupts */
check_again:
p0.h = hi(PLL_STAT);
p0.l = lo(PLL_STAT);
R0 = W[P0](Z);
CC = BITTST(R0,5);
if ! CC jump check_again;
/* Configure SCLK & CCLK Dividers */
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
p0.h = hi(PLL_DIV);
p0.l = lo(PLL_DIV);
w[p0] = r0.l;
ssync;
#endif
/*
* Now, Initialize the SDRAM,
* start with the SDRAM Refresh Rate Control Register
*/
p0.l = lo(EBIU_SDRRC);
p0.h = hi(EBIU_SDRRC);
r0 = mem_SDRRC;
w[p0] = r0.l;
ssync;
/*
* SDRAM Memory Bank Control Register - bank specific parameters
*/
p0.l = (EBIU_SDBCTL & 0xFFFF);
p0.h = (EBIU_SDBCTL >> 16);
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
/*
* SDRAM Global Control Register - global programmable parameters
* Disable self-refresh
*/
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITCLR (R0, 24);
/*
* Check if SDRAM is already powered up, if it is, enable self-refresh
*/
p0.h = hi(EBIU_SDSTAT);
p0.l = lo(EBIU_SDSTAT);
r2.l = w[p0];
cc = bittst(r2,3);
if !cc jump skip;
NOP;
BITSET (R0, 23);
skip:
[P2] = R0;
SSYNC;
/* Write in the new value in the register */
R0.L = lo(mem_SDGCTL);
R0.H = hi(mem_SDGCTL);
[P2] = R0;
SSYNC;
nop;
(P5:0) = [SP++];
(R7:0) = [SP++];
RETS = [SP++];
ASTAT = [SP++];
RTS;

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cpu/bf537/init_sdram_bootrom_initblock.S Normal file
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#define ASSEMBLY
#include <linux/config.h>
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mem_init.h>
.global init_sdram;
#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
#if (CONFIG_CCLK_DIV == 1)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
#endif
#if (CONFIG_CCLK_DIV == 2)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
#endif
#if (CONFIG_CCLK_DIV == 4)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
#endif
#if (CONFIG_CCLK_DIV == 8)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
#endif
#ifndef CONFIG_CCLK_ACT_DIV
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
#endif
#endif
init_sdram:
[--SP] = ASTAT;
[--SP] = RETS;
[--SP] = (R7:0);
[--SP] = (P5:0);
#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT)
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
r0.l = 0x1;
w[p0] = r0.l;
SSYNC;
p0.h = hi(SPI_BAUD);
p0.l = lo(SPI_BAUD);
r0.l = CONFIG_SPI_BAUD_INITBLOCK;
w[p0] = r0.l;
SSYNC;
#endif
#if (BFIN_BOOT_MODE != BF537_UART_BOOT)
#ifdef CONFIG_BF537
/* Enable PHY CLK buffer output */
p0.h = hi(VR_CTL);
p0.l = lo(VR_CTL);
r0.l = w[p0];
bitset(r0, 14);
w[p0] = r0.l;
ssync;
#endif
/*
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
*/
p0.h = hi(PLL_LOCKCNT);
p0.l = lo(PLL_LOCKCNT);
r0 = 0x300(Z);
w[p0] = r0.l;
ssync;
/*
* Put SDRAM in self-refresh, incase anything is running
*/
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITSET (R0, 24);
[P2] = R0;
SSYNC;
/*
* Set PLL_CTL with the value that we calculate in R0
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
* - [7] = output delay (add 200ps of delay to mem signals)
* - [6] = input delay (add 200ps of input delay to mem signals)
* - [5] = PDWN : 1=All Clocks off
* - [3] = STOPCK : 1=Core Clock off
* - [1] = PLL_OFF : 1=Disable Power to PLL
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
* all other bits set to zero
*/
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over */
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
r0 = r1 | r0;
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */
cli r2; /* Disable interrupts */
ssync;
w[p0] = r0.l; /* Set the value */
idle; /* Wait for the PLL to stablize */
sti r2; /* Enable interrupts */
check_again:
p0.h = hi(PLL_STAT);
p0.l = lo(PLL_STAT);
R0 = W[P0](Z);
CC = BITTST(R0,5);
if ! CC jump check_again;
/* Configure SCLK & CCLK Dividers */
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
p0.h = hi(PLL_DIV);
p0.l = lo(PLL_DIV);
w[p0] = r0.l;
ssync;
#endif
/*
* We now are running at speed, time to set the Async mem bank wait states
* This will speed up execution, since we are normally running from FLASH.
*/
p2.h = (EBIU_AMBCTL1 >> 16);
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
r0.h = (AMBCTL1VAL >> 16);
r0.l = (AMBCTL1VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMBCTL0 >> 16);
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
r0.h = (AMBCTL0VAL >> 16);
r0.l = (AMBCTL0VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMGCTL >> 16);
p2.l = (EBIU_AMGCTL & 0xffff);
r0 = AMGCTLVAL;
w[p2] = r0;
ssync;
/*
* Now, Initialize the SDRAM,
* start with the SDRAM Refresh Rate Control Register
*/
p0.l = lo(EBIU_SDRRC);
p0.h = hi(EBIU_SDRRC);
r0 = mem_SDRRC;
w[p0] = r0.l;
ssync;
/*
* SDRAM Memory Bank Control Register - bank specific parameters
*/
p0.l = (EBIU_SDBCTL & 0xFFFF);
p0.h = (EBIU_SDBCTL >> 16);
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
/*
* SDRAM Global Control Register - global programmable parameters
* Disable self-refresh
*/
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITCLR (R0, 24);
/*
* Check if SDRAM is already powered up, if it is, enable self-refresh
*/
p0.h = hi(EBIU_SDSTAT);
p0.l = lo(EBIU_SDSTAT);
r2.l = w[p0];
cc = bittst(r2,3);
if !cc jump skip;
NOP;
BITSET (R0, 23);
skip:
[P2] = R0;
SSYNC;
/* Write in the new value in the register */
R0.L = lo(mem_SDGCTL);
R0.H = hi(mem_SDGCTL);
[P2] = R0;
SSYNC;
nop;
(P5:0) = [SP++];
(R7:0) = [SP++];
RETS = [SP++];
ASTAT = [SP++];
RTS;

246
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/*
* U-boot - interrupt.S Processing of interrupts and exception handling
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This file is based on interrupt.S
*
* Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com>
* Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
* Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
* Kenneth Albanowski <kjahds@kjahds.com>,
* The Silver Hammer Group, Ltd.
*
* (c) 1995, Dionne & Associates
* (c) 1995, DKG Display Tech.
*
* This file is also based on exception.asm
* (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define ASSEMBLY
#include <config.h>
#include <asm/blackfin.h>
#include <asm/hw_irq.h>
#include <asm/entry.h>
#include <asm/blackfin_defs.h>
.global _blackfin_irq_panic;
.text
.align 2
#ifndef CONFIG_KGDB
.global _evt_emulation
_evt_emulation:
SAVE_CONTEXT
r0 = IRQ_EMU;
r1 = seqstat;
sp += -12;
call _blackfin_irq_panic;
sp += 12;
rte;
#endif
.global _evt_nmi
_evt_nmi:
SAVE_CONTEXT
r0 = IRQ_NMI;
r1 = RETN;
sp += -12;
call _blackfin_irq_panic;
sp += 12;
_evt_nmi_exit:
rtn;
.global _trap
_trap:
SAVE_ALL_SYS
r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
sp += -12;
call _trap_c
sp += 12;
RESTORE_ALL_SYS
rtx;
.global _evt_rst
_evt_rst:
SAVE_CONTEXT
r0 = IRQ_RST;
r1 = RETN;
sp += -12;
call _do_reset;
sp += 12;
_evt_rst_exit:
rtn;
irq_panic:
r0 = IRQ_EVX;
r1 = sp;
sp += -12;
call _blackfin_irq_panic;
sp += 12;
.global _evt_ivhw
_evt_ivhw:
SAVE_CONTEXT
RAISE 14;
_evt_ivhw_exit:
rti;
.global _evt_timer
_evt_timer:
SAVE_CONTEXT
r0 = IRQ_CORETMR;
sp += -12;
/* Polling method used now. */
/* call timer_int; */
sp += 12;
RESTORE_CONTEXT
rti;
nop;
.global _evt_evt7
_evt_evt7:
SAVE_CONTEXT
r0 = 7;
sp += -12;
call _process_int;
sp += 12;
evt_evt7_exit:
RESTORE_CONTEXT
rti;
.global _evt_evt8
_evt_evt8:
SAVE_CONTEXT
r0 = 8;
sp += -12;
call _process_int;
sp += 12;
evt_evt8_exit:
RESTORE_CONTEXT
rti;
.global _evt_evt9
_evt_evt9:
SAVE_CONTEXT
r0 = 9;
sp += -12;
call _process_int;
sp += 12;
evt_evt9_exit:
RESTORE_CONTEXT
rti;
.global _evt_evt10
_evt_evt10:
SAVE_CONTEXT
r0 = 10;
sp += -12;
call _process_int;
sp += 12;
evt_evt10_exit:
RESTORE_CONTEXT
rti;
.global _evt_evt11
_evt_evt11:
SAVE_CONTEXT
r0 = 11;
sp += -12;
call _process_int;
sp += 12;
evt_evt11_exit:
RESTORE_CONTEXT
rti;
.global _evt_evt12
_evt_evt12:
SAVE_CONTEXT
r0 = 12;
sp += -12;
call _process_int;
sp += 12;
evt_evt12_exit:
RESTORE_CONTEXT
rti;
.global _evt_evt13
_evt_evt13:
SAVE_CONTEXT
r0 = 13;
sp += -12;
call _process_int;
sp += 12;
evt_evt13_exit:
RESTORE_CONTEXT
rti;
.global _evt_system_call
_evt_system_call:
[--sp] = r0;
[--SP] = RETI;
r0 = [sp++];
r0 += 2;
[--sp] = r0;
RETI = [SP++];
r0 = [SP++];
SAVE_CONTEXT
sp += -12;
call _exception_handle;
sp += 12;
RESTORE_CONTEXT
RTI;
evt_system_call_exit:
rti;
.global _evt_soft_int1
_evt_soft_int1:
[--sp] = r0;
[--SP] = RETI;
r0 = [sp++];
r0 += 2;
[--sp] = r0;
RETI = [SP++];
r0 = [SP++];
SAVE_CONTEXT
sp += -12;
call _exception_handle;
sp += 12;
RESTORE_CONTEXT
RTI;
evt_soft_int1_exit:
rti;

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/*
* U-boot - interrupts.c Interrupt related routines
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* This file is based on interrupts.c
* Copyright 1996 Roman Zippel
* Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
* Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
* Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
* Copyright 2003 Metrowerks/Motorola
* Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
* BuyWays B.V. (www.buyways.nl)
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <config.h>
#include <asm/blackfin.h>
#include "cpu.h"
static ulong timestamp;
static ulong last_time;
static int int_flag;
int irq_flags; /* needed by asm-blackfin/system.h */
/* Functions just to satisfy the linker */
/*
* This function is derived from PowerPC code (read timebase as long long).
* On BF533 it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On BF533 it returns the number of timer ticks per second.
*/
ulong get_tbclk (void)
{
ulong tbclk;
tbclk = CFG_HZ;
return tbclk;
}
void enable_interrupts(void)
{
restore_flags(int_flag);
}
int disable_interrupts(void)
{
save_and_cli(int_flag);
return 1;
}
int interrupt_init(void)
{
return (0);
}
void udelay(unsigned long usec)
{
unsigned long delay, start, stop;
unsigned long cclk;
cclk = (CONFIG_CCLK_HZ);
while (usec > 1) {
/*
* how many clock ticks to delay?
* - request(in useconds) * clock_ticks(Hz) / useconds/second
*/
if (usec < 1000) {
delay = (usec * (cclk / 244)) >> 12;
usec = 0;
} else {
delay = (1000 * (cclk / 244)) >> 12;
usec -= 1000;
}
asm volatile (" %0 = CYCLES;":"=r" (start));
do {
asm volatile (" %0 = CYCLES; ":"=r" (stop));
} while (stop - start < delay);
}
return;
}
void timer_init(void)
{
*pTCNTL = 0x1;
*pTSCALE = 0x0;
*pTCOUNT = MAX_TIM_LOAD;
*pTPERIOD = MAX_TIM_LOAD;
*pTCNTL = 0x7;
asm("CSYNC;");
timestamp = 0;
last_time = 0;
}
/* Any network command or flash
* command is started get_timer shall
* be called before TCOUNT gets reset,
* to implement the accurate timeouts.
*
* How ever milliconds doesn't return
* the number that has been elapsed from
* the last reset.
*
* As get_timer is used in the u-boot
* only for timeouts this should be
* sufficient
*/
ulong get_timer(ulong base)
{
ulong milisec;
/* Number of clocks elapsed */
ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
/**
* Find if the TCOUNT is reset
* timestamp gives the number of times
* TCOUNT got reset
*/
if (clocks < last_time)
timestamp++;
last_time = clocks;
/* Get the number of milliseconds */
milisec = clocks / (CONFIG_CCLK_HZ / 1000);
/**
* Find the number of millisonds
* that got elapsed before this TCOUNT cycle
*/
milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
return (milisec - base);
}
void reset_timer (void)
{
timestamp = 0;
}

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/*
* U-boot - ints.c Interrupt related routines
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* This file is based on ints.c
*
* Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
* drivers
*
* Copyright 1996 Roman Zippel
* Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
* Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
* Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
* Copyright 2003 Metrowerks/Motorola
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/stddef.h>
#include <asm/system.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/machdep.h>
#include <asm/setup.h>
#include <asm/blackfin.h>
#include "cpu.h"
void blackfin_irq_panic(int reason, struct pt_regs *regs)
{
printf("\n\nException: IRQ 0x%x entered\n", reason);
printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
printf("stack frame=0x%x, ", (unsigned int)regs);
printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
dump(regs);
printf("Unhandled IRQ or exceptions!\n");
printf("Please reset the board \n");
}
void blackfin_init_IRQ(void)
{
*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
cli();
#ifndef CONFIG_KGDB
*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
#endif
*(unsigned volatile long *)(EVT_NMI_ADDR) =
(unsigned volatile long)evt_nmi;
*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
(unsigned volatile long)trap;
*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
(unsigned volatile long)evt_ivhw;
*(unsigned volatile long *)(EVT_RESET_ADDR) =
(unsigned volatile long)evt_rst;
*(unsigned volatile long *)(EVT_TIMER_ADDR) =
(unsigned volatile long)evt_timer;
*(unsigned volatile long *)(EVT_IVG7_ADDR) =
(unsigned volatile long)evt_evt7;
*(unsigned volatile long *)(EVT_IVG8_ADDR) =
(unsigned volatile long)evt_evt8;
*(unsigned volatile long *)(EVT_IVG9_ADDR) =
(unsigned volatile long)evt_evt9;
*(unsigned volatile long *)(EVT_IVG10_ADDR) =
(unsigned volatile long)evt_evt10;
*(unsigned volatile long *)(EVT_IVG11_ADDR) =
(unsigned volatile long)evt_evt11;
*(unsigned volatile long *)(EVT_IVG12_ADDR) =
(unsigned volatile long)evt_evt12;
*(unsigned volatile long *)(EVT_IVG13_ADDR) =
(unsigned volatile long)evt_evt13;
*(unsigned volatile long *)(EVT_IVG14_ADDR) =
(unsigned volatile long)evt_system_call;
*(unsigned volatile long *)(EVT_IVG15_ADDR) =
(unsigned volatile long)evt_soft_int1;
*(volatile unsigned long *)ILAT = 0;
asm("csync;");
sti();
*(volatile unsigned long *)IMASK = 0xffbf;
asm("csync;");
}
void exception_handle(void)
{
#if defined (CONFIG_PANIC_HANG)
display_excp();
#else
udelay(100000); /* allow messages to go out */
do_reset(NULL, 0, 0, NULL);
#endif
}
void display_excp(void)
{
printf("Exception!\n");
}

194
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/*
* U-boot - serial.c Serial driver for BF537
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* This file is based on
* bf537_serial.c: Serial driver for BlackFin BF537 internal UART.
* Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
* BuyWays B.V. (www.buyways.nl)
*
* Based heavily on blkfinserial.c
* blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
* Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
* Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
* Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
*
* Based on code from 68328 version serial driver imlpementation which was:
* Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
* Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
* Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/segment.h>
#include <asm/bitops.h>
#include <asm/delay.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include "serial.h"
unsigned long pll_div_fact;
void calc_baud(void)
{
unsigned char i;
int temp;
u_long sclk = get_sclk();
for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
temp = sclk / (baud_table[i] * 8);
if ((temp & 0x1) == 1) {
temp++;
}
temp = temp / 2;
hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
hw_baud_table[i].dl_low = (temp) & 0xFF;
}
}
void serial_setbrg(void)
{
int i;
DECLARE_GLOBAL_DATA_PTR;
calc_baud();
for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
if (gd->baudrate == baud_table[i])
break;
}
/* Enable UART */
*pUART_GCTL |= UART_GCTL_UCEN;
sync();
/* Set DLAB in LCR to Access DLL and DLH */
ACCESS_LATCH;
sync();
*pUART_DLL = hw_baud_table[i].dl_low;
sync();
*pUART_DLH = hw_baud_table[i].dl_high;
sync();
/* Clear DLAB in LCR to Access THR RBR IER */
ACCESS_PORT_IER;
sync();
/* Enable ERBFI and ELSI interrupts
* to poll SIC_ISR register*/
*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
sync();
/* Set LCR to Word Lengh 8-bit word select */
*pUART_LCR = UART_LCR_WLS8;
sync();
return;
}
int serial_init(void)
{
serial_setbrg();
return (0);
}
void serial_putc(const char c)
{
if ((*pUART_LSR) & UART_LSR_TEMT) {
if (c == '\n')
serial_putc('\r');
local_put_char(c);
}
while (!((*pUART_LSR) & UART_LSR_TEMT))
SYNC_ALL;
return;
}
int serial_tstc(void)
{
if (*pUART_LSR & UART_LSR_DR)
return 1;
else
return 0;
}
int serial_getc(void)
{
unsigned short uart_lsr_val, uart_rbr_val;
unsigned long isr_val;
int ret;
/* Poll for RX Interrupt */
while (!((isr_val =
*(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
asm("csync;");
uart_lsr_val = *pUART_LSR; /* Clear status bit */
uart_rbr_val = *pUART_RBR; /* getc() */
if (isr_val & IRQ_UART_ERROR_BIT) {
ret = -1;
} else {
ret = uart_rbr_val & 0xff;
}
return ret;
}
void serial_puts(const char *s)
{
while (*s) {
serial_putc(*s++);
}
}
static void local_put_char(char ch)
{
int flags = 0;
unsigned long isr_val;
save_and_cli(flags);
/* Poll for TX Interruput */
while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
asm("csync;");
*pUART_THR = ch; /* putc() */
if (isr_val & IRQ_UART_ERROR_BIT) {
printf("?");
}
restore_flags(flags);
return;
}

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/*
* U-boot - bf537_serial.h Serial Driver defines
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* This file is based on
* bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
* Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl>
* BuyWays B.V. (www.buyways.nl)
*
* Based heavily on:
* blkfinserial.h: Definitions for the BlackFin DSP serial driver.
*
* Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com
* Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com>
*
* Based on code from 68328serial.c which was:
* Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
* Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
* Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _Bf537_SERIAL_H
#define _Bf537_SERIAL_H
#include <linux/config.h>
#include <asm/blackfin.h>
#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB;
#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB);
void serial_setbrg(void);
static void local_put_char(char ch);
void calc_baud(void);
void serial_setbrg(void);
int serial_init(void);
void serial_putc(const char c);
int serial_tstc(void);
int serial_getc(void);
void serial_puts(const char *s);
static void local_put_char(char ch);
int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
struct {
unsigned char dl_high;
unsigned char dl_low;
} hw_baud_table[5];
#ifdef CONFIG_STAMP
extern unsigned long pll_div_fact;
#endif
#endif

579
cpu/bf537/start.S Normal file
View file

@ -0,0 +1,579 @@
/*
* U-boot - start.S Startup file of u-boot for BF537
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* This file is based on head.S
* Copyright (c) 2003 Metrowerks/Motorola
* Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
* Kenneth Albanowski <kjahds@kjahds.com>,
* The Silver Hammer Group, Ltd.
* (c) 1995, Dionne & Associates
* (c) 1995, DKG Display Tech.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Note: A change in this file subsequently requires a change in
* board/$(board_name)/config.mk for a valid u-boot.bin
*/
#define ASSEMBLY
#include <linux/config.h>
#include <config.h>
#include <asm/blackfin.h>
.global _stext;
.global __bss_start;
.global start;
.global _start;
.global _rambase;
.global _ramstart;
.global _ramend;
.global _bf533_data_dest;
.global _bf533_data_size;
.global edata;
.global _initialize;
.global _exit;
.global flashdataend;
.global init_sdram;
.global _icache_enable;
.global _dcache_enable;
#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
.global _memory_post_test;
.global _post_flag;
#endif
#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
#if (CONFIG_CCLK_DIV == 1)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
#endif
#if (CONFIG_CCLK_DIV == 2)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
#endif
#if (CONFIG_CCLK_DIV == 4)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
#endif
#if (CONFIG_CCLK_DIV == 8)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
#endif
#ifndef CONFIG_CCLK_ACT_DIV
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
#endif
#endif
.text
_start:
start:
_stext:
R0 = 0x32;
SYSCFG = R0;
SSYNC;
/* As per HW reference manual DAG registers,
* DATA and Address resgister shall be zero'd
* in initialization, after a reset state
*/
r1 = 0; /* Data registers zero'd */
r2 = 0;
r3 = 0;
r4 = 0;
r5 = 0;
r6 = 0;
r7 = 0;
p0 = 0; /* Address registers zero'd */
p1 = 0;
p2 = 0;
p3 = 0;
p4 = 0;
p5 = 0;
i0 = 0; /* DAG Registers zero'd */
i1 = 0;
i2 = 0;
i3 = 0;
m0 = 0;
m1 = 0;
m3 = 0;
m3 = 0;
l0 = 0;
l1 = 0;
l2 = 0;
l3 = 0;
b0 = 0;
b1 = 0;
b2 = 0;
b3 = 0;
/* Set loop counters to zero, to make sure that
* hw loops are disabled.
*/
r0 = 0;
lc0 = r0;
lc1 = r0;
SSYNC;
/* Check soft reset status */
p0.h = SWRST >> 16;
p0.l = SWRST & 0xFFFF;
r0.l = w[p0];
cc = bittst(r0, 15);
if !cc jump no_soft_reset;
/* Clear Soft reset */
r0 = 0x0000;
w[p0] = r0;
ssync;
no_soft_reset:
nop;
/* Clear EVT registers */
p0.h = (EVT_EMULATION_ADDR >> 16);
p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
p0 += 8;
p1 = 14;
r1 = 0;
LSETUP(4,4) lc0 = p1;
[ p0 ++ ] = r1;
#if (BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT)
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
r0.l = 0x1;
w[p0] = r0.l;
SSYNC;
#endif
#if (BFIN_BOOT_MODE == BF537_UART_BOOT)
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
r0.l = 0x1;
w[p0] = r0.l;
SSYNC;
/*
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
*/
p0.h = hi(PLL_LOCKCNT);
p0.l = lo(PLL_LOCKCNT);
r0 = 0x300(Z);
w[p0] = r0.l;
ssync;
/*
* Put SDRAM in self-refresh, incase anything is running
*/
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITSET (R0, 24);
[P2] = R0;
SSYNC;
/*
* Set PLL_CTL with the value that we calculate in R0
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
* - [7] = output delay (add 200ps of delay to mem signals)
* - [6] = input delay (add 200ps of input delay to mem signals)
* - [5] = PDWN : 1=All Clocks off
* - [3] = STOPCK : 1=Core Clock off
* - [1] = PLL_OFF : 1=Disable Power to PLL
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
* all other bits set to zero
*/
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over, */
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
r0 = r1 | r0;
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */
cli r2; /* Disable interrupts */
ssync;
w[p0] = r0.l; /* Set the value */
idle; /* Wait for the PLL to stablize */
sti r2; /* Enable interrupts */
check_again:
p0.h = hi(PLL_STAT);
p0.l = lo(PLL_STAT);
R0 = W[P0](Z);
CC = BITTST(R0,5);
if ! CC jump check_again;
/* Configure SCLK & CCLK Dividers */
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
p0.h = hi(PLL_DIV);
p0.l = lo(PLL_DIV);
w[p0] = r0.l;
ssync;
#endif
/*
* We now are running at speed, time to set the Async mem bank wait states
* This will speed up execution, since we are normally running from FLASH.
* we need to read MAC address from FLASH
*/
p2.h = (EBIU_AMBCTL1 >> 16);
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
r0.h = (AMBCTL1VAL >> 16);
r0.l = (AMBCTL1VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMBCTL0 >> 16);
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
r0.h = (AMBCTL0VAL >> 16);
r0.l = (AMBCTL0VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMGCTL >> 16);
p2.l = (EBIU_AMGCTL & 0xffff);
r0 = AMGCTLVAL;
w[p2] = r0;
ssync;
#if ((BFIN_BOOT_MODE != BF537_SPI_MASTER_BOOT) && (BFIN_BOOT_MODE != BF537_UART_BOOT))
sp.l = (0xffb01000 & 0xFFFF);
sp.h = (0xffb01000 >> 16);
call init_sdram;
#endif
#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
/* DMA POST code to Hi of L1 SRAM */
postcopy:
/* P1 Points to the beginning of SYSTEM MMR Space */
P1.H = hi(SYSMMR_BASE);
P1.L = lo(SYSMMR_BASE);
R0.H = _text_l1;
R0.L = _text_l1;
R1.H = _etext_l1;
R1.L = _etext_l1;
R2 = R1 - R0; /* Count */
R0.H = _etext;
R0.L = _etext;
R1.H = (CFG_MONITOR_BASE >> 16);
R1.L = (CFG_MONITOR_BASE & 0xFFFF);
R0 = R0 - R1;
R1.H = (CFG_FLASH_BASE >> 16);
R1.L = (CFG_FLASH_BASE & 0xFFFF);
R0 = R0 + R1; /* Source Address */
R1.H = hi(L1_ISRAM); /* Destination Address (high) */
R1.L = lo(L1_ISRAM); /* Destination Address (low) */
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
/* Destination DMAConfig Value (8-bit words) */
R4.L = (DI_EN | WNR | DMAEN);
R6 = 0x1 (Z);
W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
/* Set Source DMAConfig = DMA Enable,
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
/* Set Destination DMAConfig = DMA Enable,
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
POST_DMA_DONE:
p0.h = hi(MDMA_D0_IRQ_STATUS);
p0.l = lo(MDMA_D0_IRQ_STATUS);
R0 = W[P0](Z);
CC = BITTST(R0, 0);
if ! CC jump POST_DMA_DONE
R0 = 0x1;
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
/* DMA POST data to Hi of L1 SRAM */
R0.H = _rodata_l1;
R0.L = _rodata_l1;
R1.H = _erodata_l1;
R1.L = _erodata_l1;
R2 = R1 - R0; /* Count */
R0.H = _erodata;
R0.L = _erodata;
R1.H = (CFG_MONITOR_BASE >> 16);
R1.L = (CFG_MONITOR_BASE & 0xFFFF);
R0 = R0 - R1;
R1.H = (CFG_FLASH_BASE >> 16);
R1.L = (CFG_FLASH_BASE & 0xFFFF);
R0 = R0 + R1; /* Source Address */
R1.H = hi(DATA_BANKB_SRAM); /* Destination Address (high) */
R1.L = lo(DATA_BANKB_SRAM); /* Destination Address (low) */
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
R6 = 0x1 (Z);
W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
/* Set Source DMAConfig = DMA Enable,
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
/* Set Destination DMAConfig = DMA Enable,
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
POST_DATA_DMA_DONE:
p0.h = hi(MDMA_D0_IRQ_STATUS);
p0.l = lo(MDMA_D0_IRQ_STATUS);
R0 = W[P0](Z);
CC = BITTST(R0, 0);
if ! CC jump POST_DATA_DMA_DONE
R0 = 0x1;
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
p0.l = _memory_post_test;
p0.h = _memory_post_test;
r0 = 0x0;
call (p0);
r7 = r0; /* save return value */
call init_sdram;
#endif
/* relocate into to RAM */
call get_pc;
offset:
r2.l = offset;
r2.h = offset;
r3.l = start;
r3.h = start;
r1 = r2 - r3;
r0 = r0 - r1;
p1 = r0;
p2.l = (CFG_MONITOR_BASE & 0xffff);
p2.h = (CFG_MONITOR_BASE >> 16);
p3 = 0x04;
p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
loop1:
r1 = [p1 ++ p3];
[p2 ++ p3] = r1;
cc=p2==p4;
if !cc jump loop1;
/*
* configure STACK
*/
r0.h = (CONFIG_STACKBASE >> 16);
r0.l = (CONFIG_STACKBASE & 0xFFFF);
sp = r0;
fp = sp;
/*
* This next section keeps the processor in supervisor mode
* during kernel boot. Switches to user mode at end of boot.
* See page 3-9 of Hardware Reference manual for documentation.
*/
/* To keep ourselves in the supervisor mode */
p0.l = (EVT_IVG15_ADDR & 0xFFFF);
p0.h = (EVT_IVG15_ADDR >> 16);
p1.l = _real_start;
p1.h = _real_start;
[p0] = p1;
p0.l = (IMASK & 0xFFFF);
p0.h = (IMASK >> 16);
r0.l = LO(IVG15_POS);
r0.h = HI(IVG15_POS);
[p0] = r0;
raise 15;
p0.l = WAIT_HERE;
p0.h = WAIT_HERE;
reti = p0;
rti;
WAIT_HERE:
jump WAIT_HERE;
.global _real_start;
_real_start:
[ -- sp ] = reti;
#ifdef CONFIG_BF537
/* Initialise General-Purpose I/O Modules on BF537
* Rev 0.0 Anomaly 05000212 - PORTx_FER,
* PORT_MUX Registers Do Not accept "writes" correctly
*/
p0.h = hi(PORTF_FER);
p0.l = lo(PORTF_FER);
R0.L = W[P0]; /* Read */
nop;
nop;
nop;
ssync;
R0 = 0x000F(Z);
W[P0] = R0.L; /* Write */
nop;
nop;
nop;
ssync;
W[P0] = R0.L; /* Enable peripheral function of PORTF for UART0 and UART1 */
nop;
nop;
nop;
ssync;
p0.h = hi(PORTH_FER);
p0.l = lo(PORTH_FER);
R0.L = W[P0]; /* Read */
nop;
nop;
nop;
ssync;
R0 = 0xFFFF(Z);
W[P0] = R0.L; /* Write */
nop;
nop;
nop;
ssync;
W[P0] = R0.L; /* Enable peripheral function of PORTH for MAC */
nop;
nop;
nop;
ssync;
#endif
/* DMA reset code to Hi of L1 SRAM */
copy:
P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
P1.L = lo(SYSMMR_BASE);
R0.H = reset_start; /* Source Address (high) */
R0.L = reset_start; /* Source Address (low) */
R1.H = reset_end;
R1.L = reset_end;
R2 = R1 - R0; /* Count */
R1.H = hi(L1_ISRAM); /* Destination Address (high) */
R1.L = lo(L1_ISRAM); /* Destination Address (low) */
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
DMA:
R6 = 0x1 (Z);
W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
/* Set Source DMAConfig = DMA Enable,
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
/* Set Destination DMAConfig = DMA Enable,
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
WAIT_DMA_DONE:
p0.h = hi(MDMA_D0_IRQ_STATUS);
p0.l = lo(MDMA_D0_IRQ_STATUS);
R0 = W[P0](Z);
CC = BITTST(R0, 0);
if ! CC jump WAIT_DMA_DONE
R0 = 0x1;
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
/* Initialize BSS Section with 0 s */
p1.l = __bss_start;
p1.h = __bss_start;
p2.l = _end;
p2.h = _end;
r1 = p1;
r2 = p2;
r3 = r2 - r1;
r3 = r3 >> 2;
p3 = r3;
lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
CC = p2<=p1;
if CC jump _clear_bss_skip;
r0 = 0;
_clear_bss:
_clear_bss_end:
[p1++] = r0;
_clear_bss_skip:
#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
p0.l = _post_flag;
p0.h = _post_flag;
r0 = r7;
[p0] = r0;
#endif
p0.l = _start1;
p0.h = _start1;
jump (p0);
reset_start:
p0.h = WDOG_CNT >> 16;
p0.l = WDOG_CNT & 0xffff;
r0 = 0x0010;
w[p0] = r0;
p0.h = WDOG_CTL >> 16;
p0.l = WDOG_CTL & 0xffff;
r0 = 0x0000;
w[p0] = r0;
reset_wait:
jump reset_wait;
reset_end:
nop;
_exit:
jump.s _exit;
get_pc:
r0 = rets;
rts;

40
post/dsp.c → cpu/bf537/start1.S
View file

@ -1,6 +1,7 @@
/*
* (C) Copyright 2004
* Pantelis Antoniou, Intracom S.A. , panto@intracom.gr
* U-boot - start1.S Code running out of RAM after relocation
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* See file CREDITS for list of people who contributed to this
* project.
@ -21,28 +22,17 @@
* MA 02111-1307 USA
*/
#include <common.h>
#define ASSEMBLY
#include <linux/config.h>
#include <config.h>
#include <asm/blackfin.h>
/*
* DSP test
*
* This test verifies the connection and performs a memory test
* on any connected DSP(s). The meat of the work is done
* in the board specific function.
*/
.global start1;
.global _start1;
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_DSP
extern int board_post_dsp(int flags);
int dsp_post_test (int flags)
{
return board_post_dsp(flags);
}
#endif /* CONFIG_POST & CFG_POST_DSP */
#endif /* CONFIG_POST */
.text
_start1:
start1:
sp += -12;
call _board_init_f;
sp += 12;

241
cpu/bf537/traps.c Normal file
View file

@ -0,0 +1,241 @@
/*
* U-boot - traps.c Routines related to interrupts and exceptions
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* This file is based on
* No original Copyright holder listed,
* Probabily original (C) Roman Zippel (assigned DJD, 1999)
*
* Copyright 2003 Metrowerks - for Blackfin
* Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
* Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/types.h>
#include <asm/errno.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/page.h>
#include <asm/machdep.h>
#include "cpu.h"
#include <asm/arch/anomaly.h>
#include <asm/cplb.h>
#include <asm/io.h>
void init_IRQ(void)
{
blackfin_init_IRQ();
return;
}
void process_int(unsigned long vec, struct pt_regs *fp)
{
printf("interrupt\n");
return;
}
extern unsigned int icplb_table[page_descriptor_table_size][2];
extern unsigned int dcplb_table[page_descriptor_table_size][2];
unsigned long last_cplb_fault_retx;
static unsigned int cplb_sizes[4] =
{ 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
void trap_c(struct pt_regs *regs)
{
unsigned int addr;
unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
unsigned int i, j, size, *I0, *I1;
unsigned short data = 0;
switch (trapnr) {
/* 0x26 - Data CPLB Miss */
case VEC_CPLB_M:
#ifdef ANOMALY_05000261
/*
* Work around an anomaly: if we see a new DCPLB fault,
* return without doing anything. Then,
* if we get the same fault again, handle it.
*/
addr = last_cplb_fault_retx;
last_cplb_fault_retx = regs->retx;
printf("this time, curr = 0x%08x last = 0x%08x\n",
addr, last_cplb_fault_retx);
if (addr != last_cplb_fault_retx)
goto trap_c_return;
#endif
data = 1;
case VEC_CPLB_I_M:
if (data) {
addr = *pDCPLB_FAULT_ADDR;
} else {
addr = *pICPLB_FAULT_ADDR;
}
for (i = 0; i < page_descriptor_table_size; i++) {
if (data) {
size = cplb_sizes[dcplb_table[i][1] >> 16];
j = dcplb_table[i][0];
} else {
size = cplb_sizes[icplb_table[i][1] >> 16];
j = icplb_table[i][0];
}
if ((j <= addr) && ((j + size) > addr)) {
debug("found %i 0x%08x\n", i, j);
break;
}
}
if (i == page_descriptor_table_size) {
printf("something is really wrong\n");
do_reset(NULL, 0, 0, NULL);
}
/* Turn the cache off */
if (data) {
sync();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL &=
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
sync();
} else {
sync();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
sync();
}
if (data) {
I0 = (unsigned int *)DCPLB_ADDR0;
I1 = (unsigned int *)DCPLB_DATA0;
} else {
I0 = (unsigned int *)ICPLB_ADDR0;
I1 = (unsigned int *)ICPLB_DATA0;
}
j = 0;
while (*I1 & CPLB_LOCK) {
debug("skipping %i %08p - %08x\n", j, I1, *I1);
*I0++;
*I1++;
j++;
}
debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
for (; j < 15; j++) {
debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
*I0++ = *(I0 + 1);
*I1++ = *(I1 + 1);
}
if (data) {
*I0 = dcplb_table[i][0];
*I1 = dcplb_table[i][1];
I0 = (unsigned int *)DCPLB_ADDR0;
I1 = (unsigned int *)DCPLB_DATA0;
} else {
*I0 = icplb_table[i][0];
*I1 = icplb_table[i][1];
I0 = (unsigned int *)ICPLB_ADDR0;
I1 = (unsigned int *)ICPLB_DATA0;
}
for (j = 0; j < 16; j++) {
debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
}
/* Turn the cache back on */
if (data) {
j = *(unsigned int *)DMEM_CONTROL;
sync();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL =
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
sync();
} else {
sync();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
sync();
}
break;
default:
/* All traps come here */
printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
printf("stack frame=0x%x, ", (unsigned int)regs);
printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
dump(regs);
printf("\n\n");
printf("Unhandled IRQ or exceptions!\n");
printf("Please reset the board \n");
do_reset(NULL, 0, 0, NULL);
}
trap_c_return:
return;
}
void dump(struct pt_regs *fp)
{
debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n",
fp->rete, fp->retn, fp->retx, fp->rets);
debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
fp->r0, fp->r1, fp->r2, fp->r3);
debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
fp->r4, fp->r5, fp->r6, fp->r7);
debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
fp->p0, fp->p1, fp->p2, fp->p3);
debug("P4: %08lx P5: %08lx FP: %08lx\n",
fp->p4, fp->p5, fp->fp);
debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
fp->a0w, fp->a0x, fp->a1w, fp->a1x);
debug("LB0: %08lx LT0: %08lx LC0: %08lx\n",
fp->lb0, fp->lt0, fp->lc0);
debug("LB1: %08lx LT1: %08lx LC1: %08lx\n",
fp->lb1, fp->lt1, fp->lc1);
debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n",
fp->b0, fp->l0, fp->m0, fp->i0);
debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n",
fp->b1, fp->l1, fp->m1, fp->i1);
debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n",
fp->b2, fp->l2, fp->m2, fp->i2);
debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n",
fp->b3, fp->l3, fp->m3, fp->i3);
debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
}

194
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/*
* (C) Copyright 2000
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
* (C) Copyright 2002
* Wolfgang Denk, wd@denx.de
* (C) Copyright 2006
* Aubrey Li, aubrey.li@analog.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <stdarg.h>
#include <common.h>
#include <config.h>
#include <asm/blackfin.h>
#include <i2c.h>
#include <linux/types.h>
#include <devices.h>
#ifdef CONFIG_VIDEO
#define NTSC_FRAME_ADDR 0x06000000
#include "video.h"
/* NTSC OUTPUT SIZE 720 * 240 */
#define VERTICAL 2
#define HORIZONTAL 4
int is_vblank_line(const int line)
{
/*
* This array contains a single bit for each line in
* an NTSC frame.
*/
if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
return true;
return false;
}
int NTSC_framebuffer_init(char *base_address)
{
const int NTSC_frames = 1;
const int NTSC_lines = 525;
char *dest = base_address;
int frame_num, line_num;
for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
unsigned int code;
int offset = 0;
int i;
if (is_vblank_line(line_num))
offset++;
if (line_num > 266 || line_num < 3)
offset += 2;
/* Output EAV code */
code = SystemCodeMap[offset].EAV;
write_dest_byte((char)(code >> 24) & 0xff);
write_dest_byte((char)(code >> 16) & 0xff);
write_dest_byte((char)(code >> 8) & 0xff);
write_dest_byte((char)(code) & 0xff);
/* Output horizontal blanking */
for (i = 0; i < 67 * 2; ++i) {
write_dest_byte(0x80);
write_dest_byte(0x10);
}
/* Output SAV */
code = SystemCodeMap[offset].SAV;
write_dest_byte((char)(code >> 24) & 0xff);
write_dest_byte((char)(code >> 16) & 0xff);
write_dest_byte((char)(code >> 8) & 0xff);
write_dest_byte((char)(code) & 0xff);
/* Output empty horizontal data */
for (i = 0; i < 360 * 2; ++i) {
write_dest_byte(0x80);
write_dest_byte(0x10);
}
}
}
return dest - base_address;
}
void fill_frame(char *Frame, int Value)
{
int *OddPtr32;
int OddLine;
int *EvenPtr32;
int EvenLine;
int i;
int *data;
int m, n;
/* fill odd and even frames */
for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
*OddPtr32 = Value;
*EvenPtr32 = Value;
}
}
for (m = 0; m < VERTICAL; m++) {
data = (int *)u_boot_logo.data;
for (OddLine = (22 + m), EvenLine = (285 + m);
OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
OddLine += VERTICAL, EvenLine += VERTICAL) {
OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
EvenPtr32 =
(int *)((Frame + ((EvenLine) * 1716)) + 276);
for (i = 0; i < u_boot_logo.width / 2; i++) {
/* enlarge one pixel to m x n */
for (n = 0; n < HORIZONTAL; n++) {
*OddPtr32++ = *data;
*EvenPtr32++ = *data;
}
data++;
}
}
}
}
void video_putc(const char c)
{
}
void video_puts(const char *s)
{
}
static int video_init(void)
{
char *NTSCFrame;
NTSCFrame = (char *)NTSC_FRAME_ADDR;
NTSC_framebuffer_init(NTSCFrame);
fill_frame(NTSCFrame, BLUE);
*pPPI_CONTROL = 0x0082;
*pPPI_FRAME = 0x020D;
*pDMA0_START_ADDR = NTSCFrame;
*pDMA0_X_COUNT = 0x035A;
*pDMA0_X_MODIFY = 0x0002;
*pDMA0_Y_COUNT = 0x020D;
*pDMA0_Y_MODIFY = 0x0002;
*pDMA0_CONFIG = 0x1015;
*pPPI_CONTROL = 0x0083;
return 0;
}
int drv_video_init(void)
{
int error, devices = 1;
device_t videodev;
video_init(); /* Video initialization */
memset(&videodev, 0, sizeof(videodev));
strcpy(videodev.name, "video");
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */
videodev.putc = video_putc; /* 'putc' function */
videodev.puts = video_puts; /* 'puts' function */
error = device_register(&videodev);
return (error == 0) ? devices : error;
}
#endif

25
cpu/bf537/video.h Normal file
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#include <video_logo.h>
#define write_dest_byte(val) {*dest++=val;}
#define BLACK (0x01800180) /* black pixel pattern */
#define BLUE (0x296E29F0) /* blue pixel pattern */
#define RED (0x51F0515A) /* red pixel pattern */
#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern*/
#define GREEN (0x91229136) /* green pixel pattern */
#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
#define YELLOW (0xD292D210) /* yellow pixel pattern */
#define WHITE (0xFE80FE80) /* white pixel pattern */
#define true 1
#define false 0
typedef struct {
unsigned int SAV;
unsigned int EAV;
} SystemCodeType;
const SystemCodeType SystemCodeMap[4] = {
{0xFF000080, 0xFF00009D},
{0xFF0000AB, 0xFF0000B6},
{0xFF0000C7, 0xFF0000DA},
{0xFF0000EC, 0xFF0000F1}
};

52
cpu/bf561/Makefile Normal file
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# U-boot - Makefile
#
# Copyright (c) 2005 blackfin.uclinux.org
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o
EXTRA = init_sdram_bootrom_initblock.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB) $(obj).depend $(EXTRA)
$(LIB): $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

128
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#define ASSEMBLY
#include <asm/linkage.h>
#include <config.h>
#include <asm/blackfin.h>
.text
.align 2
ENTRY(_blackfin_icache_flush_range)
R2 = -32;
R2 = R0 & R2;
P0 = R2;
P1 = R1;
CSYNC;
1:
IFLUSH[P0++];
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
IFLUSH[P0];
SSYNC;
RTS;
ENTRY(_blackfin_dcache_flush_range)
R2 = -32;
R2 = R0 & R2;
P0 = R2;
P1 = R1;
CSYNC;
1:
FLUSH[P0++];
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
FLUSH[P0];
SSYNC;
RTS;
ENTRY(_icache_invalidate)
ENTRY(_invalidate_entire_icache)
[--SP] = (R7:5);
P0.L = (IMEM_CONTROL & 0xFFFF);
P0.H = (IMEM_CONTROL >> 16);
R7 =[P0];
/*
* Clear the IMC bit , All valid bits in the instruction
* cache are set to the invalid state
*/
BITCLR(R7, IMC_P);
CLI R6;
/* SSYNC required before invalidating cache. */
SSYNC;
.align 8;
[P0] = R7;
SSYNC;
STI R6;
/* Configures the instruction cache agian */
R6 = (IMC | ENICPLB);
R7 = R7 | R6;
CLI R6;
SSYNC;
.align 8;
[P0] = R7;
SSYNC;
STI R6;
(R7:5) =[SP++];
RTS;
/*
* Invalidate the Entire Data cache by
* clearing DMC[1:0] bits
*/
ENTRY(_invalidate_entire_dcache)
ENTRY(_dcache_invalidate)
[--SP] = (R7:6);
P0.L = (DMEM_CONTROL & 0xFFFF);
P0.H = (DMEM_CONTROL >> 16);
R7 =[P0];
/*
* Clear the DMC[1:0] bits, All valid bits in the data
* cache are set to the invalid state
*/
BITCLR(R7, DMC0_P);
BITCLR(R7, DMC1_P);
CLI R6;
SSYNC;
.align 8;
[P0] = R7;
SSYNC;
STI R6;
/* Configures the data cache again */
R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
R7 = R7 | R6;
CLI R6;
SSYNC;
.align 8;
[P0] = R7;
SSYNC;
STI R6;
(R7:6) =[SP++];
RTS;
ENTRY(_blackfin_dcache_invalidate_range)
R2 = -32;
R2 = R0 & R2;
P0 = R2;
P1 = R1;
CSYNC;
1:
FLUSHINV[P0++];
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
/*
* If the data crosses a cache line, then we'll be pointing to
* the last cache line, but won't have flushed/invalidated it yet, so do
* one more.
*/
FLUSHINV[P0];
SSYNC;
RTS;

27
cpu/bf561/config.mk Normal file
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# U-boot - config.mk
#
# Copyright (c) 2005 blackfin.uclinux.org
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
PLATFORM_RELFLAGS += -mcpu=bf561 -ffixed-P5

220
cpu/bf561/cpu.c Normal file
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/*
* U-boot - cpu.c CPU specific functions
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/blackfin.h>
#include <command.h>
#include <asm/entry.h>
#include <asm/cplb.h>
#include <asm/io.h>
#define CACHE_ON 1
#define CACHE_OFF 0
extern unsigned int icplb_table[page_descriptor_table_size][2];
extern unsigned int dcplb_table[page_descriptor_table_size][2];
int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
);
return 0;
}
/* These functions are just used to satisfy the linker */
int cpu_init(void)
{
return 0;
}
int cleanup_before_linux(void)
{
return 0;
}
void icache_enable(void)
{
unsigned int *I0, *I1;
int i, j = 0;
/* Before enable icache, disable it first */
icache_disable();
I0 = (unsigned int *)ICPLB_ADDR0;
I1 = (unsigned int *)ICPLB_DATA0;
/* make sure the locked ones go in first */
for (i = 0; i < page_descriptor_table_size; i++) {
if (CPLB_LOCK & icplb_table[i][1]) {
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
icplb_table[i][0], icplb_table[i][1]);
*I0++ = icplb_table[i][0];
*I1++ = icplb_table[i][1];
j++;
}
}
for (i = 0; i < page_descriptor_table_size; i++) {
if (!(CPLB_LOCK & icplb_table[i][1])) {
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
icplb_table[i][0], icplb_table[i][1]);
*I0++ = icplb_table[i][0];
*I1++ = icplb_table[i][1];
j++;
if (j == 16) {
break;
}
}
}
/* Fill the rest with invalid entry */
if (j <= 15) {
for (; j < 16; j++) {
debug("filling %i with 0", j);
*I1++ = 0x0;
}
}
cli();
sync();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
sync();
sti();
}
void icache_disable(void)
{
cli();
sync();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
sync();
sti();
}
int icache_status(void)
{
unsigned int value;
value = *(unsigned int *)IMEM_CONTROL;
if (value & (IMC | ENICPLB))
return CACHE_ON;
else
return CACHE_OFF;
}
void dcache_enable(void)
{
unsigned int *I0, *I1;
unsigned int temp;
int i, j = 0;
/* Before enable dcache, disable it first */
dcache_disable();
I0 = (unsigned int *)DCPLB_ADDR0;
I1 = (unsigned int *)DCPLB_DATA0;
/* make sure the locked ones go in first */
for (i = 0; i < page_descriptor_table_size; i++) {
if (CPLB_LOCK & dcplb_table[i][1]) {
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
dcplb_table[i][0], dcplb_table[i][1]);
*I0++ = dcplb_table[i][0];
*I1++ = dcplb_table[i][1];
j++;
} else {
debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
dcplb_table[i][0], dcplb_table[i][1]);
}
}
for (i = 0; i < page_descriptor_table_size; i++) {
if (!(CPLB_LOCK & dcplb_table[i][1])) {
debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
dcplb_table[i][0], dcplb_table[i][1]);
*I0++ = dcplb_table[i][0];
*I1++ = dcplb_table[i][1];
j++;
if (j == 16) {
break;
}
}
}
/* Fill the rest with invalid entry */
if (j <= 15) {
for (; j < 16; j++) {
debug("filling %i with 0", j);
*I1++ = 0x0;
}
}
cli();
temp = *(unsigned int *)DMEM_CONTROL;
sync();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL =
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
sync();
sti();
}
void dcache_disable(void)
{
unsigned int *I0, *I1;
int i;
cli();
sync();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL &=
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
sync();
sti();
/* after disable dcache, clear it so we don't confuse the next application */
I0 = (unsigned int *)DCPLB_ADDR0;
I1 = (unsigned int *)DCPLB_DATA0;
for (i = 0; i < 16; i++) {
*I0++ = 0x0;
*I1++ = 0x0;
}
}
int dcache_status(void)
{
unsigned int value;
value = *(unsigned int *)DMEM_CONTROL;
if (value & (ENDCPLB))
return CACHE_ON;
else
return CACHE_OFF;
}

66
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/*
* U-boot - cpu.h
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _CPU_H_
#define _CPU_H_
#include <command.h>
#define INTERNAL_IRQS (32)
#define NUM_IRQ_NODES 16
#define DEF_INTERRUPT_FLAGS 1
#define MAX_TIM_LOAD 0xFFFFFFFF
void blackfin_irq_panic(int reason, struct pt_regs *reg);
extern void dump(struct pt_regs *regs);
void display_excp(void);
asmlinkage void evt_nmi(void);
asmlinkage void evt_exception(void);
asmlinkage void trap(void);
asmlinkage void evt_ivhw(void);
asmlinkage void evt_rst(void);
asmlinkage void evt_timer(void);
asmlinkage void evt_evt7(void);
asmlinkage void evt_evt8(void);
asmlinkage void evt_evt9(void);
asmlinkage void evt_evt10(void);
asmlinkage void evt_evt11(void);
asmlinkage void evt_evt12(void);
asmlinkage void evt_evt13(void);
asmlinkage void evt_soft_int1(void);
asmlinkage void evt_system_call(void);
void blackfin_irq_panic(int reason, struct pt_regs *regs);
void blackfin_free_irq(unsigned int irq, void *dev_id);
void call_isr(int irq, struct pt_regs *fp);
void blackfin_do_irq(int vec, struct pt_regs *fp);
void blackfin_init_IRQ(void);
void blackfin_enable_irq(unsigned int irq);
void blackfin_disable_irq(unsigned int irq);
extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
int blackfin_request_irq(unsigned int irq,
void (*handler) (int, void *, struct pt_regs *),
unsigned long flags, const char *devname,
void *dev_id);
void timer_init(void);
#endif

402
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/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
* Copyright (C) 2004 LG SOft India. All Rights Reserved.
*
* This file is subject to the terms and conditions of the GNU General Public
* License.
*/
#define ASSEMBLY
#include <asm/linkage.h>
#include <asm/cplb.h>
#include <config.h>
#include <asm/blackfin.h>
.text
/* This is an external function being called by the user
* application through __flush_cache_all. Currently this function
* serves the purpose of flushing all the pending writes in
* in the instruction cache.
*/
ENTRY(_flush_instruction_cache)
[--SP] = ( R7:6, P5:4 );
LINK 12;
SP += -12;
P5.H = (ICPLB_ADDR0 >> 16);
P5.L = (ICPLB_ADDR0 & 0xFFFF);
P4.H = (ICPLB_DATA0 >> 16);
P4.L = (ICPLB_DATA0 & 0xFFFF);
R7 = CPLB_VALID | CPLB_L1_CHBL;
R6 = 16;
inext: R0 = [P5++];
R1 = [P4++];
[--SP] = RETS;
CALL _icplb_flush; /* R0 = page, R1 = data*/
RETS = [SP++];
iskip: R6 += -1;
CC = R6;
IF CC JUMP inext;
SSYNC;
SP += 12;
UNLINK;
( R7:6, P5:4 ) = [SP++];
RTS;
/* This is an internal function to flush all pending
* writes in the cache associated with a particular ICPLB.
*
* R0 - page's start address
* R1 - CPLB's data field.
*/
.align 2
ENTRY(_icplb_flush)
[--SP] = ( R7:0, P5:0 );
[--SP] = LC0;
[--SP] = LT0;
[--SP] = LB0;
[--SP] = LC1;
[--SP] = LT1;
[--SP] = LB1;
/* If it's a 1K or 4K page, then it's quickest to
* just systematically flush all the addresses in
* the page, regardless of whether they're in the
* cache, or dirty. If it's a 1M or 4M page, there
* are too many addresses, and we have to search the
* cache for lines corresponding to the page.
*/
CC = BITTST(R1, 17); /* 1MB or 4MB */
IF !CC JUMP iflush_whole_page;
/* We're only interested in the page's size, so extract
* this from the CPLB (bits 17:16), and scale to give an
* offset into the page_size and page_prefix tables.
*/
R1 <<= 14;
R1 >>= 30;
R1 <<= 2;
/* We can also determine the sub-bank used, because this is
* taken from bits 13:12 of the address.
*/
R3 = ((12<<8)|2); /* Extraction pattern */
nop; /*Anamoly 05000209*/
R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/
/* So:
* R0 = Page start
* R1 = Page length (actually, offset into size/prefix tables)
* R3 = sub-bank deposit values
*
* The cache has 2 Ways, and 64 sets, so we iterate through
* the sets, accessing the tag for each Way, for our Bank and
* sub-bank, looking for dirty, valid tags that match our
* address prefix.
*/
P5.L = (ITEST_COMMAND & 0xFFFF);
P5.H = (ITEST_COMMAND >> 16);
P4.L = (ITEST_DATA0 & 0xFFFF);
P4.H = (ITEST_DATA0 >> 16);
P0.L = page_prefix_table;
P0.H = page_prefix_table;
P1 = R1;
R5 = 0; /* Set counter*/
P0 = P1 + P0;
R4 = [P0]; /* This is the address prefix*/
/* We're reading (bit 1==0) the tag (bit 2==0), and we
* don't care about which double-word, since we're only
* fetching tags, so we only have to set Set, Bank,
* Sub-bank and Way.
*/
P2 = 4;
LSETUP (ifs1, ife1) LC1 = P2;
ifs1: P0 = 32; /* iterate over all sets*/
LSETUP (ifs0, ife0) LC0 = P0;
ifs0: R6 = R5 << 5; /* Combine set*/
R6.H = R3.H << 0 ; /* and sub-bank*/
[P5] = R6; /* Issue Command*/
SSYNC; /* CSYNC will not work here :(*/
R7 = [P4]; /* and read Tag.*/
CC = BITTST(R7, 0); /* Check if valid*/
IF !CC JUMP ifskip; /* and skip if not.*/
/* Compare against the page address. First, plant bits 13:12
* into the tag, since those aren't part of the returned data.
*/
R7 = DEPOSIT(R7, R3); /* set 13:12*/
R1 = R7 & R4; /* Mask off lower bits*/
CC = R1 == R0; /* Compare against page start.*/
IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/
/* Tag address matches against page, so this is an entry
* we must flush.
*/
R7 >>= 10; /* Mask off the non-address bits*/
R7 <<= 10;
P3 = R7;
IFLUSH [P3]; /* And flush the entry*/
ifskip:
ife0: R5 += 1; /* Advance to next Set*/
ife1: NOP;
ifinished:
SSYNC; /* Ensure the data gets out to mem.*/
/*Finished. Restore context.*/
LB1 = [SP++];
LT1 = [SP++];
LC1 = [SP++];
LB0 = [SP++];
LT0 = [SP++];
LC0 = [SP++];
( R7:0, P5:0 ) = [SP++];
RTS;
iflush_whole_page:
/* It's a 1K or 4K page, so quicker to just flush the
* entire page.
*/
P1 = 32; /* For 1K pages*/
P2 = P1 << 2; /* For 4K pages*/
P0 = R0; /* Start of page*/
CC = BITTST(R1, 16); /* Whether 1K or 4K*/
IF CC P1 = P2;
P1 += -1; /* Unroll one iteration*/
SSYNC;
IFLUSH [P0++]; /* because CSYNC can't end loops.*/
LSETUP (isall, ieall) LC0 = P1;
isall:IFLUSH [P0++];
ieall: NOP;
SSYNC;
JUMP ifinished;
/* This is an external function being called by the user
* application through __flush_cache_all. Currently this function
* serves the purpose of flushing all the pending writes in
* in the data cache.
*/
ENTRY(_flush_data_cache)
[--SP] = ( R7:6, P5:4 );
LINK 12;
SP += -12;
P5.H = (DCPLB_ADDR0 >> 16);
P5.L = (DCPLB_ADDR0 & 0xFFFF);
P4.H = (DCPLB_DATA0 >> 16);
P4.L = (DCPLB_DATA0 & 0xFFFF);
R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
R6 = 16;
next: R0 = [P5++];
R1 = [P4++];
CC = BITTST(R1, 14); /* Is it write-through?*/
IF CC JUMP skip; /* If so, ignore it.*/
R2 = R1 & R7; /* Is it a dirty, cached page?*/
CC = R2;
IF !CC JUMP skip; /* If not, ignore it.*/
[--SP] = RETS;
CALL _dcplb_flush; /* R0 = page, R1 = data*/
RETS = [SP++];
skip: R6 += -1;
CC = R6;
IF CC JUMP next;
SSYNC;
SP += 12;
UNLINK;
( R7:6, P5:4 ) = [SP++];
RTS;
/* This is an internal function to flush all pending
* writes in the cache associated with a particular DCPLB.
*
* R0 - page's start address
* R1 - CPLB's data field.
*/
.align 2
ENTRY(_dcplb_flush)
[--SP] = ( R7:0, P5:0 );
[--SP] = LC0;
[--SP] = LT0;
[--SP] = LB0;
[--SP] = LC1;
[--SP] = LT1;
[--SP] = LB1;
/* If it's a 1K or 4K page, then it's quickest to
* just systematically flush all the addresses in
* the page, regardless of whether they're in the
* cache, or dirty. If it's a 1M or 4M page, there
* are too many addresses, and we have to search the
* cache for lines corresponding to the page.
*/
CC = BITTST(R1, 17); /* 1MB or 4MB */
IF !CC JUMP dflush_whole_page;
/* We're only interested in the page's size, so extract
* this from the CPLB (bits 17:16), and scale to give an
* offset into the page_size and page_prefix tables.
*/
R1 <<= 14;
R1 >>= 30;
R1 <<= 2;
/* The page could be mapped into Bank A or Bank B, depending
* on (a) whether both banks are configured as cache, and
* (b) on whether address bit A[x] is set. x is determined
* by DCBS in DMEM_CONTROL
*/
R2 = 0; /* Default to Bank A (Bank B would be 1)*/
P0.L = (DMEM_CONTROL & 0xFFFF);
P0.H = (DMEM_CONTROL >> 16);
R3 = [P0]; /* If Bank B is not enabled as cache*/
CC = BITTST(R3, 2); /* then Bank A is our only option.*/
IF CC JUMP bank_chosen;
R4 = 1<<14; /* If DCBS==0, use A[14].*/
R5 = R4 << 7; /* If DCBS==1, use A[23];*/
CC = BITTST(R3, 4);
IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
R5 = R0 & R4; /* Use it to test the Page address*/
CC = R5; /* and if that bit is set, we use Bank B,*/
R2 = CC; /* else we use Bank A.*/
R2 <<= 23; /* The Bank selection's at posn 23.*/
bank_chosen:
/* We can also determine the sub-bank used, because this is
* taken from bits 13:12 of the address.
*/
R3 = ((12<<8)|2); /* Extraction pattern */
nop; /*Anamoly 05000209*/
R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
/* Save in extraction pattern for later deposit.*/
R3.H = R4.L << 0;
/* So:
* R0 = Page start
* R1 = Page length (actually, offset into size/prefix tables)
* R2 = Bank select mask
* R3 = sub-bank deposit values
*
* The cache has 2 Ways, and 64 sets, so we iterate through
* the sets, accessing the tag for each Way, for our Bank and
* sub-bank, looking for dirty, valid tags that match our
* address prefix.
*/
P5.L = (DTEST_COMMAND & 0xFFFF);
P5.H = (DTEST_COMMAND >> 16);
P4.L = (DTEST_DATA0 & 0xFFFF);
P4.H = (DTEST_DATA0 >> 16);
P0.L = page_prefix_table;
P0.H = page_prefix_table;
P1 = R1;
R5 = 0; /* Set counter*/
P0 = P1 + P0;
R4 = [P0]; /* This is the address prefix*/
/* We're reading (bit 1==0) the tag (bit 2==0), and we
* don't care about which double-word, since we're only
* fetching tags, so we only have to set Set, Bank,
* Sub-bank and Way.
*/
P2 = 2;
LSETUP (fs1, fe1) LC1 = P2;
fs1: P0 = 64; /* iterate over all sets*/
LSETUP (fs0, fe0) LC0 = P0;
fs0: R6 = R5 << 5; /* Combine set*/
R6.H = R3.H << 0 ; /* and sub-bank*/
R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
BITSET(R6,14);
[P5] = R6; /* Issue Command*/
SSYNC;
R7 = [P4]; /* and read Tag.*/
CC = BITTST(R7, 0); /* Check if valid*/
IF !CC JUMP fskip; /* and skip if not.*/
CC = BITTST(R7, 1); /* Check if dirty*/
IF !CC JUMP fskip; /* and skip if not.*/
/* Compare against the page address. First, plant bits 13:12
* into the tag, since those aren't part of the returned data.
*/
R7 = DEPOSIT(R7, R3); /* set 13:12*/
R1 = R7 & R4; /* Mask off lower bits*/
CC = R1 == R0; /* Compare against page start.*/
IF !CC JUMP fskip; /* Skip it if it doesn't match.*/
/* Tag address matches against page, so this is an entry
* we must flush.
*/
R7 >>= 10; /* Mask off the non-address bits*/
R7 <<= 10;
P3 = R7;
SSYNC;
FLUSHINV [P3]; /* And flush the entry*/
fskip:
fe0: R5 += 1; /* Advance to next Set*/
fe1: BITSET(R2, 26); /* Go to next Way.*/
dfinished:
SSYNC; /* Ensure the data gets out to mem.*/
/*Finished. Restore context.*/
LB1 = [SP++];
LT1 = [SP++];
LC1 = [SP++];
LB0 = [SP++];
LT0 = [SP++];
LC0 = [SP++];
( R7:0, P5:0 ) = [SP++];
RTS;
dflush_whole_page:
/* It's a 1K or 4K page, so quicker to just flush the
* entire page.
*/
P1 = 32; /* For 1K pages*/
P2 = P1 << 2; /* For 4K pages*/
P0 = R0; /* Start of page*/
CC = BITTST(R1, 16); /* Whether 1K or 4K*/
IF CC P1 = P2;
P1 += -1; /* Unroll one iteration*/
SSYNC;
FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
LSETUP (eall, eall) LC0 = P1;
eall: FLUSHINV [P0++];
SSYNC;
JUMP dfinished;
.align 4;
page_prefix_table:
.byte4 0xFFFFFC00; /* 1K */
.byte4 0xFFFFF000; /* 4K */
.byte4 0xFFF00000; /* 1M */
.byte4 0xFFC00000; /* 4M */
.page_prefix_table.end:

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#define ASSEMBLY
#include <linux/config.h>
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mem_init.h>
.global init_sdram;
#if (CONFIG_CCLK_DIV == 1)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
#endif
#if (CONFIG_CCLK_DIV == 2)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
#endif
#if (CONFIG_CCLK_DIV == 4)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
#endif
#if (CONFIG_CCLK_DIV == 8)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
#endif
#ifndef CONFIG_CCLK_ACT_DIV
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
#endif
init_sdram:
[--SP] = ASTAT;
[--SP] = RETS;
[--SP] = (R7:0);
[--SP] = (P5:0);
/*
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
*/
p0.h = hi(PLL_LOCKCNT);
p0.l = lo(PLL_LOCKCNT);
r0 = 0x300(Z);
w[p0] = r0.l;
ssync;
/*
* Put SDRAM in self-refresh, incase anything is running
*/
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITSET (R0, 24);
[P2] = R0;
SSYNC;
/*
* Set PLL_CTL with the value that we calculate in R0
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
* - [7] = output delay (add 200ps of delay to mem signals)
* - [6] = input delay (add 200ps of input delay to mem signals)
* - [5] = PDWN : 1=All Clocks off
* - [3] = STOPCK : 1=Core Clock off
* - [1] = PLL_OFF : 1=Disable Power to PLL
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
* all other bits set to zero
*/
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over, */
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */
r0 = r1 | r0;
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */
cli r2; /* Disable interrupts */
ssync;
w[p0] = r0.l; /* Set the value */
idle; /* Wait for the PLL to stablize */
sti r2; /* Enable interrupts */
check_again:
p0.h = hi(PLL_STAT);
p0.l = lo(PLL_STAT);
R0 = W[P0](Z);
CC = BITTST(R0,5);
if ! CC jump check_again;
/* Configure SCLK & CCLK Dividers */
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
p0.h = hi(PLL_DIV);
p0.l = lo(PLL_DIV);
w[p0] = r0.l;
ssync;
/*
* We now are running at speed, time to set the Async mem bank wait states
* This will speed up execution, since we are normally running from FLASH.
*/
p2.h = (EBIU_AMBCTL1 >> 16);
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
r0.h = (AMBCTL1VAL >> 16);
r0.l = (AMBCTL1VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMBCTL0 >> 16);
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
r0.h = (AMBCTL0VAL >> 16);
r0.l = (AMBCTL0VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMGCTL >> 16);
p2.l = (EBIU_AMGCTL & 0xffff);
r0 = AMGCTLVAL;
w[p2] = r0;
ssync;
/*
* Now, Initialize the SDRAM,
* start with the SDRAM Refresh Rate Control Register
*/
p0.l = lo(EBIU_SDRRC);
p0.h = hi(EBIU_SDRRC);
r0 = mem_SDRRC;
w[p0] = r0.l;
ssync;
/*
* SDRAM Memory Bank Control Register - bank specific parameters
*/
p0.l = (EBIU_SDBCTL & 0xFFFF);
p0.h = (EBIU_SDBCTL >> 16);
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
/*
* SDRAM Global Control Register - global programmable parameters
* Disable self-refresh
*/
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITCLR (R0, 24);
/*
* Check if SDRAM is already powered up, if it is, enable self-refresh
*/
p0.h = hi(EBIU_SDSTAT);
p0.l = lo(EBIU_SDSTAT);
r2.l = w[p0];
cc = bittst(r2,3);
if !cc jump skip;
NOP;
BITSET (R0, 23);
skip:
[P2] = R0;
SSYNC;
/* Write in the new value in the register */
R0.L = lo(mem_SDGCTL);
R0.H = hi(mem_SDGCTL);
[P2] = R0;
SSYNC;
nop;
(P5:0) = [SP++];
(R7:0) = [SP++];
RETS = [SP++];
ASTAT = [SP++];
RTS;

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cpu/bf561/init_sdram_bootrom_initblock.S Normal file
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#define ASSEMBLY
#include <linux/config.h>
#include <config.h>
#include <asm/blackfin.h>
#include <asm/mem_init.h>
.global init_sdram;
#if (CONFIG_CCLK_DIV == 1)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
#endif
#if (CONFIG_CCLK_DIV == 2)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
#endif
#if (CONFIG_CCLK_DIV == 4)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
#endif
#if (CONFIG_CCLK_DIV == 8)
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
#endif
#ifndef CONFIG_CCLK_ACT_DIV
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
#endif
init_sdram:
[--SP] = ASTAT;
[--SP] = RETS;
[--SP] = (R7:0);
[--SP] = (P5:0);
p0.h = hi(SICA_IWR0);
p0.l = lo(SICA_IWR0);
r0.l = 0x1;
w[p0] = r0.l;
SSYNC;
p0.h = hi(SPI_BAUD);
p0.l = lo(SPI_BAUD);
r0.l = CONFIG_SPI_BAUD_INITBLOCK;
w[p0] = r0.l;
SSYNC;
/*
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
*/
p0.h = hi(PLL_LOCKCNT);
p0.l = lo(PLL_LOCKCNT);
r0 = 0x300(Z);
w[p0] = r0.l;
ssync;
/*
* Put SDRAM in self-refresh, incase anything is running
*/
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITSET (R0, 24);
[P2] = R0;
SSYNC;
/*
* Set PLL_CTL with the value that we calculate in R0
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
* - [7] = output delay (add 200ps of delay to mem signals)
* - [6] = input delay (add 200ps of input delay to mem signals)
* - [5] = PDWN : 1=All Clocks off
* - [3] = STOPCK : 1=Core Clock off
* - [1] = PLL_OFF : 1=Disable Power to PLL
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
* all other bits set to zero
*/
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over, */
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */
r0 = r1 | r0;
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */
cli r2; /* Disable interrupts */
ssync;
w[p0] = r0.l; /* Set the value */
idle; /* Wait for the PLL to stablize */
sti r2; /* Enable interrupts */
check_again:
p0.h = hi(PLL_STAT);
p0.l = lo(PLL_STAT);
R0 = W[P0](Z);
CC = BITTST(R0,5);
if ! CC jump check_again;
/* Configure SCLK & CCLK Dividers */
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
p0.h = hi(PLL_DIV);
p0.l = lo(PLL_DIV);
w[p0] = r0.l;
ssync;
/*
* We now are running at speed, time to set the Async mem bank wait states
* This will speed up execution, since we are normally running from FLASH.
*/
p2.h = (EBIU_AMBCTL1 >> 16);
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
r0.h = (AMBCTL1VAL >> 16);
r0.l = (AMBCTL1VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMBCTL0 >> 16);
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
r0.h = (AMBCTL0VAL >> 16);
r0.l = (AMBCTL0VAL & 0xFFFF);
[p2] = r0;
ssync;
p2.h = (EBIU_AMGCTL >> 16);
p2.l = (EBIU_AMGCTL & 0xffff);
r0 = AMGCTLVAL;
w[p2] = r0;
ssync;
/*
* Now, Initialize the SDRAM,
* start with the SDRAM Refresh Rate Control Register
*/
p0.l = lo(EBIU_SDRRC);
p0.h = hi(EBIU_SDRRC);
r0 = mem_SDRRC;
w[p0] = r0.l;
ssync;
/*
* SDRAM Memory Bank Control Register - bank specific parameters
*/
p0.l = (EBIU_SDBCTL & 0xFFFF);
p0.h = (EBIU_SDBCTL >> 16);
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
/*
* SDRAM Global Control Register - global programmable parameters
* Disable self-refresh
*/
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITCLR (R0, 24);
/*
* Check if SDRAM is already powered up, if it is, enable self-refresh
*/
p0.h = hi(EBIU_SDSTAT);
p0.l = lo(EBIU_SDSTAT);
r2.l = w[p0];
cc = bittst(r2,3);
if !cc jump skip;
NOP;
BITSET (R0, 23);
skip:
[P2] = R0;
SSYNC;
/* Write in the new value in the register */
R0.L = lo(mem_SDGCTL);
R0.H = hi(mem_SDGCTL);
[P2] = R0;
SSYNC;
nop;
(P5:0) = [SP++];
(R7:0) = [SP++];
RETS = [SP++];
ASTAT = [SP++];
RTS;

246
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/*
* U-boot - interrupt.S Processing of interrupts and exception handling
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This file is based on interrupt.S
*
* Copyright (C) 2003 Metrowerks, Inc. <mwaddel@metrowerks.com>
* Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma <mated@sympatico.ca>
* Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
* Kenneth Albanowski <kjahds@kjahds.com>,
* The Silver Hammer Group, Ltd.
*
* (c) 1995, Dionne & Associates
* (c) 1995, DKG Display Tech.
*
* This file is also based on exception.asm
* (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define ASSEMBLY
#include <config.h>
#include <asm/blackfin.h>
#include <asm/hw_irq.h>
#include <asm/entry.h>
#include <asm/blackfin_defs.h>
.global _blackfin_irq_panic;
.text
.align 2
#ifndef CONFIG_KGDB
.global _evt_emulation
_evt_emulation:
SAVE_CONTEXT
r0 = IRQ_EMU;
r1 = seqstat;
sp += -12;
call _blackfin_irq_panic;
sp += 12;
rte;
#endif
.global _evt_nmi
_evt_nmi:
SAVE_CONTEXT
r0 = IRQ_NMI;
r1 = RETN;
sp += -12;
call _blackfin_irq_panic;
sp += 12;
_evt_nmi_exit:
rtn;
.global _trap
_trap:
SAVE_ALL_SYS
r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
sp += -12;
call _trap_c
sp += 12;
RESTORE_ALL_SYS
rtx;
.global _evt_rst
_evt_rst:
SAVE_CONTEXT
r0 = IRQ_RST;
r1 = RETN;
sp += -12;
call _do_reset;
sp += 12;
_evt_rst_exit:
rtn;
irq_panic:
r0 = IRQ_EVX;
r1 = sp;
sp += -12;
call _blackfin_irq_panic;
sp += 12;
.global _evt_ivhw
_evt_ivhw:
SAVE_CONTEXT
RAISE 14;
_evt_ivhw_exit:
rti;
.global _evt_timer
_evt_timer:
SAVE_CONTEXT
r0 = IRQ_CORETMR;
sp += -12;
/* Polling method used now. */
/* call timer_int; */
sp += 12;
RESTORE_CONTEXT
rti;
nop;
.global _evt_evt7
_evt_evt7:
SAVE_CONTEXT
r0 = 7;
sp += -12;
call _process_int;
sp += 12;
evt_evt7_exit:
RESTORE_CONTEXT
rti;
.global _evt_evt8
_evt_evt8:
SAVE_CONTEXT
r0 = 8;
sp += -12;
call _process_int;
sp += 12;
evt_evt8_exit:
RESTORE_CONTEXT
rti;
.global _evt_evt9
_evt_evt9:
SAVE_CONTEXT
r0 = 9;
sp += -12;
call _process_int;
sp += 12;
evt_evt9_exit:
RESTORE_CONTEXT
rti;
.global _evt_evt10
_evt_evt10:
SAVE_CONTEXT
r0 = 10;
sp += -12;
call _process_int;
sp += 12;
evt_evt10_exit:
RESTORE_CONTEXT
rti;
.global _evt_evt11
_evt_evt11:
SAVE_CONTEXT
r0 = 11;
sp += -12;
call _process_int;
sp += 12;
evt_evt11_exit:
RESTORE_CONTEXT
rti;
.global _evt_evt12
_evt_evt12:
SAVE_CONTEXT
r0 = 12;
sp += -12;
call _process_int;
sp += 12;
evt_evt12_exit:
RESTORE_CONTEXT
rti;
.global _evt_evt13
_evt_evt13:
SAVE_CONTEXT
r0 = 13;
sp += -12;
call _process_int;
sp += 12;
evt_evt13_exit:
RESTORE_CONTEXT
rti;
.global _evt_system_call
_evt_system_call:
[--sp] = r0;
[--SP] = RETI;
r0 = [sp++];
r0 += 2;
[--sp] = r0;
RETI = [SP++];
r0 = [SP++];
SAVE_CONTEXT
sp += -12;
call _exception_handle;
sp += 12;
RESTORE_CONTEXT
RTI;
evt_system_call_exit:
rti;
.global _evt_soft_int1
_evt_soft_int1:
[--sp] = r0;
[--SP] = RETI;
r0 = [sp++];
r0 += 2;
[--sp] = r0;
RETI = [SP++];
r0 = [SP++];
SAVE_CONTEXT
sp += -12;
call _exception_handle;
sp += 12;
RESTORE_CONTEXT
RTI;
evt_soft_int1_exit:
rti;

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/*
* U-boot - interrupts.c Interrupt related routines
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* This file is based on interrupts.c
* Copyright 1996 Roman Zippel
* Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
* Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
* Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
* Copyright 2003 Metrowerks/Motorola
* Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
* BuyWays B.V. (www.buyways.nl)
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/machdep.h>
#include <asm/irq.h>
#include <config.h>
#include <asm/blackfin.h>
#include "cpu.h"
static ulong timestamp;
static ulong last_time;
static int int_flag;
int irq_flags; /* needed by asm-blackfin/system.h */
/* Functions just to satisfy the linker */
/*
* This function is derived from PowerPC code (read timebase as long long).
* On BF561 it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On BF561 it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
ulong tbclk;
tbclk = CFG_HZ;
return tbclk;
}
void enable_interrupts(void)
{
restore_flags(int_flag);
}
int disable_interrupts(void)
{
save_and_cli(int_flag);
return 1;
}
int interrupt_init(void)
{
return (0);
}
void udelay(unsigned long usec)
{
unsigned long delay, start, stop;
unsigned long cclk;
cclk = (CONFIG_CCLK_HZ);
while (usec > 1) {
/*
* how many clock ticks to delay?
* - request(in useconds) * clock_ticks(Hz) / useconds/second
*/
if (usec < 1000) {
delay = (usec * (cclk / 244)) >> 12;
usec = 0;
} else {
delay = (1000 * (cclk / 244)) >> 12;
usec -= 1000;
}
asm volatile (" %0 = CYCLES;":"=r" (start));
do {
asm volatile (" %0 = CYCLES; ":"=r" (stop));
} while (stop - start < delay);
}
return;
}
void timer_init(void)
{
*pTCNTL = 0x1;
*pTSCALE = 0x0;
*pTCOUNT = MAX_TIM_LOAD;
*pTPERIOD = MAX_TIM_LOAD;
*pTCNTL = 0x7;
asm("CSYNC;");
timestamp = 0;
last_time = 0;
}
/*
* Any network command or flash
* command is started get_timer shall
* be called before TCOUNT gets reset,
* to implement the accurate timeouts.
*
* How ever milliconds doesn't return
* the number that has been elapsed from
* the last reset.
*
* As get_timer is used in the u-boot
* only for timeouts this should be
* sufficient
*/
ulong get_timer(ulong base)
{
ulong milisec;
/* Number of clocks elapsed */
ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
/*
* Find if the TCOUNT is reset
* timestamp gives the number of times
* TCOUNT got reset
*/
if (clocks < last_time)
timestamp++;
last_time = clocks;
/* Get the number of milliseconds */
milisec = clocks / (CONFIG_CCLK_HZ / 1000);
/*
* Find the number of millisonds
* that got elapsed before this TCOUNT
* cycle
*/
milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
return (milisec - base);
}

117
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/*
* U-boot - ints.c Interrupt related routines
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* This file is based on ints.c
*
* Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin
* drivers
*
* Copyright 1996 Roman Zippel
* Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
* Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
* Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
* Copyright 2003 Metrowerks/Motorola
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/stddef.h>
#include <asm/system.h>
#include <asm/irq.h>
#include <asm/traps.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/machdep.h>
#include <asm/setup.h>
#include <asm/blackfin.h>
#include "cpu.h"
void blackfin_irq_panic(int reason, struct pt_regs *regs)
{
printf("\n\nException: IRQ 0x%x entered\n", reason);
printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
printf("stack frame=0x%x, ", (unsigned int)regs);
printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
dump(regs);
printf("Unhandled IRQ or exceptions!\n");
printf("Please reset the board \n");
}
void blackfin_init_IRQ(void)
{
*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
cli();
#ifndef CONFIG_KGDB
*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
#endif
*(unsigned volatile long *)(EVT_NMI_ADDR) =
(unsigned volatile long)evt_nmi;
*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
(unsigned volatile long)trap;
*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
(unsigned volatile long)evt_ivhw;
*(unsigned volatile long *)(EVT_RESET_ADDR) =
(unsigned volatile long)evt_rst;
*(unsigned volatile long *)(EVT_TIMER_ADDR) =
(unsigned volatile long)evt_timer;
*(unsigned volatile long *)(EVT_IVG7_ADDR) =
(unsigned volatile long)evt_evt7;
*(unsigned volatile long *)(EVT_IVG8_ADDR) =
(unsigned volatile long)evt_evt8;
*(unsigned volatile long *)(EVT_IVG9_ADDR) =
(unsigned volatile long)evt_evt9;
*(unsigned volatile long *)(EVT_IVG10_ADDR) =
(unsigned volatile long)evt_evt10;
*(unsigned volatile long *)(EVT_IVG11_ADDR) =
(unsigned volatile long)evt_evt11;
*(unsigned volatile long *)(EVT_IVG12_ADDR) =
(unsigned volatile long)evt_evt12;
*(unsigned volatile long *)(EVT_IVG13_ADDR) =
(unsigned volatile long)evt_evt13;
*(unsigned volatile long *)(EVT_IVG14_ADDR) =
(unsigned volatile long)evt_system_call;
*(unsigned volatile long *)(EVT_IVG15_ADDR) =
(unsigned volatile long)evt_soft_int1;
*(volatile unsigned long *)ILAT = 0;
asm("csync;");
sti();
*(volatile unsigned long *)IMASK = 0xffbf;
asm("csync;");
}
void exception_handle(void)
{
#if defined (CONFIG_PANIC_HANG)
display_excp();
#else
udelay(100000); /* allow messages to go out */
do_reset(NULL, 0, 0, NULL);
#endif
}
void display_excp(void)
{
printf("Exception!\n");
}

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/*
* U-boot - serial.c Serial driver for BF561
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* This file is based on
* bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART.
* Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
* BuyWays B.V. (www.buyways.nl)
*
* Based heavily on blkfinserial.c
* blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
* Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
* Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
* Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
*
* Based on code from 68328 version serial driver imlpementation which was:
* Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
* Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
* Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/segment.h>
#include <asm/bitops.h>
#include <asm/delay.h>
#include <asm/uaccess.h>
#include "serial.h"
#include <asm/io.h>
unsigned long pll_div_fact;
void calc_baud(void)
{
unsigned char i;
int temp;
u_long sclk = get_sclk();
for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
temp = sclk / (baud_table[i] * 8);
if ((temp & 0x1) == 1) {
temp++;
}
temp = temp / 2;
hw_baud_table[i].dl_high = (temp >> 8) & 0xFF;
hw_baud_table[i].dl_low = (temp) & 0xFF;
}
}
void serial_setbrg(void)
{
int i;
DECLARE_GLOBAL_DATA_PTR;
calc_baud();
for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
if (gd->baudrate == baud_table[i])
break;
}
/* Enable UART */
*pUART_GCTL |= UART_GCTL_UCEN;
sync();
/* Set DLAB in LCR to Access DLL and DLH */
ACCESS_LATCH;
sync();
*pUART_DLL = hw_baud_table[i].dl_low;
sync();
*pUART_DLH = hw_baud_table[i].dl_high;
sync();
/* Clear DLAB in LCR to Access THR RBR IER */
ACCESS_PORT_IER;
sync();
/*
* Enable ERBFI and ELSI interrupts
* to poll SIC_ISR register
*/
*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
sync();
/* Set LCR to Word Lengh 8-bit word select */
*pUART_LCR = UART_LCR_WLS8;
sync();
return;
}
int serial_init(void)
{
serial_setbrg();
return (0);
}
void serial_putc(const char c)
{
if ((*pUART_LSR) & UART_LSR_TEMT) {
if (c == '\n')
serial_putc('\r');
local_put_char(c);
}
while (!((*pUART_LSR) & UART_LSR_TEMT))
SYNC_ALL;
return;
}
int serial_tstc(void)
{
if (*pUART_LSR & UART_LSR_DR)
return 1;
else
return 0;
}
int serial_getc(void)
{
unsigned short uart_lsr_val, uart_rbr_val;
unsigned long isr_val;
int ret;
/* Poll for RX Interrupt */
while (!((isr_val =
*(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
asm("csync;");
uart_lsr_val = *pUART_LSR; /* Clear status bit */
uart_rbr_val = *pUART_RBR; /* getc() */
if (isr_val & IRQ_UART_ERROR_BIT) {
ret = -1;
} else {
ret = uart_rbr_val & 0xff;
}
return ret;
}
void serial_puts(const char *s)
{
while (*s) {
serial_putc(*s++);
}
}
static void local_put_char(char ch)
{
int flags = 0;
unsigned long isr_val;
save_and_cli(flags);
/* Poll for TX Interruput */
while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
asm("csync;");
*pUART_THR = ch; /* putc() */
if (isr_val & IRQ_UART_ERROR_BIT) {
printf("?");
}
restore_flags(flags);
return;
}

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/*
* U-boot - bf561_serial.h Serial Driver defines
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* This file is based on
* bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
* Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl>
* BuyWays B.V. (www.buyways.nl)
*
* Based heavily on:
* blkfinserial.h: Definitions for the BlackFin DSP serial driver.
*
* Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com
* Copyright (C) 2001 Arcturus Networks Inc. <www.arcturusnetworks.com>
*
* Based on code from 68328serial.c which was:
* Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
* Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
* Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _Bf561_SERIAL_H
#define _Bf561_SERIAL_H
#include <linux/config.h>
#include <asm/blackfin.h>
#define SYNC_ALL __asm__ __volatile__ ("ssync;\n")
#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB;
#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB);
void serial_setbrg(void);
static void local_put_char(char ch);
void calc_baud(void);
void serial_setbrg(void);
int serial_init(void);
void serial_putc(const char c);
int serial_tstc(void);
int serial_getc(void);
void serial_puts(const char *s);
static void local_put_char(char ch);
int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
struct {
unsigned char dl_high;
unsigned char dl_low;
} hw_baud_table[5];
#ifdef CONFIG_STAMP
extern unsigned long pll_div_fact;
#endif
#endif

311
cpu/bf561/start.S Normal file
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@ -0,0 +1,311 @@
/*
* U-boot - start.S Startup file of u-boot for BF533/BF561
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* This file is based on head.S
* Copyright (c) 2003 Metrowerks/Motorola
* Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
* Kenneth Albanowski <kjahds@kjahds.com>,
* The Silver Hammer Group, Ltd.
* (c) 1995, Dionne & Associates
* (c) 1995, DKG Display Tech.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Note: A change in this file subsequently requires a change in
* board/$(board_name)/config.mk for a valid u-boot.bin
*/
#define ASSEMBLY
#include <linux/config.h>
#include <config.h>
#include <asm/blackfin.h>
.global _stext;
.global __bss_start;
.global start;
.global _start;
.global _rambase;
.global _ramstart;
.global _ramend;
.global edata;
.global _initialize;
.global _exit;
.global flashdataend;
.global init_sdram;
.text
_start:
start:
_stext:
R0 = 0x32;
SYSCFG = R0;
SSYNC;
/*
* As per HW reference manual DAG registers,
* DATA and Address resgister shall be zero'd
* in initialization, after a reset state
*/
r1 = 0; /* Data registers zero'd */
r2 = 0;
r3 = 0;
r4 = 0;
r5 = 0;
r6 = 0;
r7 = 0;
p0 = 0; /* Address registers zero'd */
p1 = 0;
p2 = 0;
p3 = 0;
p4 = 0;
p5 = 0;
i0 = 0; /* DAG Registers zero'd */
i1 = 0;
i2 = 0;
i3 = 0;
m0 = 0;
m1 = 0;
m3 = 0;
m3 = 0;
l0 = 0;
l1 = 0;
l2 = 0;
l3 = 0;
b0 = 0;
b1 = 0;
b2 = 0;
b3 = 0;
/*
* Set loop counters to zero, to make sure that
* hw loops are disabled.
*/
r0 = 0;
lc0 = r0;
lc1 = r0;
SSYNC;
/* Check soft reset status */
p0.h = SWRST >> 16;
p0.l = SWRST & 0xFFFF;
r0.l = w[p0];
cc = bittst(r0, 15);
if !cc jump no_soft_reset;
/* Clear Soft reset */
r0 = 0x0000;
w[p0] = r0;
ssync;
no_soft_reset:
nop;
/* Clear EVT registers */
p0.h = (EVT_EMULATION_ADDR >> 16);
p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
p0 += 8;
p1 = 14;
r1 = 0;
LSETUP(4,4) lc0 = p1;
[ p0 ++ ] = r1;
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
r0.l = 0x1;
w[p0] = r0.l;
SSYNC;
sp.l = (0xffb01000 & 0xFFFF);
sp.h = (0xffb01000 >> 16);
/*
* Check if the code is in SDRAM
* If the code is in SDRAM, skip SDRAM initializaiton
*/
call get_pc;
r3.l = 0x0;
r3.h = 0x2000;
cc = r0 < r3 (iu);
if cc jump sdram_initialized;
call init_sdram;
/* relocate into to RAM */
sdram_initialized:
call get_pc;
offset:
r2.l = offset;
r2.h = offset;
r3.l = start;
r3.h = start;
r1 = r2 - r3;
r0 = r0 - r1;
p1 = r0;
p2.l = (CFG_MONITOR_BASE & 0xffff);
p2.h = (CFG_MONITOR_BASE >> 16);
p3 = 0x04;
p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
loop1:
r1 = [p1 ++ p3];
[p2 ++ p3] = r1;
cc=p2==p4;
if !cc jump loop1;
/*
* configure STACK
*/
r0.h = (CONFIG_STACKBASE >> 16);
r0.l = (CONFIG_STACKBASE & 0xFFFF);
sp = r0;
fp = sp;
/*
* This next section keeps the processor in supervisor mode
* during kernel boot. Switches to user mode at end of boot.
* See page 3-9 of Hardware Reference manual for documentation.
*/
/* To keep ourselves in the supervisor mode */
p0.l = (EVT_IVG15_ADDR & 0xFFFF);
p0.h = (EVT_IVG15_ADDR >> 16);
p1.l = _real_start;
p1.h = _real_start;
[p0] = p1;
p0.l = (IMASK & 0xFFFF);
p0.h = (IMASK >> 16);
r0.l = LO(IVG15_POS);
r0.h = HI(IVG15_POS);
[p0] = r0;
raise 15;
p0.l = WAIT_HERE;
p0.h = WAIT_HERE;
reti = p0;
rti;
WAIT_HERE:
jump WAIT_HERE;
.global _real_start;
_real_start:
[ -- sp ] = reti;
#ifdef CONFIG_EZKIT561
p0.l = (WDOG_CTL & 0xFFFF);
p0.h = (WDOG_CTL >> 16);
r0 = WATCHDOG_DISABLE(z);
w[p0] = r0;
#endif
/* DMA reset code to Hi of L1 SRAM */
copy:
P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
P1.L = lo(SYSMMR_BASE);
R0.H = reset_start; /* Source Address (high) */
R0.L = reset_start; /* Source Address (low) */
R1.H = reset_end;
R1.L = reset_end;
R2 = R1 - R0; /* Count */
R1.H = hi(L1_ISRAM); /* Destination Address (high) */
R1.L = lo(L1_ISRAM); /* Destination Address (low) */
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
DMA:
R6 = 0x1 (Z);
W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
/* Set Source DMAConfig = DMA Enable,
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
/* Set Destination DMAConfig = DMA Enable,
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
WAIT_DMA_DONE:
p0.h = hi(MDMA_D0_IRQ_STATUS);
p0.l = lo(MDMA_D0_IRQ_STATUS);
R0 = W[P0](Z);
CC = BITTST(R0, 0);
if ! CC jump WAIT_DMA_DONE
R0 = 0x1;
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
/* Initialize BSS Section with 0 s */
p1.l = __bss_start;
p1.h = __bss_start;
p2.l = _end;
p2.h = _end;
r1 = p1;
r2 = p2;
r3 = r2 - r1;
r3 = r3 >> 2;
p3 = r3;
lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
CC = p2<=p1;
if CC jump _clear_bss_skip;
r0 = 0;
_clear_bss:
_clear_bss_end:
[p1++] = r0;
_clear_bss_skip:
p0.l = _start1;
p0.h = _start1;
jump (p0);
reset_start:
p0.h = WDOG_CNT >> 16;
p0.l = WDOG_CNT & 0xffff;
r0 = 0x0010;
w[p0] = r0;
p0.h = WDOG_CTL >> 16;
p0.l = WDOG_CTL & 0xffff;
r0 = 0x0000;
w[p0] = r0;
reset_wait:
jump reset_wait;
reset_end: nop;
_exit:
jump.s _exit;
get_pc:
r0 = rets;
rts;

40
post/codec.c → cpu/bf561/start1.S
View file

@ -1,6 +1,7 @@
/*
* (C) Copyright 2004
* Pantelis Antoniou, Intracom S.A. , panto@intracom.gr
* U-boot - start1.S Code running out of RAM after relocation
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* See file CREDITS for list of people who contributed to this
* project.
@ -21,28 +22,17 @@
* MA 02111-1307 USA
*/
#include <common.h>
#define ASSEMBLY
#include <linux/config.h>
#include <config.h>
#include <asm/blackfin.h>
/*
* CODEC test
*
* This test verifies the connection and performs a memory test
* on any connected codec(s). The meat of the work is done
* in the board specific function.
*/
.global start1;
.global _start1;
#ifdef CONFIG_POST
#include <post.h>
#if CONFIG_POST & CFG_POST_CODEC
extern int board_post_codec(int flags);
int codec_post_test (int flags)
{
return board_post_codec(flags);
}
#endif /* CONFIG_POST & CFG_POST_CODEC */
#endif /* CONFIG_POST */
.text
_start1:
start1:
sp += -12;
call _board_init_f;
sp += 12;

239
cpu/bf561/traps.c Normal file
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@ -0,0 +1,239 @@
/*
* U-boot - traps.c Routines related to interrupts and exceptions
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* This file is based on
* No original Copyright holder listed,
* Probabily original (C) Roman Zippel (assigned DJD, 1999)
*
* Copyright 2003 Metrowerks - for Blackfin
* Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
* Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/types.h>
#include <asm/errno.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/machdep.h>
#include "cpu.h"
#include <asm/arch/anomaly.h>
#include <asm/cplb.h>
#include <asm/io.h>
void init_IRQ(void)
{
blackfin_init_IRQ();
return;
}
void process_int(unsigned long vec, struct pt_regs *fp)
{
printf("interrupt\n");
return;
}
extern unsigned int icplb_table[page_descriptor_table_size][2];
extern unsigned int dcplb_table[page_descriptor_table_size][2];
unsigned long last_cplb_fault_retx;
static unsigned int cplb_sizes[4] =
{ 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
void trap_c(struct pt_regs *regs)
{
unsigned int addr;
unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
unsigned int i, j, size, *I0, *I1;
unsigned short data = 0;
switch (trapnr) {
/* 0x26 - Data CPLB Miss */
case VEC_CPLB_M:
#ifdef ANOMALY_05000261
/*
* Work around an anomaly: if we see a new DCPLB fault, return
* without doing anything. Then, if we get the same fault again,
* handle it.
*/
addr = last_cplb_fault_retx;
last_cplb_fault_retx = regs->retx;
printf("this time, curr = 0x%08x last = 0x%08x\n", addr,
last_cplb_fault_retx);
if (addr != last_cplb_fault_retx)
goto trap_c_return;
#endif
data = 1;
case VEC_CPLB_I_M:
if (data)
addr = *pDCPLB_FAULT_ADDR;
else
addr = *pICPLB_FAULT_ADDR;
for (i = 0; i < page_descriptor_table_size; i++) {
if (data) {
size = cplb_sizes[dcplb_table[i][1] >> 16];
j = dcplb_table[i][0];
} else {
size = cplb_sizes[icplb_table[i][1] >> 16];
j = icplb_table[i][0];
}
if ((j <= addr) && ((j + size) > addr)) {
debug("found %i 0x%08x\n", i, j);
break;
}
}
if (i == page_descriptor_table_size) {
printf("something is really wrong\n");
do_reset(NULL, 0, 0, NULL);
}
/* Turn the cache off */
if (data) {
sync();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL &=
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
sync();
} else {
sync();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
sync();
}
if (data) {
I0 = (unsigned int *)DCPLB_ADDR0;
I1 = (unsigned int *)DCPLB_DATA0;
} else {
I0 = (unsigned int *)ICPLB_ADDR0;
I1 = (unsigned int *)ICPLB_DATA0;
}
j = 0;
while (*I1 & CPLB_LOCK) {
debug("skipping %i %08p - %08x\n", j, I1, *I1);
*I0++;
*I1++;
j++;
}
debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
for (; j < 15; j++) {
debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
*I0++ = *(I0 + 1);
*I1++ = *(I1 + 1);
}
if (data) {
*I0 = dcplb_table[i][0];
*I1 = dcplb_table[i][1];
I0 = (unsigned int *)DCPLB_ADDR0;
I1 = (unsigned int *)DCPLB_DATA0;
} else {
*I0 = icplb_table[i][0];
*I1 = icplb_table[i][1];
I0 = (unsigned int *)ICPLB_ADDR0;
I1 = (unsigned int *)ICPLB_DATA0;
}
for (j = 0; j < 16; j++) {
debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
}
/* Turn the cache back on */
if (data) {
j = *(unsigned int *)DMEM_CONTROL;
sync();
asm(" .align 8; ");
*(unsigned int *)DMEM_CONTROL =
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
sync();
} else {
sync();
asm(" .align 8; ");
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
sync();
}
break;
default:
/* All traps come here */
printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
printf("stack frame=0x%x, ", (unsigned int)regs);
printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
dump(regs);
printf("\n\n");
printf("Unhandled IRQ or exceptions!\n");
printf("Please reset the board \n");
do_reset(NULL, 0, 0, NULL);
}
trap_c_return:
return;
}
void dump(struct pt_regs *fp)
{
debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n", fp->rete,
fp->retn, fp->retx, fp->rets);
debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n", fp->r0,
fp->r1, fp->r2, fp->r3);
debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", fp->r4,
fp->r5, fp->r6, fp->r7);
debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n", fp->p0,
fp->p1, fp->p2, fp->p3);
debug("P4: %08lx P5: %08lx FP: %08lx\n", fp->p4, fp->p5, fp->fp);
debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
fp->a0w, fp->a0x, fp->a1w, fp->a1x);
debug("LB0: %08lx LT0: %08lx LC0: %08lx\n", fp->lb0, fp->lt0,
fp->lc0);
debug("LB1: %08lx LT1: %08lx LC1: %08lx\n", fp->lb1, fp->lt1,
fp->lc1);
debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n", fp->b0, fp->l0,
fp->m0, fp->i0);
debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n", fp->b1, fp->l1,
fp->m1, fp->i1);
debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n", fp->b2, fp->l2,
fp->m2, fp->i2);
debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n", fp->b3, fp->l3,
fp->m3, fp->i3);
debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
}

194
cpu/bf561/video.c Normal file
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@ -0,0 +1,194 @@
/*
* (C) Copyright 2000
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
* (C) Copyright 2002
* Wolfgang Denk, wd@denx.de
* (C) Copyright 2006
* Aubrey Li, aubrey.li@analog.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <stdarg.h>
#include <common.h>
#include <config.h>
#include <asm/blackfin.h>
#include <i2c.h>
#include <linux/types.h>
#include <devices.h>
#ifdef CONFIG_VIDEO
#define NTSC_FRAME_ADDR 0x06000000
#include "video.h"
/* NTSC OUTPUT SIZE 720 * 240 */
#define VERTICAL 2
#define HORIZONTAL 4
int is_vblank_line(const int line)
{
/*
* This array contains a single bit for each line in
* an NTSC frame.
*/
if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
return true;
return false;
}
int NTSC_framebuffer_init(char *base_address)
{
const int NTSC_frames = 1;
const int NTSC_lines = 525;
char *dest = base_address;
int frame_num, line_num;
for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
unsigned int code;
int offset = 0;
int i;
if (is_vblank_line(line_num))
offset++;
if (line_num > 266 || line_num < 3)
offset += 2;
/* Output EAV code */
code = SystemCodeMap[offset].EAV;
write_dest_byte((char)(code >> 24) & 0xff);
write_dest_byte((char)(code >> 16) & 0xff);
write_dest_byte((char)(code >> 8) & 0xff);
write_dest_byte((char)(code) & 0xff);
/* Output horizontal blanking */
for (i = 0; i < 67 * 2; ++i) {
write_dest_byte(0x80);
write_dest_byte(0x10);
}
/* Output SAV */
code = SystemCodeMap[offset].SAV;
write_dest_byte((char)(code >> 24) & 0xff);
write_dest_byte((char)(code >> 16) & 0xff);
write_dest_byte((char)(code >> 8) & 0xff);
write_dest_byte((char)(code) & 0xff);
/* Output empty horizontal data */
for (i = 0; i < 360 * 2; ++i) {
write_dest_byte(0x80);
write_dest_byte(0x10);
}
}
}
return dest - base_address;
}
void fill_frame(char *Frame, int Value)
{
int *OddPtr32;
int OddLine;
int *EvenPtr32;
int EvenLine;
int i;
int *data;
int m, n;
/* fill odd and even frames */
for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
*OddPtr32 = Value;
*EvenPtr32 = Value;
}
}
for (m = 0; m < VERTICAL; m++) {
data = (int *)u_boot_logo.data;
for (OddLine = (22 + m), EvenLine = (285 + m);
OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
OddLine += VERTICAL, EvenLine += VERTICAL) {
OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
EvenPtr32 =
(int *)((Frame + ((EvenLine) * 1716)) + 276);
for (i = 0; i < u_boot_logo.width / 2; i++) {
/* enlarge one pixel to m x n */
for (n = 0; n < HORIZONTAL; n++) {
*OddPtr32++ = *data;
*EvenPtr32++ = *data;
}
data++;
}
}
}
}
void video_putc(const char c)
{
}
void video_puts(const char *s)
{
}
static int video_init(void)
{
char *NTSCFrame;
NTSCFrame = (char *)NTSC_FRAME_ADDR;
NTSC_framebuffer_init(NTSCFrame);
fill_frame(NTSCFrame, BLUE);
*pPPI_CONTROL = 0x0082;
*pPPI_FRAME = 0x020D;
*pDMA0_START_ADDR = NTSCFrame;
*pDMA0_X_COUNT = 0x035A;
*pDMA0_X_MODIFY = 0x0002;
*pDMA0_Y_COUNT = 0x020D;
*pDMA0_Y_MODIFY = 0x0002;
*pDMA0_CONFIG = 0x1015;
*pPPI_CONTROL = 0x0083;
return 0;
}
int drv_video_init(void)
{
int error, devices = 1;
device_t videodev;
video_init(); /* Video initialization */
memset(&videodev, 0, sizeof(videodev));
strcpy(videodev.name, "video");
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */
videodev.putc = video_putc; /* 'putc' function */
videodev.puts = video_puts; /* 'puts' function */
error = device_register(&videodev);
return (error == 0) ? devices : error;
}
#endif

25
cpu/bf561/video.h Normal file
View file

@ -0,0 +1,25 @@
#include <video_logo.h>
#define write_dest_byte(val) {*dest++=val;}
#define BLACK (0x01800180) /* black pixel pattern */
#define BLUE (0x296E29F0) /* blue pixel pattern */
#define RED (0x51F0515A) /* red pixel pattern */
#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */
#define GREEN (0x91229136) /* green pixel pattern */
#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
#define YELLOW (0xD292D210) /* yellow pixel pattern */
#define WHITE (0xFE80FE80) /* white pixel pattern */
#define true 1
#define false 0
typedef struct {
unsigned int SAV;
unsigned int EAV;
} SystemCodeType;
const SystemCodeType SystemCodeMap[4] = {
{0xFF000080, 0xFF00009D},
{0xFF0000AB, 0xFF0000B6},
{0xFF0000C7, 0xFF0000DA},
{0xFF0000EC, 0xFF0000F1}
};

8
cpu/mpc8260/cpu_init.c
View file

@ -129,9 +129,9 @@ void cpu_init_f (volatile immap_t * immr)
/* BCR - Bus Configuration Register (4-25) */
#if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE)
if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
immr->im_siu_conf.sc_bcr = CFG_BCR_60x;
immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_60x, 0x80000010);
} else {
immr->im_siu_conf.sc_bcr = CFG_BCR_SINGLE;
immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_SINGLE, 0x80000010);
}
#else
immr->im_siu_conf.sc_bcr = CFG_BCR;
@ -141,9 +141,9 @@ void cpu_init_f (volatile immap_t * immr)
#if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH)
cpu_clk = board_get_cpu_clk_f ();
if (cpu_clk >= 100000000) {
immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_HIGH;
immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_HIGH, 0x9f3cc000);
} else {
immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_LOW;
immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_LOW, 0x9f3cc000);
}
#else
immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;

18
cpu/mpc8260/pci.c
View file

@ -275,22 +275,7 @@ void pci_mpc8250_init (struct pci_controller *hose)
| SIUMCR_BCTLC00
| SIUMCR_MMR11;
#elif defined(CONFIG_TQM8272)
#if 0
immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
~SIUMCR_LBPC11 &
~SIUMCR_CS10PC11 &
~SIUMCR_LBPC11) |
SIUMCR_LBPC01 |
SIUMCR_CS10PC01 |
SIUMCR_APPC10;
#else
#if 0
immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr |
SIUMCR_APPC10);
#else
immap->im_siu_conf.sc_siumcr = 0x88000000;
#endif
#endif
/* nothing to do for this Board here */
#else
/*
* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
@ -304,7 +289,6 @@ void pci_mpc8250_init (struct pci_controller *hose)
SIUMCR_CS10PC01 |
SIUMCR_APPC10;
#endif
printf("%s siumcr: %x\n", __FUNCTION__, immap->im_siu_conf.sc_siumcr);
/* Make PCI lowest priority */
/* Each 4 bits is a device bus request and the MS 4bits

20
cpu/mpc86xx/interrupts.c
View file

@ -80,6 +80,26 @@ int interrupt_init(void)
{
int ret;
/*
* The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to
* implement PEX10 errata. As INT is active high, it
* will cause core to take 0x500 interrupt.
*
* Due to the PIC's default pass through mode, as soon
* as interrupts are enabled (MSR[EE] = 1), an interrupt
* will be taken and u-boot will hang. This is due to a
* hardware change (per an errata fix) on new revisions
* of the board with Rev 2.x parts.
*
* Setting the PIC to mixed mode prevents the hang.
*/
if ((get_svr() & 0xf0) == 0x20) {
volatile immap_t *immr = (immap_t *)CFG_IMMR;
immr->im_pic.gcr = MPC86xx_PICGCR_RST;
while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
}
/* call cpu specific function from $(CPU)/interrupts.c */
ret = interrupt_init_cpu(&decrementer_count);

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