GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-17 12:41:32 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi

Browse source 
- Beelink-x2 STB support (Marcus)
- H6 DDR3, LPDDR3 changes (Andre, Jernej)
- H6 pin controller, USB PHY (Andre)
This commit is contained in:
Tom Rini 2019-07-16 11:19:31 -04:00
commit 0e80dda32c
165 changed files with 719 additions and 328 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/Kconfig
View file

@ -936,6 +936,7 @@ config ARCH_SUNXI
select SPL_STACK_R if SPL
select SPL_SYS_MALLOC_SIMPLE if SPL
select SPL_SYS_THUMB_BUILD if !ARM64
select SUNXI_GPIO
select SYS_NS16550
select SYS_THUMB_BUILD if !ARM64
select USB if DISTRO_DEFAULTS

1
arch/arm/dts/Makefile
View file

@ -482,6 +482,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h2-plus-orangepi-r1.dtb \
sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-h3-beelink-x2.dtb \
sun8i-h3-libretech-all-h3-cc.dtb \
sun8i-h3-nanopi-m1.dtb \
sun8i-h3-nanopi-m1-plus.dtb \

216
arch/arm/dts/sun8i-h3-beelink-x2.dts Normal file
View file

@ -0,0 +1,216 @@
/*
* Copyright (C) 2017 Marcus Cooper <codekipper@gmail.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun8i-h3.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Beelink X2";
compatible = "roofull,beelink-x2", "allwinner,sun8i-h3";
aliases {
serial0 = &uart0;
ethernet0 = &emac;
ethernet1 = &sdiowifi;
};
chosen {
stdout-path = "serial0:115200n8";
};
connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
blue {
label = "beelink-x2:blue:pwr";
gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
default-state = "on";
};
red {
label = "beelink-x2:red:standby";
gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
};
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
};
sound_spdif {
compatible = "simple-audio-card";
simple-audio-card,name = "On-board SPDIF";
simple-audio-card,cpu {
sound-dai = <&spdif>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
spdif_out: spdif-out {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
};
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
&mmc1 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
non-removable;
status = "okay";
/*
* Explicitly define the sdio device, so that we can add an ethernet
* alias for it (which e.g. makes u-boot set a mac-address).
*/
sdiowifi: sdio_wifi@1 {
reg = <1>;
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_pins>;
vmmc-supply = <&reg_vcc3v3>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&reg_usb0_vbus {
gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
status = "okay";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx_pins_a>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
/* USB VBUS is always on except for the OTG port */
status = "okay";
usb0_id_det-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA07 */
usb0_vbus-supply = <&reg_usb0_vbus>;
};

35
arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
View file

@ -9,6 +9,8 @@
#ifndef _SUNXI_DRAM_SUN50I_H6_H
#define _SUNXI_DRAM_SUN50I_H6_H
#include <stdbool.h>
enum sunxi_dram_type {
SUNXI_DRAM_TYPE_DDR3 = 3,
SUNXI_DRAM_TYPE_DDR4,
@ -16,6 +18,11 @@ enum sunxi_dram_type {
SUNXI_DRAM_TYPE_LPDDR3,
};
static inline bool sunxi_dram_is_lpddr(int type)
{
return type >= SUNXI_DRAM_TYPE_LPDDR2;
}
/*
* The following information is mainly retrieved by disassembly and some FPGA
* test code of sun50iw3 platform.
@ -286,6 +293,32 @@ check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0);
#define DCR_DDR3 (3 << 0)
#define DCR_DDR4 (4 << 0)
#define DCR_DDR8BANK BIT(3)
#define DCR_DDR2T BIT(28)
/*
* The delay parameters allow to allegedly specify delay times of some
* unknown unit for each individual bit trace in each of the four data bytes
* the 32-bit wide access consists of. Also three control signals can be
* adjusted individually.
*/
#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */
#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4)
/*
* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN,
* Termination and Power down
*/
#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6)
struct dram_para {
u32 clk;
enum sunxi_dram_type type;
u8 cols;
u8 rows;
u8 ranks;
const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
};
static inline int ns_to_t(int nanoseconds)
{
@ -294,4 +327,6 @@ static inline int ns_to_t(int nanoseconds)
return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
}
void mctl_set_timing_params(struct dram_para *para);
#endif /* _SUNXI_DRAM_SUN50I_H6_H */

19
arch/arm/mach-sunxi/Kconfig
View file

@ -300,6 +300,7 @@ config MACH_SUN50I_H6
select ARM64
select SUPPORT_SPL
select FIT
select PHY_SUN4I_USB
select SPL_LOAD_FIT
select DRAM_SUN50I_H6
@ -340,7 +341,7 @@ config ARM_BOOT_HOOK_RMR
This allows both the SPL and the U-Boot proper to be entered in
either mode and switch to AArch64 if needed.
if SUNXI_DRAM_DW
if SUNXI_DRAM_DW || DRAM_SUN50I_H6
config SUNXI_DRAM_DDR3
bool
@ -370,6 +371,22 @@ config SUNXI_DRAM_LPDDR3_STOCK
This option is the LPDDR3 timing used by the stock boot0 by
Allwinner.
config SUNXI_DRAM_H6_LPDDR3
bool "LPDDR3 DRAM chips on the H6 DRAM controller"
select SUNXI_DRAM_LPDDR3
depends on DRAM_SUN50I_H6
---help---
This option is the LPDDR3 timing used by the stock boot0 by
Allwinner.
config SUNXI_DRAM_H6_DDR3_1333
bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
select SUNXI_DRAM_DDR3
depends on DRAM_SUN50I_H6
---help---
This option is the DDR3 timing used by the boot0 on H6 TV boxes
which use a DDR3-1333 timing.
config SUNXI_DRAM_DDR2_V3S
bool "DDR2 found in V3s chip"
select SUNXI_DRAM_DDR2

1
arch/arm/mach-sunxi/Makefile
View file

@ -39,4 +39,5 @@ obj-$(CONFIG_SPL_SPI_SUNXI) += spl_spi_sunxi.o
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o
obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/
obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o
obj-$(CONFIG_DRAM_SUN50I_H6) += dram_timings/
endif

251
arch/arm/mach-sunxi/dram_sun50i_h6.c
View file

@ -32,33 +32,8 @@
* similar PHY is ZynqMP.
*/
/*
* The delay parameters below allow to allegedly specify delay times of some
* unknown unit for each individual bit trace in each of the four data bytes
* the 32-bit wide access consists of. Also three control signals can be
* adjusted individually.
*/
#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */
#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4)
/*
* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN,
* Termination and Power down
*/
#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6)
struct dram_para {
u32 clk;
enum sunxi_dram_type type;
u8 cols;
u8 rows;
u8 ranks;
const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
};
static void mctl_sys_init(struct dram_para *para);
static void mctl_com_init(struct dram_para *para);
static void mctl_set_timing_lpddr3(struct dram_para *para);
static void mctl_channel_init(struct dram_para *para);
static void mctl_core_init(struct dram_para *para)
@ -67,7 +42,8 @@ static void mctl_core_init(struct dram_para *para)
mctl_com_init(para);
switch (para->type) {
case SUNXI_DRAM_TYPE_LPDDR3:
mctl_set_timing_lpddr3(para);
case SUNXI_DRAM_TYPE_DDR3:
mctl_set_timing_params(para);
break;
default:
panic("Unsupported DRAM type!");
@ -75,12 +51,14 @@ static void mctl_core_init(struct dram_para *para)
mctl_channel_init(para);
}
/* PHY initialisation */
static void mctl_phy_pir_init(u32 val)
{
struct sunxi_mctl_phy_reg * const mctl_phy =
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
writel(val | BIT(0), &mctl_phy->pir);
writel(val, &mctl_phy->pir);
writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */
mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
}
@ -169,125 +147,6 @@ static void mctl_set_master_priority(void)
MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32);
}
static u32 mr_lpddr3[12] = {
0x00000000, 0x00000043, 0x0000001a, 0x00000001,
0x00000000, 0x00000000, 0x00000048, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000003,
};
/* TODO: flexible timing */
static void mctl_set_timing_lpddr3(struct dram_para *para)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
struct sunxi_mctl_phy_reg * const mctl_phy =
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
u8 tccd = 2;
u8 tfaw = max(ns_to_t(50), 4);
u8 trrd = max(ns_to_t(10), 2);
u8 trcd = max(ns_to_t(24), 2);
u8 trc = ns_to_t(70);
u8 txp = max(ns_to_t(8), 2);
u8 twtr = max(ns_to_t(8), 2);
u8 trtp = max(ns_to_t(8), 2);
u8 twr = max(ns_to_t(15), 2);
u8 trp = ns_to_t(18);
u8 tras = ns_to_t(42);
u8 twtr_sa = ns_to_t(5);
u8 tcksrea = ns_to_t(11);
u16 trefi = ns_to_t(3900) / 32;
u16 trfc = ns_to_t(210);
u16 txsr = ns_to_t(220);
if (CONFIG_DRAM_CLK % 400 == 0) {
/* Round up these parameters */
twtr_sa++;
tcksrea++;
}
u8 tmrw = 5;
u8 tmrd = 5;
u8 tmod = 12;
u8 tcke = 3;
u8 tcksrx = 5;
u8 tcksre = 5;
u8 tckesr = 5;
u8 trasmax = CONFIG_DRAM_CLK / 60;
u8 txs = 4;
u8 txsdll = 4;
u8 txsabort = 4;
u8 txsfast = 4;
u8 tcl = 5; /* CL 10 */
u8 tcwl = 3; /* CWL 6 */
u8 t_rdata_en = twtr_sa + 8;
u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */
u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
u8 twtp = tcwl + 4 + twr + 1;
/*
* The code below for twr2rd and trd2wr follows the IP core's
* document from ZynqMP and i.MX7. The BSP has both number
* substracted by 2.
*/
u8 twr2rd = tcwl + 4 + 1 + twtr;
u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1;
/* set mode register */
memcpy(mctl_phy->mr, mr_lpddr3, sizeof(mr_lpddr3));
/* set DRAM timing */
writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
&mctl_ctl->dramtmg[0]);
writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
&mctl_ctl->dramtmg[2]);
writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
&mctl_ctl->dramtmg[4]);
writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
&mctl_ctl->dramtmg[5]);
/* Value suggested by ZynqMP manual and used by libdram */
writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
&mctl_ctl->dramtmg[8]);
writel(txsr, &mctl_ctl->dramtmg[14]);
clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30));
writel(0, &mctl_ctl->dfimisc);
clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
/*
* Set timing registers of the PHY.
* Note: the PHY is clocked 2x from the DRAM frequency.
*/
writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1),
&mctl_phy->dtpr[0]);
writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]);
writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]);
writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8),
&mctl_phy->dtpr[3]);
writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]);
writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);
writel(0x0505, &mctl_phy->dtpr[6]);
/* Configure DFI timing */
writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000,
&mctl_ctl->dfitmg0);
writel(0x040201, &mctl_ctl->dfitmg1);
/* Configure PHY timing */
writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]);
writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]);
/* set refresh timing */
writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
}
static void mctl_sys_init(struct dram_para *para)
{
struct sunxi_ccm_reg * const ccm =
@ -426,14 +285,11 @@ static void mctl_com_init(struct dram_para *para)
mctl_set_addrmap(para);
setbits_le32(&mctl_com->cr, BIT(31));
/*
* This address is magic; it's in SID memory area, but there's no
* known definition of it.
* On my Pine H64 board it has content 7.
*/
if (readl(0x03006100) == 7)
/* The bonding ID seems to be always 7. */
if (readl(SUNXI_SIDC_BASE + 0x100) == 7) /* bonding ID */
clrbits_le32(&mctl_com->cr, BIT(27));
else if (readl(0x03006100) == 3)
else if (readl(SUNXI_SIDC_BASE + 0x100) == 3)
setbits_le32(&mctl_com->cr, BIT(27));
if (para->clk > 408)
@ -444,22 +300,37 @@ static void mctl_com_init(struct dram_para *para)
reg_val = 0x3f00;
clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
/* TODO: half DQ, non-LPDDR3 types */
writel(MSTR_DEVICETYPE_LPDDR3 | MSTR_BUSWIDTH_FULL |
MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks) |
0x80000000, &mctl_ctl->mstr);
writel(DCR_LPDDR3 | DCR_DDR8BANK | 0x400, &mctl_phy->dcr);
/* TODO: half DQ, DDR4 */
reg_val = MSTR_BUSWIDTH_FULL | MSTR_BURST_LENGTH(8) |
MSTR_ACTIVE_RANKS(para->ranks);
if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
reg_val |= MSTR_DEVICETYPE_LPDDR3;
if (para->type == SUNXI_DRAM_TYPE_DDR3)
reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
writel(reg_val | BIT(31), &mctl_ctl->mstr);
if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
reg_val = DCR_LPDDR3 | DCR_DDR8BANK;
if (para->type == SUNXI_DRAM_TYPE_DDR3)
reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T;
writel(reg_val | 0x400, &mctl_phy->dcr);
if (para->ranks == 2)
writel(0x0303, &mctl_ctl->odtmap);
else
writel(0x0201, &mctl_ctl->odtmap);
/* TODO: non-LPDDR3 types */
tmp = para->clk * 7 / 2000;
reg_val = 0x0400;
reg_val |= (tmp + 7) << 24;
reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;
/* TODO: DDR4 */
if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
tmp = para->clk * 7 / 2000;
reg_val = 0x0400;
reg_val |= (tmp + 7) << 24;
reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;
} else if (para->type == SUNXI_DRAM_TYPE_DDR3) {
reg_val = 0x06000400; /* TODO?: Use CL - CWL value in [7:0] */
} else {
panic("Only (LP)DDR3 supported (type = %d)\n", para->type);
}
writel(reg_val, &mctl_ctl->odtcfg);
/* TODO: half DQ */
@ -514,6 +385,9 @@ static void mctl_bit_delay_set(struct dram_para *para)
setbits_le32(&mctl_phy->pgcr[0], BIT(26));
udelay(1);
if (para->type != SUNXI_DRAM_TYPE_LPDDR3)
return;
for (i = 1; i < 14; i++) {
val = readl(&mctl_phy->acbdlr[i]);
val += 0x0a0a0a0a;
@ -561,7 +435,8 @@ static void mctl_channel_init(struct dram_para *para)
else
clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
if (sunxi_dram_is_lpddr(para->type))
clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
if (para->ranks == 2) {
writel(0x00010001, &mctl_phy->rankidr);
writel(0x20000, &mctl_phy->odtcr);
@ -570,8 +445,11 @@ static void mctl_channel_init(struct dram_para *para)
writel(0x10000, &mctl_phy->odtcr);
}
/* TODO: non-LPDDR3 types */
clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
/* set bits [3:0] to 1? 0 not valid in ZynqMP d/s */
if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
else
clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000000);
if (para->clk <= 792) {
if (para->clk <= 672) {
if (para->clk <= 600)
@ -601,12 +479,13 @@ static void mctl_channel_init(struct dram_para *para)
writel(0x06060606, &mctl_phy->acbdlr[i]);
}
/* TODO: non-LPDDR3 types */
mctl_phy_pir_init(PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT |
PIR_QSGATE | PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE |
PIR_WREYE);
val = PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | PIR_QSGATE |
PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | PIR_WREYE;
if (para->type == SUNXI_DRAM_TYPE_DDR3)
val |= PIR_DRAMRST | PIR_WL;
mctl_phy_pir_init(val);
/* TODO: non-LPDDR3 types */
/* TODO: DDR4 types ? */
for (i = 0; i < 4; i++)
writel(0x00000909, &mctl_phy->dx[i].gcr[5]);
@ -662,7 +541,8 @@ static void mctl_channel_init(struct dram_para *para)
panic("Error while initializing DRAM PHY!\n");
}
clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);
if (sunxi_dram_is_lpddr(para->type))
clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);
clrbits_le32(&mctl_phy->pgcr[1], 0x40);
clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
writel(1, &mctl_ctl->swctl);
@ -714,29 +594,46 @@ unsigned long mctl_calc_size(struct dram_para *para)
return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks;
}
#define SUN50I_H6_DX_WRITE_DELAYS \
#define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \
{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
#define SUN50I_H6_DX_READ_DELAYS \
#define SUN50I_H6_LPDDR3_DX_READ_DELAYS \
{{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }}
#define SUN50I_H6_DDR3_DX_WRITE_DELAYS \
{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
#define SUN50I_H6_DDR3_DX_READ_DELAYS \
{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
unsigned long sunxi_dram_init(void)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
struct dram_para para = {
.clk = CONFIG_DRAM_CLK,
.type = SUNXI_DRAM_TYPE_LPDDR3,
.ranks = 2,
.cols = 11,
.rows = 14,
.dx_read_delays = SUN50I_H6_DX_READ_DELAYS,
.dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS,
#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
.type = SUNXI_DRAM_TYPE_LPDDR3,
.dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
.dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
#elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333)
.type = SUNXI_DRAM_TYPE_DDR3,
.dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS,
.dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
#endif
};
unsigned long size;

2
arch/arm/mach-sunxi/dram_timings/Makefile
View file

@ -1,3 +1,5 @@
obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o
obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o
obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o
obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3) += h6_lpddr3.o
obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333) += h6_ddr3_1333.o

144
arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c Normal file
View file

@ -0,0 +1,144 @@
/*
* sun50i H6 DDR3-1333 timings, as programmed by Allwinner's boot0
* for some TV boxes with the H6 and DDR3 memory.
*
* The chips are probably able to be driven by a faster clock, but boot0
* uses a more conservative timing (as usual).
*
* (C) Copyright 2018,2019 Arm Ltd.
* based on previous work by:
* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
*
* References used:
* - JEDEC DDR3 SDRAM standard: JESD79-3F.pdf
* - Samsung K4B2G0446D datasheet
* - ZynqMP UG1087 register DDRC/PHY documentation
*
* Many thanks to Jernej Skrabec for contributing some fixes!
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>
/*
* Only the first four are used for DDR3(?)
* MR0: BL8, seq. read burst, no test, fast exit (DLL on), no DLL reset,
* CAS latency (CL): 11, write recovery (WR): 12
* MR1: DLL enabled, output strength RZQ/6, Rtt_norm RZQ/2,
* write levelling disabled, TDQS disabled, output buffer enabled
* MR2: manual full array self refresh, dynamic ODT off,
* CAS write latency (CWL): 8
*/
static u32 mr_ddr3[7] = {
0x00001c70, 0x00000040, 0x00000018, 0x00000000,
0x00000000, 0x00000400, 0x00000848,
};
/* TODO: flexible timing */
void mctl_set_timing_params(struct dram_para *para)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
struct sunxi_mctl_phy_reg * const mctl_phy =
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
int i;
u8 tccd = 2; /* JEDEC: 4nCK */
u8 tfaw = ns_to_t(50); /* JEDEC: 30 ns w/ 1K pages */
u8 trrd = max(ns_to_t(6), 4); /* JEDEC: max(6 ns, 4nCK) */
u8 trcd = ns_to_t(15); /* JEDEC: 13.5 ns */
u8 trc = ns_to_t(53); /* JEDEC: 49.5 ns */
u8 txp = max(ns_to_t(6), 3); /* JEDEC: max(6 ns, 3nCK) */
u8 twtr = max(ns_to_t(8), 2); /* JEDEC: max(7.5 ns, 4nCK) */
u8 trtp = max(ns_to_t(8), 2); /* JEDEC: max(7.5 ns, 4nCK) */
u8 twr = ns_to_t(15); /* JEDEC: 15 ns */
u8 trp = ns_to_t(15); /* JEDEC: >= 13.75 ns */
u8 tras = ns_to_t(38); /* JEDEC >= 36 ns, <= 9*trefi */
u8 twtr_sa = 2; /* ? */
u8 tcksrea = 4; /* ? */
u16 trefi = ns_to_t(7800) / 32; /* JEDEC: 7.8us@Tcase <= 85C */
u16 trfc = ns_to_t(350); /* JEDEC: 160 ns for 2Gb */
u16 txsr = 4; /* ? */
u8 tmrw = 0; /* ? */
u8 tmrd = 4; /* JEDEC: 4nCK */
u8 tmod = max(ns_to_t(15), 12); /* JEDEC: max(15 ns, 12nCK) */
u8 tcke = max(ns_to_t(6), 3); /* JEDEC: max(5.625 ns, 3nCK) */
u8 tcksrx = max(ns_to_t(10), 5); /* JEDEC: max(10 ns, 5nCK) */
u8 tcksre = max(ns_to_t(10), 5); /* JEDEC: max(10 ns, 5nCK) */
u8 tckesr = tcke + 1; /* JEDEC: tCKE(min) + 1nCK */
u8 trasmax = 24; /* JEDEC: tREFI * 9 */
u8 txs = ns_to_t(360) / 32; /* JEDEC: max(5nCK,tRFC+10ns) */
u8 txsdll = 4; /* JEDEC: 512 nCK */
u8 txsabort = 4; /* ? */
u8 txsfast = 4; /* ? */
u8 tcl = 6; /* JEDEC: CL / 2 => 6 */
u8 tcwl = 4; /* JEDEC: 8 */
u8 t_rdata_en = 7; /* ? */
u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1;
u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1;
u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
u8 twtp = tcwl + 2 + twr; /* (WL + BL / 2 + tWR) / 2 */
u8 twr2rd = tcwl + 2 + twtr; /* (WL + BL / 2 + tWTR) / 2 */
u8 trd2wr = 5; /* (RL + BL / 2 + 2 - WL) / 2 */
if (tcl + 1 >= trtp + trp)
trtp = tcl + 2 - trp;
/* set mode registers */
for (i = 0; i < ARRAY_SIZE(mr_ddr3); i++)
writel(mr_ddr3[i], &mctl_phy->mr[i]);
/* set DRAM timing */
writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
&mctl_ctl->dramtmg[0]);
writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
&mctl_ctl->dramtmg[2]);
writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
&mctl_ctl->dramtmg[4]);
writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
&mctl_ctl->dramtmg[5]);
/* Value suggested by ZynqMP manual and used by libdram */
writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
&mctl_ctl->dramtmg[8]);
writel(txsr, &mctl_ctl->dramtmg[14]);
clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30));
writel(0, &mctl_ctl->dfimisc);
clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
/*
* Set timing registers of the PHY.
* Note: the PHY is clocked 2x from the DRAM frequency.
*/
writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1),
&mctl_phy->dtpr[0]);
writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]);
writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]);
writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8),
&mctl_phy->dtpr[3]);
writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]);
writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);
writel(0x0505, &mctl_phy->dtpr[6]);
/* Configure DFI timing */
writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000,
&mctl_ctl->dfitmg0);
writel(0x040201, &mctl_ctl->dfitmg1);
/* Configure PHY timing. Zynq uses different registers. */
writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]);
writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]);
/* set refresh timing */
writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
}

132
arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c Normal file
View file

@ -0,0 +1,132 @@
/*
* sun50i H6 LPDDR3 timings
*
* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/dram.h>
#include <asm/arch/cpu.h>
static u32 mr_lpddr3[12] = {
0x00000000, 0x00000043, 0x0000001a, 0x00000001,
0x00000000, 0x00000000, 0x00000048, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000003,
};
/* TODO: flexible timing */
void mctl_set_timing_params(struct dram_para *para)
{
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
struct sunxi_mctl_phy_reg * const mctl_phy =
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
int i;
u8 tccd = 2;
u8 tfaw = max(ns_to_t(50), 4);
u8 trrd = max(ns_to_t(10), 2);
u8 trcd = max(ns_to_t(24), 2);
u8 trc = ns_to_t(70);
u8 txp = max(ns_to_t(8), 2);
u8 twtr = max(ns_to_t(8), 2);
u8 trtp = max(ns_to_t(8), 2);
u8 twr = max(ns_to_t(15), 2);
u8 trp = ns_to_t(18);
u8 tras = ns_to_t(42);
u8 twtr_sa = ns_to_t(5);
u8 tcksrea = ns_to_t(11);
u16 trefi = ns_to_t(3900) / 32;
u16 trfc = ns_to_t(210);
u16 txsr = ns_to_t(220);
if (CONFIG_DRAM_CLK % 400 == 0) {
/* Round up these parameters */
twtr_sa++;
tcksrea++;
}
u8 tmrw = 5;
u8 tmrd = 5;
u8 tmod = 12;
u8 tcke = 3;
u8 tcksrx = 5;
u8 tcksre = 5;
u8 tckesr = 5;
u8 trasmax = CONFIG_DRAM_CLK / 60;
u8 txs = 4;
u8 txsdll = 4;
u8 txsabort = 4;
u8 txsfast = 4;
u8 tcl = 5; /* CL 10 */
u8 tcwl = 3; /* CWL 6 */
u8 t_rdata_en = twtr_sa + 8;
u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */
u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
u8 twtp = tcwl + 4 + twr + 1;
/*
* The code below for twr2rd and trd2wr follows the IP core's
* document from ZynqMP and i.MX7. The BSP has both number
* substracted by 2.
*/
u8 twr2rd = tcwl + 4 + 1 + twtr;
u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1;
/* set mode registers */
for (i = 0; i < ARRAY_SIZE(mr_lpddr3); i++)
writel(mr_lpddr3[i], &mctl_phy->mr[i]);
/* set DRAM timing */
writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,
&mctl_ctl->dramtmg[0]);
writel((txp << 16) | (trtp << 8) | trc, &mctl_ctl->dramtmg[1]);
writel((tcwl << 24) | (tcl << 16) | (trd2wr << 8) | twr2rd,
&mctl_ctl->dramtmg[2]);
writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
&mctl_ctl->dramtmg[4]);
writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
&mctl_ctl->dramtmg[5]);
/* Value suggested by ZynqMP manual and used by libdram */
writel((txp + 2) | 0x02020000, &mctl_ctl->dramtmg[6]);
writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
&mctl_ctl->dramtmg[8]);
writel(txsr, &mctl_ctl->dramtmg[14]);
clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30));
writel(0, &mctl_ctl->dfimisc);
clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
/*
* Set timing registers of the PHY.
* Note: the PHY is clocked 2x from the DRAM frequency.
*/
writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1),
&mctl_phy->dtpr[0]);
writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]);
writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]);
writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8),
&mctl_phy->dtpr[3]);
writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]);
writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);
writel(0x0505, &mctl_phy->dtpr[6]);
/* Configure DFI timing */
writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000,
&mctl_ctl->dfitmg0);
writel(0x040201, &mctl_ctl->dfitmg1);
/* Configure PHY timing */
writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]);
writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]);
/* set refresh timing */
writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
}

6
board/sunxi/MAINTAINERS
View file

@ -172,6 +172,12 @@ S: Maintained
F: configs/beelink_gs1_defconfig
F: arch/arm/dts/sun50i-h6-beelink-gs1.dts
BEELINK X2 BOARD
M: Marcus Cooper <codekipper@gmail.com>
S: Maintained
F: configs/beelink_x2_defconfig
F: arch/arm/dts/sun8i-h3-beelink-x2.dts
COLOMBUS BOARD
M: Maxime Ripard <maxime.ripard@bootlin.com>
S: Maintained

3
common/spl/Kconfig
View file

@ -116,6 +116,9 @@ config SPL_LDSCRIPT
config SPL_TEXT_BASE
hex "SPL Text Base"
default ISW_ENTRY_ADDR if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
default 0x20060 if MACH_SUN50I_H6
default 0x00060 if ARCH_SUNXI
default 0x0
help
The address in memory that SPL will be running from.

1
configs/A10-OLinuXino-Lime_defconfig
View file

@ -11,7 +11,6 @@ CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/A10s-OLinuXino-M_defconfig
View file

@ -9,7 +9,6 @@ CONFIG_MMC1_CD_PIN="PG13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/A13-OLinuXinoM_defconfig
View file

@ -13,7 +13,6 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
CONFIG_VIDEO_LCD_POWER="PB10"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/A13-OLinuXino_defconfig
View file

@ -15,7 +15,6 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set

1
configs/A20-OLinuXino-Lime2-eMMC_defconfig
View file

@ -13,7 +13,6 @@ CONFIG_SATAPWR="PC3"
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set

1
configs/A20-OLinuXino-Lime2_defconfig
View file

@ -11,7 +11,6 @@ CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set

1
configs/A20-OLinuXino-Lime_defconfig
View file

@ -9,7 +9,6 @@ CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/A20-OLinuXino_MICRO-eMMC_defconfig
View file

@ -11,7 +11,6 @@ CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/A20-OLinuXino_MICRO_defconfig
View file

@ -12,7 +12,6 @@ CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/A20-Olimex-SOM-EVB_defconfig
View file

@ -13,7 +13,6 @@ CONFIG_USB0_VBUS_DET="PH5"
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
View file

@ -13,7 +13,6 @@ CONFIG_SATAPWR="PC3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/A20-Olimex-SOM204-EVB_defconfig
View file

@ -12,7 +12,6 @@ CONFIG_SATAPWR="PC3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/A33-OLinuXino_defconfig
View file

@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_BL_EN="PB2"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Ainol_AW1_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Ampe_A76_defconfig
View file

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Auxtek-T003_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_DRAM_EMR1=0
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Auxtek-T004_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PG13"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Bananapi_M2_Ultra_defconfig
View file

@ -9,7 +9,6 @@ CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"

1
configs/Bananapi_defconfig
View file

@ -9,7 +9,6 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Bananapi_m2m_defconfig
View file

@ -10,7 +10,6 @@ CONFIG_MMC0_CD_PIN="PB4"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_ID_DET="PH8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set

1
configs/Bananapro_defconfig
View file

@ -11,7 +11,6 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/CHIP_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y

1
configs/CHIP_pro_defconfig
View file

@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTDPARTS=y

1
configs/CSQ_CS908_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Chuwi_V7_CW0825_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Colombus_defconfig
View file

@ -17,7 +17,6 @@ CONFIG_VIDEO_LCD_PANEL_I2C_SDA="PA23"
CONFIG_VIDEO_LCD_PANEL_I2C_SCL="PA24"
CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Cubieboard2_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Cubieboard4_defconfig
View file

@ -12,7 +12,6 @@ CONFIG_USB0_ID_DET="PH16"
CONFIG_USB1_VBUS_PIN="PH14"
CONFIG_USB3_VBUS_PIN="PH15"
CONFIG_AXP_GPIO=y
CONFIG_SPL_TEXT_BASE=0x10060
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Cubieboard_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Cubietruck_defconfig
View file

@ -13,7 +13,6 @@ CONFIG_SATAPWR="PH12"
CONFIG_GMAC_TX_DELAY=1
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set

1
configs/Cubietruck_plus_defconfig
View file

@ -16,7 +16,6 @@ CONFIG_I2C0_ENABLE=y
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Empire_electronix_d709_defconfig
View file

@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Empire_electronix_m712_defconfig
View file

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Hummingbird_A31_defconfig
View file

@ -9,7 +9,6 @@ CONFIG_USB2_VBUS_PIN=""
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Hyundai_A7HD_defconfig
View file

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Itead_Ibox_A20_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Lamobo_R1_defconfig
View file

@ -10,7 +10,6 @@ CONFIG_SATAPWR="PB3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/LicheePi_Zero_defconfig
View file

@ -4,7 +4,6 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Linksprite_pcDuino3_Nano_defconfig
View file

@ -10,7 +10,6 @@ CONFIG_SATAPWR="PH2"
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Linksprite_pcDuino3_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_DRAM_ZQ=122
CONFIG_SATAPWR="PH2"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Linksprite_pcDuino_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_MACH_SUN4I=y
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/MK808C_defconfig
View file

@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/MSI_Primo73_defconfig
View file

@ -10,7 +10,6 @@ CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/MSI_Primo81_defconfig
View file

@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Marsboard_A10_defconfig
View file

@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Mele_A1000G_quad_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_INITIAL_USB_SCAN_DELAY=2000
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Mele_A1000_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Mele_I7_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_DRAM_ZQ=120
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Mele_M3_defconfig
View file

@ -9,7 +9,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Mele_M5_defconfig
View file

@ -9,7 +9,6 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Mele_M9_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_DRAM_ZQ=120
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Merrii_A80_Optimus_defconfig
View file

@ -12,7 +12,6 @@ CONFIG_USB0_ID_DET="PH3"
CONFIG_USB1_VBUS_PIN="PH4"
CONFIG_USB3_VBUS_PIN="PH5"
CONFIG_AXP_GPIO=y
CONFIG_SPL_TEXT_BASE=0x10060
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Mini-X_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_MACH_SUN4I=y
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Nintendo_NES_Classic_Edition_defconfig
View file

@ -9,7 +9,6 @@ CONFIG_DRAM_ODT_EN=y
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MTDPARTS=y
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Orangepi_defconfig
View file

@ -12,7 +12,6 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Orangepi_mini_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Sinlinx_SinA31s_defconfig
View file

@ -11,7 +11,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Sinlinx_SinA33_defconfig
View file

@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Sinovoip_BPI_M2_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Sinovoip_BPI_M3_defconfig
View file

@ -17,7 +17,6 @@ CONFIG_AXP_GPIO=y
CONFIG_SATAPWR="PD25"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/Sunchip_CX-A99_defconfig
View file

@ -12,7 +12,6 @@ CONFIG_USB0_VBUS_PIN="PH15"
CONFIG_USB1_VBUS_PIN="PL7"
CONFIG_USB3_VBUS_PIN="PL8"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x10060
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/UTOO_P66_defconfig
View file

@ -20,7 +20,6 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_TL059WV5C0=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Wexler_TAB7200_defconfig
View file

@ -13,7 +13,6 @@ CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Wits_Pro_A20_DKT_defconfig
View file

@ -12,7 +12,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Wobo_i5_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PB3"
CONFIG_USB1_VBUS_PIN="PG12"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Yones_Toptech_BD1078_defconfig
View file

@ -19,7 +19,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/Yones_Toptech_BS1078_V2_defconfig
View file

@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/a64-olinuxino_defconfig
View file

@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x10060
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/amarula_a64_relic_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x10060
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/ba10_tv_box_defconfig
View file

@ -9,7 +9,6 @@ CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/bananapi_m1_plus_defconfig
View file

@ -9,7 +9,6 @@ CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/bananapi_m2_berry_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=576
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry"

1
configs/bananapi_m2_plus_h3_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/bananapi_m2_plus_h5_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=672
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x10060
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/bananapi_m2_zero_defconfig
View file

@ -5,7 +5,6 @@ CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN=""
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/bananapi_m64_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x10060
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

4
configs/beelink_gs1_defconfig
View file

@ -3,14 +3,16 @@ CONFIG_ARCH_SUNXI=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_SUNXI_DRAM_H6_LPDDR3=y
CONFIG_MMC0_CD_PIN="PF6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x20060
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-beelink-gs1"
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y

16
configs/beelink_x2_defconfig Normal file
View file

@ -0,0 +1,16 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=567
CONFIG_DRAM_ZQ=3881979
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

1
configs/colorfly_e708_q1_defconfig
View file

@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_BL_EN="PA25"
CONFIG_VIDEO_LCD_BL_PWM="PH13"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/difrnce_dit4350_defconfig
View file

@ -15,7 +15,6 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/dserve_dsrv9703c_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/emlid_neutis_n5_devboard_defconfig
View file

@ -8,7 +8,6 @@ CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x10060
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/ga10h_v1_1_defconfig
View file

@ -17,7 +17,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/gt90h_v4_defconfig
View file

@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_POWER="PH7"
CONFIG_VIDEO_LCD_BL_EN="PH6"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/h8_homlet_v2_defconfig
View file

@ -11,7 +11,6 @@ CONFIG_USB1_VBUS_PIN="PL6"
CONFIG_AXP_GPIO=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_SPL_TEXT_BASE=0x60
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set

1
configs/i12-tvbox_defconfig
View file

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=384
CONFIG_MACPWR="PH21"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/iNet_3F_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

1
configs/iNet_3W_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_TEXT_BASE=0x60
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_CMD_FLASH is not set
# CONFIG_SPL_DOS_PARTITION is not set

Some files were not shown because too many files have changed in this diff Show more