From 91955834f5f4f58a6919a3005a8a4061cbbe7910 Mon Sep 17 00:00:00 2001
From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Date: Thu, 19 Aug 2010 09:37:32 +0200
Subject: [PATCH 01/15] net: Fix faulty definition of uec_initialize()

The correct definition is in drivers/qe/uec.h so just
remove this one.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 include/netdev.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/netdev.h b/include/netdev.h
index 94eedfe29d..71fe805611 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -85,7 +85,6 @@ int skge_initialize(bd_t *bis);
 int smc911x_initialize(u8 dev_num, int base_addr);
 int smc91111_initialize(u8 dev_num, int base_addr);
 int tsi108_eth_initialize(bd_t *bis);
-int uec_initialize(int index);
 int uec_standard_init(bd_t *bis);
 int uli526x_initialize(bd_t *bis);
 int sh_eth_initialize(bd_t *bis);

From b7081d91977aa3bf0cfc8284a463bd3901d0d6ad Mon Sep 17 00:00:00 2001
From: "Reinhard Meyer (-VC)" <reinhard.meyer@emk-elektronik.de>
Date: Fri, 6 Aug 2010 18:42:07 +0200
Subject: [PATCH 02/15] NET: move legacy enc28j60.c to sidetrack as
 enc28j60_lpc2292.c

This patch is required before the upcoming new enc28j60 driver
using SPI framework patch can be applied:
- Move legacy enc28j60.c to enc28j60_lpc2292.c.
- Change Makefile and the two affected boards' definition files.

Tested with ./MAKEALL ARM7 that both boards still compile.

Signed-off-by: Reinhard Meyer<info@emk-elektronik.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 drivers/net/Makefile                           | 2 +-
 drivers/net/{enc28j60.c => enc28j60_lpc2292.c} | 1 +
 include/configs/SMN42.h                        | 2 +-
 include/configs/lpc2292sodimm.h                | 2 +-
 4 files changed, 4 insertions(+), 3 deletions(-)
 rename drivers/net/{enc28j60.c => enc28j60_lpc2292.c} (99%)

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 218eeff86e..479954d80c 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -39,7 +39,7 @@ COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
 COBJS-$(CONFIG_DNET) += dnet.o
 COBJS-$(CONFIG_E1000) += e1000.o
 COBJS-$(CONFIG_EEPRO100) += eepro100.o
-COBJS-$(CONFIG_ENC28J60) += enc28j60.o
+COBJS-$(CONFIG_ENC28J60_LPC2292) += enc28j60_lpc2292.o
 COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
 COBJS-$(CONFIG_ETHOC) += ethoc.o
 COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60_lpc2292.c
similarity index 99%
rename from drivers/net/enc28j60.c
rename to drivers/net/enc28j60_lpc2292.c
index 3238a502ca..bf9505206b 100644
--- a/drivers/net/enc28j60.c
+++ b/drivers/net/enc28j60_lpc2292.c
@@ -15,6 +15,7 @@
  * MA 02111-1307 USA
  */
 
+#warning This driver is depreciated. Please update to new SPI framework enc28j60 driver
 #include <config.h>
 #include <common.h>
 #include <net.h>
diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h
index adb6ac52e1..ba3ada13a5 100644
--- a/include/configs/SMN42.h
+++ b/include/configs/SMN42.h
@@ -198,6 +198,6 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_MMC			1
 /* we use this ethernet chip */
-#define CONFIG_ENC28J60
+#define CONFIG_ENC28J60_LPC2292
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h
index 7ce8d6de1f..65276a27c0 100644
--- a/include/configs/lpc2292sodimm.h
+++ b/include/configs/lpc2292sodimm.h
@@ -156,6 +156,6 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_MMC 1
 /* we use this ethernet chip */
-#define CONFIG_ENC28J60
+#define CONFIG_ENC28J60_LPC2292
 
 #endif	/* __CONFIG_H */

From bd6c25afd23a656b2283b7aecd893c1a16bcd585 Mon Sep 17 00:00:00 2001
From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Date: Wed, 11 Aug 2010 11:44:21 +0200
Subject: [PATCH 03/15] UEC: Don't udelay needlessly

uec_init() adds an udelay(100000) even though
the PHY status read went well, don't do that.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 drivers/qe/uec.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index e10c0f328c..48033d750c 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1223,8 +1223,10 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
 		i = 50;
 		do {
 			err = curphy->read_status(uec->mii_info);
+			if (!(((i-- > 0) && !uec->mii_info->link) || err))
+				break;
 			udelay(100000);
-		} while (((i-- > 0) && !uec->mii_info->link) || err);
+		} while (1);
 
 		if (err || i <= 0)
 			printf("warning: %s: timeout on PHY link\n", dev->name);

From b0a75d7aa325181d5837f0178e1fa8417ea747c2 Mon Sep 17 00:00:00 2001
From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Date: Wed, 11 Aug 2010 11:44:22 +0200
Subject: [PATCH 04/15] UEC PHY: Remove strange 0.5 sec delay

This udelay looks bogus and doesn't help my board.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 drivers/qe/uec_phy.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 2d3a896d6f..7ea2ae1af7 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -389,7 +389,6 @@ static int genmii_update_link (struct uec_mii_info *mii_info)
 			status = phy_read(mii_info, PHY_BMSR);
 		}
 		mii_info->link = 1;
-		udelay(500000);	/* another 500 ms (results in faster booting) */
 	} else {
 		if (status & PHY_BMSR_LS)
 			mii_info->link = 1;

From 68e1ede88a5d6a43beb425d8aa4ac97b850b5720 Mon Sep 17 00:00:00 2001
From: Ben Warren <biggerbadderben@gmail.com>
Date: Sun, 1 Aug 2010 23:00:31 -0700
Subject: [PATCH 05/15] Net: Remove redundant CONFIG_NET_MULTI directives

All are within an #ifdef CONFIG_NET_MULTI block already

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 net/eth.c | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/net/eth.c b/net/eth.c
index 993306f0a4..5c70d4f3ff 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -263,7 +263,6 @@ int eth_initialize(bd_t *bis)
 			dev = dev->next;
 		} while(dev != eth_devices);
 
-#ifdef CONFIG_NET_MULTI
 		/* update current ethernet name */
 		if (eth_current) {
 			char *act = getenv("ethact");
@@ -271,7 +270,6 @@ int eth_initialize(bd_t *bis)
 				setenv("ethact", eth_current->name);
 		} else
 			setenv("ethact", NULL);
-#endif
 
 		putc ('\n');
 	}
@@ -441,7 +439,7 @@ int eth_receive(volatile void *packet, int length)
 void eth_try_another(int first_restart)
 {
 	static struct eth_device *first_failed = NULL;
-	char *ethrotate;
+	char *ethrotate, *act;
 
 	/*
 	 * Do not rotate between network interfaces when
@@ -460,21 +458,16 @@ void eth_try_another(int first_restart)
 
 	eth_current = eth_current->next;
 
-#ifdef CONFIG_NET_MULTI
 	/* update current ethernet name */
-	{
-		char *act = getenv("ethact");
-		if (act == NULL || strcmp(act, eth_current->name) != 0)
-			setenv("ethact", eth_current->name);
-	}
-#endif
+	act = getenv("ethact");
+	if (act == NULL || strcmp(act, eth_current->name) != 0)
+		setenv("ethact", eth_current->name);
 
 	if (first_failed == eth_current) {
 		NetRestartWrap = 1;
 	}
 }
 
-#ifdef CONFIG_NET_MULTI
 void eth_set_current(void)
 {
 	static char *act = NULL;
@@ -501,7 +494,6 @@ void eth_set_current(void)
 
 	setenv("ethact", eth_current->name);
 }
-#endif
 
 char *eth_get_name (void)
 {

From f29c181cd4a8bd39c256ac8cabb98055a9e672f3 Mon Sep 17 00:00:00 2001
From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Date: Tue, 10 Aug 2010 16:36:49 +0200
Subject: [PATCH 06/15] UEC PHY: Speed up initial PHY neg.

Instead of always performing an autoneg, check if the PHY
already has a link and if it matches one of the requested
modes. Initially only 100MbFD is optimized this way.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 drivers/qe/uec_phy.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 7ea2ae1af7..9be784e6ad 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -351,6 +351,15 @@ static int marvell_config_aneg (struct uec_mii_info *mii_info)
 static int genmii_config_aneg (struct uec_mii_info *mii_info)
 {
 	if (mii_info->autoneg) {
+		/* Speed up the common case, if link is already up, speed and
+		   duplex match, skip auto neg as it already matches */
+		if (!genmii_read_status(mii_info) && mii_info->link)
+			if (mii_info->duplex == DUPLEX_FULL &&
+			    mii_info->speed == SPEED_100)
+				if (mii_info->advertising &
+				    ADVERTISED_100baseT_Full)
+					return 0;
+
 		config_genmii_advert (mii_info);
 		genmii_restart_aneg (mii_info);
 	} else

From a61a81967f57cb657dea9289a1b0810c668bf9ae Mon Sep 17 00:00:00 2001
From: Reinhard Meyer <u-boot@emk-elektronik.de>
Date: Sun, 12 Sep 2010 16:23:49 +0200
Subject: [PATCH 07/15] NET: add ENC28J60 driver using SPI framework

V3: further refinements:
- use priv member instead of container method
- allow setting of MAC address by write_hwaddr method
- avoid shutting down link between commands

Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 drivers/net/Makefile   |   1 +
 drivers/net/enc28j60.c | 978 +++++++++++++++++++++++++++++++++++++++++
 drivers/net/enc28j60.h | 251 +++++++++++
 include/netdev.h       |   2 +
 4 files changed, 1232 insertions(+)
 create mode 100644 drivers/net/enc28j60.c
 create mode 100644 drivers/net/enc28j60.h

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 479954d80c..79eb66b267 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
 COBJS-$(CONFIG_DNET) += dnet.o
 COBJS-$(CONFIG_E1000) += e1000.o
 COBJS-$(CONFIG_EEPRO100) += eepro100.o
+COBJS-$(CONFIG_ENC28J60) += enc28j60.o
 COBJS-$(CONFIG_ENC28J60_LPC2292) += enc28j60_lpc2292.o
 COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
 COBJS-$(CONFIG_ETHOC) += ethoc.o
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
new file mode 100644
index 0000000000..6c161b632f
--- /dev/null
+++ b/drivers/net/enc28j60.c
@@ -0,0 +1,978 @@
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ * Martin Krause, Martin.Krause@tqs.de
+ * reworked original enc28j60.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <spi.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include "enc28j60.h"
+
+/*
+ * IMPORTANT: spi_claim_bus() and spi_release_bus()
+ * are called at begin and end of each of the following functions:
+ * enc_miiphy_read(), enc_miiphy_write(), enc_write_hwaddr(),
+ * enc_init(), enc_recv(), enc_send(), enc_halt()
+ * ALL other functions assume that the bus has already been claimed!
+ * Since NetReceive() might call enc_send() in return, the bus must be
+ * released, NetReceive() called and claimed again.
+ */
+
+/*
+ * Controller memory layout.
+ * We only allow 1 frame for transmission and reserve the rest
+ * for reception to handle as many broadcast packets as possible.
+ * Also use the memory from 0x0000 for receiver buffer. See errata pt. 5
+ * 0x0000 - 0x19ff 6656 bytes receive buffer
+ * 0x1a00 - 0x1fff 1536 bytes transmit buffer =
+ * control(1)+frame(1518)+status(7)+reserve(10).
+ */
+#define ENC_RX_BUF_START	0x0000
+#define ENC_RX_BUF_END		0x19ff
+#define ENC_TX_BUF_START	0x1a00
+#define ENC_TX_BUF_END		0x1fff
+#define ENC_MAX_FRM_LEN		1518
+#define RX_RESET_COUNTER	1000
+
+/*
+ * For non data transfer functions, like phy read/write, set hwaddr, init
+ * we do not need a full, time consuming init including link ready wait.
+ * This enum helps to bring the chip through the minimum necessary inits.
+ */
+enum enc_initstate {none=0, setupdone, linkready};
+typedef struct enc_device {
+	struct eth_device	*dev;	/* back pointer */
+	struct spi_slave	*slave;
+	int			rx_reset_counter;
+	u16			next_pointer;
+	u8			bank;	/* current bank in enc28j60 */
+	enum enc_initstate	initstate;
+} enc_dev_t;
+
+/*
+ * enc_bset:		set bits in a common register
+ * enc_bclr:		clear bits in a common register
+ *
+ * making the reg parameter u8 will give a compile time warning if the
+ * functions are called with a register not accessible in all Banks
+ */
+static void enc_bset(enc_dev_t *enc, const u8 reg, const u8 data)
+{
+	u8 dout[2];
+
+	dout[0] = CMD_BFS(reg);
+	dout[1] = data;
+	spi_xfer(enc->slave, 2 * 8, dout, NULL,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+}
+
+static void enc_bclr(enc_dev_t *enc, const u8 reg, const u8 data)
+{
+	u8 dout[2];
+
+	dout[0] = CMD_BFC(reg);
+	dout[1] = data;
+	spi_xfer(enc->slave, 2 * 8, dout, NULL,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+}
+
+/*
+ * high byte of the register contains bank number:
+ * 0: no bank switch necessary
+ * 1: switch to bank 0
+ * 2: switch to bank 1
+ * 3: switch to bank 2
+ * 4: switch to bank 3
+ */
+static void enc_set_bank(enc_dev_t *enc, const u16 reg)
+{
+	u8 newbank = reg >> 8;
+
+	if (newbank == 0 || newbank == enc->bank)
+		return;
+	switch (newbank) {
+	case 1:
+		enc_bclr(enc, CTL_REG_ECON1,
+			ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
+		break;
+	case 2:
+		enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
+		enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
+		break;
+	case 3:
+		enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
+		enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
+		break;
+	case 4:
+		enc_bset(enc, CTL_REG_ECON1,
+			ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
+		break;
+	}
+	enc->bank = newbank;
+}
+
+/*
+ * local functions to access SPI
+ *
+ * reg: register inside ENC28J60
+ * data: 8/16 bits to write
+ * c: number of retries
+ *
+ * enc_r8:		read 8 bits
+ * enc_r16:		read 16 bits
+ * enc_w8:		write 8 bits
+ * enc_w16:		write 16 bits
+ * enc_w8_retry:	write 8 bits, verify and retry
+ * enc_rbuf:		read from ENC28J60 into buffer
+ * enc_wbuf:		write from buffer into ENC28J60
+ */
+
+/*
+ * MAC and MII registers need a 3 byte SPI transfer to read,
+ * all other registers need a 2 byte SPI transfer.
+ */
+static int enc_reg2nbytes(const u16 reg)
+{
+	/* check if MAC or MII register */
+	return ((reg >= CTL_REG_MACON1 && reg <= CTL_REG_MIRDH) ||
+		(reg >= CTL_REG_MAADR1 && reg <= CTL_REG_MAADR4) ||
+		(reg == CTL_REG_MISTAT)) ? 3 : 2;
+}
+
+/*
+ * Read a byte register
+ */
+static u8 enc_r8(enc_dev_t *enc, const u16 reg)
+{
+	u8 dout[3];
+	u8 din[3];
+	int nbytes = enc_reg2nbytes(reg);
+
+	enc_set_bank(enc, reg);
+	dout[0] = CMD_RCR(reg);
+	spi_xfer(enc->slave, nbytes * 8, dout, din,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+	return din[nbytes-1];
+}
+
+/*
+ * Read a L/H register pair and return a word.
+ * Must be called with the L register's address.
+ */
+static u16 enc_r16(enc_dev_t *enc, const u16 reg)
+{
+	u8 dout[3];
+	u8 din[3];
+	u16 result;
+	int nbytes = enc_reg2nbytes(reg);
+
+	enc_set_bank(enc, reg);
+	dout[0] = CMD_RCR(reg);
+	spi_xfer(enc->slave, nbytes * 8, dout, din,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+	result = din[nbytes-1];
+	dout[0]++; /* next register */
+	spi_xfer(enc->slave, nbytes * 8, dout, din,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+	result |= din[nbytes-1] << 8;
+	return result;
+}
+
+/*
+ * Write a byte register
+ */
+static void enc_w8(enc_dev_t *enc, const u16 reg, const u8 data)
+{
+	u8 dout[2];
+
+	enc_set_bank(enc, reg);
+	dout[0] = CMD_WCR(reg);
+	dout[1] = data;
+	spi_xfer(enc->slave, 2 * 8, dout, NULL,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+}
+
+/*
+ * Write a L/H register pair.
+ * Must be called with the L register's address.
+ */
+static void enc_w16(enc_dev_t *enc, const u16 reg, const u16 data)
+{
+	u8 dout[2];
+
+	enc_set_bank(enc, reg);
+	dout[0] = CMD_WCR(reg);
+	dout[1] = data;
+	spi_xfer(enc->slave, 2 * 8, dout, NULL,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+	dout[0]++; /* next register */
+	dout[1] = data >> 8;
+	spi_xfer(enc->slave, 2 * 8, dout, NULL,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+}
+
+/*
+ * Write a byte register, verify and retry
+ */
+static void enc_w8_retry(enc_dev_t *enc, const u16 reg, const u8 data, const int c)
+{
+	u8 dout[2];
+	u8 readback;
+	int i;
+
+	enc_set_bank(enc, reg);
+	for (i = 0; i < c; i++) {
+		dout[0] = CMD_WCR(reg);
+		dout[1] = data;
+		spi_xfer(enc->slave, 2 * 8, dout, NULL,
+			SPI_XFER_BEGIN | SPI_XFER_END);
+		readback = enc_r8(enc, reg);
+		if (readback == data)
+			break;
+		/* wait 1ms */
+		udelay(1000);
+	}
+	if (i == c) {
+		printf("%s: write reg 0x%03x failed\n", enc->dev->name, reg);
+	}
+}
+
+/*
+ * Read ENC RAM into buffer
+ */
+static void enc_rbuf(enc_dev_t *enc, const u16 length, u8 *buf)
+{
+	u8 dout[1];
+
+	dout[0] = CMD_RBM;
+	spi_xfer(enc->slave, 8, dout, NULL, SPI_XFER_BEGIN);
+	spi_xfer(enc->slave, length * 8, NULL, buf, SPI_XFER_END);
+#ifdef DEBUG
+	puts("Rx:\n");
+	print_buffer(0, buf, 1, length, 0);
+#endif
+}
+
+/*
+ * Write buffer into ENC RAM
+ */
+static void enc_wbuf(enc_dev_t *enc, const u16 length, const u8 *buf, const u8 control)
+{
+	u8 dout[2];
+	dout[0] = CMD_WBM;
+	dout[1] = control;
+	spi_xfer(enc->slave, 2 * 8, dout, NULL, SPI_XFER_BEGIN);
+	spi_xfer(enc->slave, length * 8, buf, NULL, SPI_XFER_END);
+#ifdef DEBUG
+	puts("Tx:\n");
+	print_buffer(0, buf, 1, length, 0);
+#endif
+}
+
+/*
+ * Try to claim the SPI bus.
+ * Print error message on failure.
+ */
+static int enc_claim_bus(enc_dev_t *enc)
+{
+	int rc = spi_claim_bus(enc->slave);
+	if (rc)
+		printf("%s: failed to claim SPI bus\n", enc->dev->name);
+	return rc;
+}
+
+/*
+ * Release previously claimed SPI bus.
+ * This function is mainly for symmetry to enc_claim_bus().
+ * Let the toolchain decide to inline it...
+ */
+static void enc_release_bus(enc_dev_t *enc)
+{
+	spi_release_bus(enc->slave);
+}
+
+/*
+ * Read PHY register
+ */
+static u16 phy_read(enc_dev_t *enc, const u8 addr)
+{
+	uint64_t etime;
+	u8 status;
+
+	enc_w8(enc, CTL_REG_MIREGADR, addr);
+	enc_w8(enc, CTL_REG_MICMD, ENC_MICMD_MIIRD);
+	/* 1 second timeout - only happens on hardware problem */
+	etime = get_ticks() + get_tbclk();
+	/* poll MISTAT.BUSY bit until operation is complete */
+	do
+	{
+		status = enc_r8(enc, CTL_REG_MISTAT);
+	} while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
+	if (status & ENC_MISTAT_BUSY) {
+		printf("%s: timeout reading phy\n", enc->dev->name);
+		return 0;
+	}
+	enc_w8(enc, CTL_REG_MICMD, 0);
+	return enc_r16(enc, CTL_REG_MIRDL);
+}
+
+/*
+ * Write PHY register
+ */
+static void phy_write(enc_dev_t *enc, const u8 addr, const u16 data)
+{
+	uint64_t etime;
+	u8 status;
+
+	enc_w8(enc, CTL_REG_MIREGADR, addr);
+	enc_w16(enc, CTL_REG_MIWRL, data);
+	/* 1 second timeout - only happens on hardware problem */
+	etime = get_ticks() + get_tbclk();
+	/* poll MISTAT.BUSY bit until operation is complete */
+	do
+	{
+		status = enc_r8(enc, CTL_REG_MISTAT);
+	} while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
+	if (status & ENC_MISTAT_BUSY) {
+		printf("%s: timeout writing phy\n", enc->dev->name);
+		return;
+	}
+}
+
+/*
+ * Verify link status, wait if necessary
+ *
+ * Note: with a 10 MBit/s only PHY there is no autonegotiation possible,
+ * half/full duplex is a pure setup matter. For the time being, this driver
+ * will setup in half duplex mode only.
+ */
+static int enc_phy_link_wait(enc_dev_t *enc)
+{
+	u16 status;
+	int duplex;
+	uint64_t etime;
+
+#ifdef CONFIG_ENC_SILENTLINK
+	/* check if we have a link, then just return */
+	status = phy_read(enc, PHY_REG_PHSTAT1);
+	if (status & ENC_PHSTAT1_LLSTAT)
+		return 0;
+#endif
+
+	/* wait for link with 1 second timeout */
+	etime = get_ticks() + get_tbclk();
+	while (get_ticks() <= etime) {
+		status = phy_read(enc, PHY_REG_PHSTAT1);
+		if (status & ENC_PHSTAT1_LLSTAT) {
+			/* now we have a link */
+			status = phy_read(enc, PHY_REG_PHSTAT2);
+			duplex = (status & ENC_PHSTAT2_DPXSTAT) ? 1 : 0;
+			printf("%s: link up, 10Mbps %s-duplex\n",
+				enc->dev->name, duplex ? "full" : "half");
+			return 0;
+		}
+		udelay(1000);
+	}
+
+	/* timeout occured */
+	printf("%s: link down\n", enc->dev->name);
+	return 1;
+}
+
+/*
+ * This function resets the receiver only.
+ */
+static void enc_reset_rx(enc_dev_t *enc)
+{
+	u8 econ1;
+
+	econ1 = enc_r8(enc, CTL_REG_ECON1);
+	if ((econ1 & ENC_ECON1_RXRST) == 0) {
+		enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
+		enc->rx_reset_counter = RX_RESET_COUNTER;
+	}
+}
+
+/*
+ * Reset receiver and reenable it.
+ */
+static void enc_reset_rx_call(enc_dev_t *enc)
+{
+	enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
+	enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
+}
+
+/*
+ * Copy a packet from the receive ring and forward it to
+ * the protocol stack.
+ */
+static void enc_receive(enc_dev_t *enc)
+{
+	u8 *packet = (u8 *)NetRxPackets[0];
+	u16 pkt_len;
+	u16 copy_len;
+	u16 status;
+	u8 eir_reg;
+	u8 pkt_cnt = 0;
+	u16 rxbuf_rdpt;
+	u8 hbuf[6];
+
+	enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
+	do {
+		enc_rbuf(enc, 6, hbuf);
+		enc->next_pointer = hbuf[0] | (hbuf[1] << 8);
+		pkt_len = hbuf[2] | (hbuf[3] << 8);
+		status = hbuf[4] | (hbuf[5] << 8);
+		debug("next_pointer=$%04x pkt_len=%u status=$%04x\n",
+			enc->next_pointer, pkt_len, status);
+		if (pkt_len <= ENC_MAX_FRM_LEN)
+			copy_len = pkt_len;
+		else
+			copy_len = 0;
+		if ((status & (1L << 7)) == 0) /* check Received Ok bit */
+			copy_len = 0;
+		/* check if next pointer is resonable */
+		if (enc->next_pointer >= ENC_TX_BUF_START)
+			copy_len = 0;
+		if (copy_len > 0) {
+			enc_rbuf(enc, copy_len, packet);
+		}
+		/* advance read pointer to next pointer */
+		enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
+		/* decrease packet counter */
+		enc_bset(enc, CTL_REG_ECON2, ENC_ECON2_PKTDEC);
+		/*
+		 * Only odd values should be written to ERXRDPTL,
+		 * see errata B4 pt.13
+		 */
+		rxbuf_rdpt = enc->next_pointer - 1;
+		if ((rxbuf_rdpt < enc_r16(enc, CTL_REG_ERXSTL)) ||
+			(rxbuf_rdpt > enc_r16(enc, CTL_REG_ERXNDL))) {
+			enc_w16(enc, CTL_REG_ERXRDPTL,
+				enc_r16(enc, CTL_REG_ERXNDL));
+		} else {
+			enc_w16(enc, CTL_REG_ERXRDPTL, rxbuf_rdpt);
+		}
+		/* read pktcnt */
+		pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
+		if (copy_len == 0) {
+			eir_reg = enc_r8(enc, CTL_REG_EIR);
+			enc_reset_rx(enc);
+			printf("%s: receive copy_len=0\n", enc->dev->name);
+			continue;
+		}
+		/*
+		 * Because NetReceive() might call enc_send(), we need to
+		 * release the SPI bus, call NetReceive(), reclaim the bus
+		 */
+		enc_release_bus(enc);
+		NetReceive(packet, pkt_len);
+		if (enc_claim_bus(enc))
+			return;
+		eir_reg = enc_r8(enc, CTL_REG_EIR);
+	} while (pkt_cnt);
+	/* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
+}
+
+/*
+ * Poll for completely received packets.
+ */
+static void enc_poll(enc_dev_t *enc)
+{
+	u8 eir_reg;
+	u8 estat_reg;
+	u8 pkt_cnt;
+
+#ifdef CONFIG_USE_IRQ
+	/* clear global interrupt enable bit in enc28j60 */
+	enc_bclr(enc, CTL_REG_EIE, ENC_EIE_INTIE);
+#endif
+	estat_reg = enc_r8(enc, CTL_REG_ESTAT);
+	eir_reg = enc_r8(enc, CTL_REG_EIR);
+	if (eir_reg & ENC_EIR_TXIF) {
+		/* clear TXIF bit in EIR */
+		enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXIF);
+	}
+	/* We have to use pktcnt and not pktif bit, see errata pt. 6 */
+	pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
+	if (pkt_cnt > 0) {
+		if ((eir_reg & ENC_EIR_PKTIF) == 0) {
+			debug("enc_poll: pkt cnt > 0, but pktif not set\n");
+		}
+		enc_receive(enc);
+		/*
+		 * clear PKTIF bit in EIR, this should not need to be done
+		 * but it seems like we get problems if we do not
+		 */
+		enc_bclr(enc, CTL_REG_EIR, ENC_EIR_PKTIF);
+	}
+	if (eir_reg & ENC_EIR_RXERIF) {
+		printf("%s: rx error\n", enc->dev->name);
+		enc_bclr(enc, CTL_REG_EIR, ENC_EIR_RXERIF);
+	}
+	if (eir_reg & ENC_EIR_TXERIF) {
+		printf("%s: tx error\n", enc->dev->name);
+		enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF);
+	}
+#ifdef CONFIG_USE_IRQ
+	/* set global interrupt enable bit in enc28j60 */
+	enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
+#endif
+}
+
+/*
+ * Completely Reset the ENC
+ */
+static void enc_reset(enc_dev_t *enc)
+{
+	u8 dout[1];
+
+	dout[0] = CMD_SRC;
+	spi_xfer(enc->slave, 8, dout, NULL,
+		SPI_XFER_BEGIN | SPI_XFER_END);
+	/* sleep 1 ms. See errata pt. 2 */
+	udelay(1000);
+}
+
+/*
+ * Initialisation data for most of the ENC registers
+ */
+static const u16 enc_initdata[] = {
+	/*
+	 * Setup the buffer space. The reset values are valid for the
+	 * other pointers.
+	 *
+	 * We shall not write to ERXST, see errata pt. 5. Instead we
+	 * have to make sure that ENC_RX_BUS_START is 0.
+	 */
+	CTL_REG_ERXSTL, ENC_RX_BUF_START,
+	CTL_REG_ERXSTH, ENC_RX_BUF_START >> 8,
+	CTL_REG_ERXNDL, ENC_RX_BUF_END,
+	CTL_REG_ERXNDH, ENC_RX_BUF_END >> 8,
+	CTL_REG_ERDPTL, ENC_RX_BUF_START,
+	CTL_REG_ERDPTH, ENC_RX_BUF_START >> 8,
+	/*
+	 * Set the filter to receive only good-CRC, unicast and broadcast
+	 * frames.
+	 * Note: some DHCP servers return their answers as broadcasts!
+	 * So its unwise to remove broadcast from this. This driver
+	 * might incur receiver overruns with packet loss on a broadcast
+	 * flooded network.
+	 */
+	CTL_REG_ERXFCON, ENC_RFR_BCEN | ENC_RFR_UCEN | ENC_RFR_CRCEN,
+
+	/* enable MAC to receive frames */
+	CTL_REG_MACON1,
+		ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS,
+
+	/* configure pad, tx-crc and duplex */
+	CTL_REG_MACON3,
+		ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN |
+		ENC_MACON3_FRMLNEN,
+
+	/* Allow infinite deferals if the medium is continously busy */
+	CTL_REG_MACON4, ENC_MACON4_DEFER,
+
+	/* Late collisions occur beyond 63 bytes */
+	CTL_REG_MACLCON2, 63,
+
+	/*
+	 * Set (low byte) Non-Back-to_Back Inter-Packet Gap.
+	 * Recommended 0x12
+	 */
+	CTL_REG_MAIPGL, 0x12,
+
+	/*
+	 * Set (high byte) Non-Back-to_Back Inter-Packet Gap.
+	 * Recommended 0x0c for half-duplex. Nothing for full-duplex
+	 */
+	CTL_REG_MAIPGH, 0x0C,
+
+	/* set maximum frame length */
+	CTL_REG_MAMXFLL, ENC_MAX_FRM_LEN,
+	CTL_REG_MAMXFLH, ENC_MAX_FRM_LEN >> 8,
+
+	/*
+	 * Set MAC back-to-back inter-packet gap.
+	 * Recommended 0x12 for half duplex
+	 * and 0x15 for full duplex.
+	 */
+	CTL_REG_MABBIPG, 0x12,
+
+	/* end of table */
+	0xffff
+};
+
+/*
+ * Wait for the XTAL oscillator to become ready
+ */
+static int enc_clock_wait(enc_dev_t *enc)
+{
+	uint64_t etime;
+
+	/* one second timeout */
+	etime = get_ticks() + get_tbclk();
+
+	/*
+	 * Wait for CLKRDY to become set (i.e., check that we can
+	 * communicate with the ENC)
+	 */
+	do
+	{
+		if (enc_r8(enc, CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY)
+			return 0;
+	} while (get_ticks() <= etime);
+
+	printf("%s: timeout waiting for CLKRDY\n", enc->dev->name);
+	return -1;
+}
+
+/*
+ * Write the MAC address into the ENC
+ */
+static int enc_write_macaddr(enc_dev_t *enc)
+{
+	unsigned char *p = enc->dev->enetaddr;
+
+	enc_w8_retry(enc, CTL_REG_MAADR5, *p++, 5);
+	enc_w8_retry(enc, CTL_REG_MAADR4, *p++, 5);
+	enc_w8_retry(enc, CTL_REG_MAADR3, *p++, 5);
+	enc_w8_retry(enc, CTL_REG_MAADR2, *p++, 5);
+	enc_w8_retry(enc, CTL_REG_MAADR1, *p++, 5);
+	enc_w8_retry(enc, CTL_REG_MAADR0, *p, 5);
+	return 0;
+}
+
+/*
+ * Setup most of the ENC registers
+ */
+static int enc_setup(enc_dev_t *enc)
+{
+	u16 phid1 = 0;
+	u16 phid2 = 0;
+	const u16 *tp;
+
+	/* reset enc struct values */
+	enc->next_pointer = ENC_RX_BUF_START;
+	enc->rx_reset_counter = RX_RESET_COUNTER;
+	enc->bank = 0xff;	/* invalidate current bank in enc28j60 */
+
+	/* verify PHY identification */
+	phid1 = phy_read(enc, PHY_REG_PHID1);
+	phid2 = phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK;
+	if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) {
+		printf("%s: failed to identify PHY. Found %04x:%04x\n",
+			enc->dev->name, phid1, phid2);
+		return -1;
+	}
+
+	/* now program registers */
+	for (tp = enc_initdata; *tp != 0xffff; tp += 2)
+		enc_w8_retry(enc, tp[0], tp[1], 10);
+
+	/*
+	 * Prevent automatic loopback of data beeing transmitted by setting
+	 * ENC_PHCON2_HDLDIS
+	 */
+	phy_write(enc, PHY_REG_PHCON2, (1<<8));
+
+	/*
+	 * LEDs configuration
+	 * LEDA: LACFG = 0100 -> display link status
+	 * LEDB: LBCFG = 0111 -> display TX & RX activity
+	 * STRCH = 1 -> LED pulses
+	 */
+	phy_write(enc, PHY_REG_PHLCON, 0x0472);
+
+	/* Reset PDPXMD-bit => half duplex */
+	phy_write(enc, PHY_REG_PHCON1, 0);
+
+#ifdef CONFIG_USE_IRQ
+	/* enable interrupts */
+	enc_bset(enc, CTL_REG_EIE, ENC_EIE_PKTIE);
+	enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXIE);
+	enc_bset(enc, CTL_REG_EIE, ENC_EIE_RXERIE);
+	enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXERIE);
+	enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
+#endif
+
+	return 0;
+}
+
+/*
+ * Check if ENC has been initialized.
+ * If not, try to initialize it.
+ * Remember initialized state in struct.
+ */
+static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate)
+{
+	if (enc->initstate >= requiredstate)
+		return 0;
+
+	if (enc->initstate < setupdone) {
+		/* Initialize the ENC only */
+		enc_reset(enc);
+		/* if any of functions fails, skip the rest and return an error */
+		if (enc_clock_wait(enc) || enc_setup(enc) || enc_write_macaddr(enc)) {
+			return -1;
+		}
+		enc->initstate = setupdone;
+	}
+	/* if that's all we need, return here */
+	if (enc->initstate >= requiredstate)
+		return 0;
+
+	/* now wait for link ready condition */
+	if (enc_phy_link_wait(enc)) {
+		return -1;
+	}
+	enc->initstate = linkready;
+	return 0;
+}
+
+#if defined(CONFIG_CMD_MII)
+/*
+ * Read a PHY register.
+ *
+ * This function is registered with miiphy_register().
+ */
+int enc_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
+{
+	struct eth_device *dev = eth_get_dev_by_name(devname);
+	enc_dev_t *enc;
+
+	if (!dev || phy_adr != 0)
+		return -1;
+
+	enc = dev->priv;
+	if (enc_claim_bus(enc))
+		return -1;
+	if (enc_initcheck(enc, setupdone)) {
+		enc_release_bus(enc);
+		return -1;
+	}
+	*value = phy_read(enc, reg);
+	enc_release_bus(enc);
+	return 0;
+}
+
+/*
+ * Write a PHY register.
+ *
+ * This function is registered with miiphy_register().
+ */
+int enc_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
+{
+	struct eth_device *dev = eth_get_dev_by_name(devname);
+	enc_dev_t *enc;
+
+	if (!dev || phy_adr != 0)
+		return -1;
+
+	enc = dev->priv;
+	if (enc_claim_bus(enc))
+		return -1;
+	if (enc_initcheck(enc, setupdone)) {
+		enc_release_bus(enc);
+		return -1;
+	}
+	phy_write(enc, reg, value);
+	enc_release_bus(enc);
+	return 0;
+}
+#endif
+
+/*
+ * Write hardware (MAC) address.
+ *
+ * This function entered into eth_device structure.
+ */
+static int enc_write_hwaddr(struct eth_device *dev)
+{
+	enc_dev_t *enc = dev->priv;
+
+	if (enc_claim_bus(enc))
+		return -1;
+	if (enc_initcheck(enc, setupdone)) {
+		enc_release_bus(enc);
+		return -1;
+	}
+	enc_release_bus(enc);
+	return 0;
+}
+
+/*
+ * Initialize ENC28J60 for use.
+ *
+ * This function entered into eth_device structure.
+ */
+static int enc_init(struct eth_device *dev, bd_t *bis)
+{
+	enc_dev_t *enc = dev->priv;
+
+	if (enc_claim_bus(enc))
+		return -1;
+	if (enc_initcheck(enc, linkready)) {
+		enc_release_bus(enc);
+		return -1;
+	}
+	/* enable receive */
+	enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
+	enc_release_bus(enc);
+	return 0;
+}
+
+/*
+ * Check for received packets.
+ *
+ * This function entered into eth_device structure.
+ */
+static int enc_recv(struct eth_device *dev)
+{
+	enc_dev_t *enc = dev->priv;
+
+	if (enc_claim_bus(enc))
+		return -1;
+	if (enc_initcheck(enc, linkready)) {
+		enc_release_bus(enc);
+		return -1;
+	}
+	/* Check for dead receiver */
+	if (enc->rx_reset_counter > 0)
+		enc->rx_reset_counter--;
+	else
+		enc_reset_rx_call(enc);
+	enc_poll(enc);
+	enc_release_bus(enc);
+	return 0;
+}
+
+/*
+ * Send a packet.
+ *
+ * This function entered into eth_device structure.
+ *
+ * Should we wait here until we have a Link? Or shall we leave that to
+ * protocol retries?
+ */
+static int enc_send(
+	struct eth_device *dev,
+	volatile void *packet,
+	int length)
+{
+	enc_dev_t *enc = dev->priv;
+
+	if (enc_claim_bus(enc))
+		return -1;
+	if (enc_initcheck(enc, linkready)) {
+		enc_release_bus(enc);
+		return -1;
+	}
+	/* setup transmit pointers */
+	enc_w16(enc, CTL_REG_EWRPTL, ENC_TX_BUF_START);
+	enc_w16(enc, CTL_REG_ETXNDL, length + ENC_TX_BUF_START);
+	enc_w16(enc, CTL_REG_ETXSTL, ENC_TX_BUF_START);
+	/* write packet to ENC */
+	enc_wbuf(enc, length, (u8 *) packet, 0x00);
+	/*
+	 * Check that the internal transmit logic has not been altered
+	 * by excessive collisions. Reset transmitter if so.
+	 * See Errata B4 12 and 14.
+	 */
+	if (enc_r8(enc, CTL_REG_EIR) & ENC_EIR_TXERIF) {
+		enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
+		enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
+	}
+	enc_bclr(enc, CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
+	/* start transmitting */
+	enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRTS);
+	enc_release_bus(enc);
+	return 0;
+}
+
+/*
+ * Finish use of ENC.
+ *
+ * This function entered into eth_device structure.
+ */
+static void enc_halt(struct eth_device *dev)
+{
+	enc_dev_t *enc = dev->priv;
+
+	if (enc_claim_bus(enc))
+		return;
+	/* Just disable receiver */
+	enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
+	enc_release_bus(enc);
+}
+
+/*
+ * This is the only exported function.
+ *
+ * It may be called several times with different bus:cs combinations.
+ */
+int enc28j60_initialize(unsigned int bus, unsigned int cs,
+	unsigned int max_hz, unsigned int mode)
+{
+	struct eth_device *dev;
+	enc_dev_t *enc;
+
+	/* try to allocate, check and clear eth_device object */
+	dev = malloc(sizeof(*dev));
+	if (!dev) {
+		return -1;
+	}
+	memset(dev, 0, sizeof(*dev));
+
+	/* try to allocate, check and clear enc_dev_t object */
+	enc = malloc(sizeof(*enc));
+	if (!enc) {
+		free(dev);
+		return -1;
+	}
+	memset(enc, 0, sizeof(*enc));
+
+	/* try to setup the SPI slave */
+	enc->slave = spi_setup_slave(bus, cs, max_hz, mode);
+	if (!enc->slave) {
+		printf("enc28j60: invalid SPI device %i:%i\n", bus, cs);
+		free(enc);
+		free(dev);
+		return -1;
+	}
+
+	enc->dev = dev;
+	/* now fill the eth_device object */
+	dev->priv = enc;
+	dev->init = enc_init;
+	dev->halt = enc_halt;
+	dev->send = enc_send;
+	dev->recv = enc_recv;
+	dev->write_hwaddr = enc_write_hwaddr;
+	sprintf(dev->name, "enc%i.%i", bus, cs);
+	eth_register(dev);
+#if defined(CONFIG_CMD_MII)
+	miiphy_register(dev->name, enc_miiphy_read, enc_miiphy_write);
+#endif
+	return 0;
+}
diff --git a/drivers/net/enc28j60.h b/drivers/net/enc28j60.h
new file mode 100644
index 0000000000..888c59903d
--- /dev/null
+++ b/drivers/net/enc28j60.h
@@ -0,0 +1,251 @@
+/*
+ * (X) extracted from enc28j60.c
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _enc28j60_h
+#define _enc28j60_h
+
+/*
+ * SPI Commands
+ *
+ * Bits 7-5: Command
+ * Bits 4-0: Register
+ */
+#define CMD_RCR(x)	(0x00+((x)&0x1f))	/* Read Control Register */
+#define CMD_RBM		0x3a			/* Read Buffer Memory */
+#define CMD_WCR(x)	(0x40+((x)&0x1f))	/* Write Control Register */
+#define CMD_WBM		0x7a			/* Write Buffer Memory */
+#define CMD_BFS(x)	(0x80+((x)&0x1f))	/* Bit Field Set */
+#define CMD_BFC(x)	(0xa0+((x)&0x1f))	/* Bit Field Clear */
+#define CMD_SRC		0xff			/* System Reset Command */
+
+/* NEW: encode (bank number+1) in upper byte */
+
+/* Common Control Registers accessible in all Banks */
+#define CTL_REG_EIE		0x01B
+#define CTL_REG_EIR		0x01C
+#define CTL_REG_ESTAT		0x01D
+#define CTL_REG_ECON2		0x01E
+#define CTL_REG_ECON1		0x01F
+
+/* Control Registers accessible in Bank 0 */
+#define CTL_REG_ERDPTL		0x100
+#define CTL_REG_ERDPTH		0x101
+#define CTL_REG_EWRPTL		0x102
+#define CTL_REG_EWRPTH		0x103
+#define CTL_REG_ETXSTL		0x104
+#define CTL_REG_ETXSTH		0x105
+#define CTL_REG_ETXNDL		0x106
+#define CTL_REG_ETXNDH		0x107
+#define CTL_REG_ERXSTL		0x108
+#define CTL_REG_ERXSTH		0x109
+#define CTL_REG_ERXNDL		0x10A
+#define CTL_REG_ERXNDH		0x10B
+#define CTL_REG_ERXRDPTL	0x10C
+#define CTL_REG_ERXRDPTH	0x10D
+#define CTL_REG_ERXWRPTL	0x10E
+#define CTL_REG_ERXWRPTH	0x10F
+#define CTL_REG_EDMASTL		0x110
+#define CTL_REG_EDMASTH		0x111
+#define CTL_REG_EDMANDL		0x112
+#define CTL_REG_EDMANDH		0x113
+#define CTL_REG_EDMADSTL	0x114
+#define CTL_REG_EDMADSTH	0x115
+#define CTL_REG_EDMACSL		0x116
+#define CTL_REG_EDMACSH		0x117
+
+/* Control Registers accessible in Bank 1 */
+#define CTL_REG_EHT0		0x200
+#define CTL_REG_EHT1		0x201
+#define CTL_REG_EHT2		0x202
+#define CTL_REG_EHT3		0x203
+#define CTL_REG_EHT4		0x204
+#define CTL_REG_EHT5		0x205
+#define CTL_REG_EHT6		0x206
+#define CTL_REG_EHT7		0x207
+#define CTL_REG_EPMM0		0x208
+#define CTL_REG_EPMM1		0x209
+#define CTL_REG_EPMM2		0x20A
+#define CTL_REG_EPMM3		0x20B
+#define CTL_REG_EPMM4		0x20C
+#define CTL_REG_EPMM5		0x20D
+#define CTL_REG_EPMM6		0x20E
+#define CTL_REG_EPMM7		0x20F
+#define CTL_REG_EPMCSL		0x210
+#define CTL_REG_EPMCSH		0x211
+#define CTL_REG_EPMOL		0x214
+#define CTL_REG_EPMOH		0x215
+#define CTL_REG_EWOLIE		0x216
+#define CTL_REG_EWOLIR		0x217
+#define CTL_REG_ERXFCON		0x218
+#define CTL_REG_EPKTCNT		0x219
+
+/* Control Registers accessible in Bank 2 */
+#define CTL_REG_MACON1		0x300
+#define CTL_REG_MACON2		0x301
+#define CTL_REG_MACON3		0x302
+#define CTL_REG_MACON4		0x303
+#define CTL_REG_MABBIPG		0x304
+#define CTL_REG_MAIPGL		0x306
+#define CTL_REG_MAIPGH		0x307
+#define CTL_REG_MACLCON1	0x308
+#define CTL_REG_MACLCON2	0x309
+#define CTL_REG_MAMXFLL		0x30A
+#define CTL_REG_MAMXFLH		0x30B
+#define CTL_REG_MAPHSUP		0x30D
+#define CTL_REG_MICON		0x311
+#define CTL_REG_MICMD		0x312
+#define CTL_REG_MIREGADR	0x314
+#define CTL_REG_MIWRL		0x316
+#define CTL_REG_MIWRH		0x317
+#define CTL_REG_MIRDL		0x318
+#define CTL_REG_MIRDH		0x319
+
+/* Control Registers accessible in Bank 3 */
+#define CTL_REG_MAADR1		0x400
+#define CTL_REG_MAADR0		0x401
+#define CTL_REG_MAADR3		0x402
+#define CTL_REG_MAADR2		0x403
+#define CTL_REG_MAADR5		0x404
+#define CTL_REG_MAADR4		0x405
+#define CTL_REG_EBSTSD		0x406
+#define CTL_REG_EBSTCON		0x407
+#define CTL_REG_EBSTCSL		0x408
+#define CTL_REG_EBSTCSH		0x409
+#define CTL_REG_MISTAT		0x40A
+#define CTL_REG_EREVID		0x412
+#define CTL_REG_ECOCON		0x415
+#define CTL_REG_EFLOCON		0x417
+#define CTL_REG_EPAUSL		0x418
+#define CTL_REG_EPAUSH		0x419
+
+/* PHY Register */
+#define PHY_REG_PHCON1		0x00
+#define PHY_REG_PHSTAT1		0x01
+#define PHY_REG_PHID1		0x02
+#define PHY_REG_PHID2		0x03
+#define PHY_REG_PHCON2		0x10
+#define PHY_REG_PHSTAT2		0x11
+#define PHY_REG_PHLCON		0x14
+
+/* Receive Filter Register (ERXFCON) bits */
+#define ENC_RFR_UCEN		0x80
+#define ENC_RFR_ANDOR		0x40
+#define ENC_RFR_CRCEN		0x20
+#define ENC_RFR_PMEN		0x10
+#define ENC_RFR_MPEN		0x08
+#define ENC_RFR_HTEN		0x04
+#define ENC_RFR_MCEN		0x02
+#define ENC_RFR_BCEN		0x01
+
+/* ECON1 Register Bits */
+#define ENC_ECON1_TXRST		0x80
+#define ENC_ECON1_RXRST		0x40
+#define ENC_ECON1_DMAST		0x20
+#define ENC_ECON1_CSUMEN	0x10
+#define ENC_ECON1_TXRTS		0x08
+#define ENC_ECON1_RXEN		0x04
+#define ENC_ECON1_BSEL1		0x02
+#define ENC_ECON1_BSEL0		0x01
+
+/* ECON2 Register Bits */
+#define ENC_ECON2_AUTOINC	0x80
+#define ENC_ECON2_PKTDEC	0x40
+#define ENC_ECON2_PWRSV		0x20
+#define ENC_ECON2_VRPS		0x08
+
+/* EIR Register Bits */
+#define ENC_EIR_PKTIF		0x40
+#define ENC_EIR_DMAIF		0x20
+#define ENC_EIR_LINKIF		0x10
+#define ENC_EIR_TXIF		0x08
+#define ENC_EIR_WOLIF		0x04
+#define ENC_EIR_TXERIF		0x02
+#define ENC_EIR_RXERIF		0x01
+
+/* ESTAT Register Bits */
+#define ENC_ESTAT_INT		0x80
+#define ENC_ESTAT_LATECOL	0x10
+#define ENC_ESTAT_RXBUSY	0x04
+#define ENC_ESTAT_TXABRT	0x02
+#define ENC_ESTAT_CLKRDY	0x01
+
+/* EIE Register Bits */
+#define ENC_EIE_INTIE		0x80
+#define ENC_EIE_PKTIE		0x40
+#define ENC_EIE_DMAIE		0x20
+#define ENC_EIE_LINKIE		0x10
+#define ENC_EIE_TXIE		0x08
+#define ENC_EIE_WOLIE		0x04
+#define ENC_EIE_TXERIE		0x02
+#define ENC_EIE_RXERIE		0x01
+
+/* MACON1 Register Bits */
+#define ENC_MACON1_LOOPBK	0x10
+#define ENC_MACON1_TXPAUS	0x08
+#define ENC_MACON1_RXPAUS	0x04
+#define ENC_MACON1_PASSALL	0x02
+#define ENC_MACON1_MARXEN	0x01
+
+/* MACON2 Register Bits */
+#define ENC_MACON2_MARST	0x80
+#define ENC_MACON2_RNDRST	0x40
+#define ENC_MACON2_MARXRST	0x08
+#define ENC_MACON2_RFUNRST	0x04
+#define ENC_MACON2_MATXRST	0x02
+#define ENC_MACON2_TFUNRST	0x01
+
+/* MACON3 Register Bits */
+#define ENC_MACON3_PADCFG2	0x80
+#define ENC_MACON3_PADCFG1	0x40
+#define ENC_MACON3_PADCFG0	0x20
+#define ENC_MACON3_TXCRCEN	0x10
+#define ENC_MACON3_PHDRLEN	0x08
+#define ENC_MACON3_HFRMEN	0x04
+#define ENC_MACON3_FRMLNEN	0x02
+#define ENC_MACON3_FULDPX	0x01
+
+/* MACON4 Register Bits */
+#define ENC_MACON4_DEFER	0x40
+
+/* MICMD Register Bits */
+#define ENC_MICMD_MIISCAN	0x02
+#define ENC_MICMD_MIIRD		0x01
+
+/* MISTAT Register Bits */
+#define ENC_MISTAT_NVALID	0x04
+#define ENC_MISTAT_SCAN		0x02
+#define ENC_MISTAT_BUSY		0x01
+
+/* PHID1 and PHID2 values */
+#define ENC_PHID1_VALUE		0x0083
+#define ENC_PHID2_VALUE		0x1400
+#define ENC_PHID2_MASK		0xFC00
+
+/* PHCON1 values */
+#define	ENC_PHCON1_PDPXMD	0x0100
+
+/* PHSTAT1 values */
+#define	ENC_PHSTAT1_LLSTAT	0x0004
+
+/* PHSTAT2 values */
+#define	ENC_PHSTAT2_LSTAT	0x0400
+#define	ENC_PHSTAT2_DPXSTAT	0x0200
+
+#endif
diff --git a/include/netdev.h b/include/netdev.h
index 71fe805611..64e5816013 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -54,6 +54,8 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
 int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
 int e1000_initialize(bd_t *bis);
 int eepro100_initialize(bd_t *bis);
+int enc28j60_initialize(unsigned int bus, unsigned int cs,
+	unsigned int max_hz, unsigned int mode);
 int ep93xx_eth_initialize(u8 dev_num, int base_addr);
 int ethoc_initialize(u8 dev_num, int base_addr);
 int eth_3com_initialize (bd_t * bis);

From e63ac4cf11b8c4a86c692b9c22c49402228a22c4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= <andreas.devel@googlemail.com>
Date: Thu, 7 Oct 2010 09:44:46 +0200
Subject: [PATCH 08/15] drivers/net/at91_emac.c: increase timeout for
 autonegotiation
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This patch increases timeout for autonegotiation from 1 second to 3 seconds.
Some boards (e.g. at91rm9200ek) did not negotiate within 1 second.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 drivers/net/at91_emac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c
index d82459b1ce..6e42bfe1d7 100644
--- a/drivers/net/at91_emac.c
+++ b/drivers/net/at91_emac.c
@@ -208,7 +208,7 @@ static int at91emac_phy_reset(struct eth_device *netdev)
 	at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
 		(BMCR_ANENABLE | BMCR_ANRESTART));
 
-	for (i = 0; i < 100000 / 100; i++) {
+	for (i = 0; i < 30000; i++) {
 		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
 			MII_BMSR, &status);
 		if (status & BMSR_ANEGCOMPLETE)

From 77179067db7353c049403fe31701c35d52458d26 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= <andreas.devel@googlemail.com>
Date: Thu, 7 Oct 2010 09:44:47 +0200
Subject: [PATCH 09/15] drivers/net/at91_emac.c: change return values
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Some return values pretended correct pass. This patch changes them according
to README.drivers.net. This patch changes e.g. command 'dhcp' to stop after
errorneous autonegotiation.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 drivers/net/at91_emac.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c
index 6e42bfe1d7..c525eeda42 100644
--- a/drivers/net/at91_emac.c
+++ b/drivers/net/at91_emac.c
@@ -221,7 +221,7 @@ static int at91emac_phy_reset(struct eth_device *netdev)
 	} else {
 		printf("%s: Autonegotiation timed out (status=0x%04x)\n",
 		       netdev->name, status);
-		return 1;
+		return -1;
 	}
 	return 0;
 }
@@ -240,7 +240,7 @@ static int at91emac_phy_init(struct eth_device *netdev)
 		MII_PHYSID1, &phy_id);
 	if (phy_id == 0xffff) {
 		printf("%s: No PHY present\n", netdev->name);
-		return 1;
+		return -1;
 	}
 
 	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
@@ -249,7 +249,7 @@ static int at91emac_phy_init(struct eth_device *netdev)
 	if (!(status & BMSR_LSTATUS)) {
 		/* Try to re-negotiate if we don't have link already. */
 		if (at91emac_phy_reset(netdev))
-			return 2;
+			return -2;
 
 		for (i = 0; i < 100000 / 100; i++) {
 			at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
@@ -261,7 +261,7 @@ static int at91emac_phy_init(struct eth_device *netdev)
 	}
 	if (!(status & BMSR_LSTATUS)) {
 		VERBOSEP("%s: link down\n", netdev->name);
-		return 3;
+		return -3;
 	} else {
 		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
 			MII_ADVERTISE, &adv);
@@ -286,7 +286,7 @@ int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
 	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
 
 	if (!(stat1 & BMSR_LSTATUS))	/* link status up? */
-		return 1;
+		return -1;
 
 	if (stat1 & BMSR_100FULL) {
 		/*set Emac for 100BaseTX and Full Duplex  */
@@ -321,7 +321,7 @@ int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
 			&emac->cfg);
 		return 0;
 	}
-	return 1;
+	return 0;
 }
 
 static int at91emac_init(struct eth_device *netdev, bd_t *bd)
@@ -387,7 +387,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd)
 		at91emac_UpdateLinkSpeed(emac);
 		return 0;
 	}
-	return 1;
+	return -1;
 }
 
 static void at91emac_halt(struct eth_device *netdev)
@@ -489,11 +489,11 @@ int at91emac_register(bd_t *bis, unsigned long iobase)
 		iobase = AT91_EMAC_BASE;
 	emac = malloc(sizeof(*emac)+512);
 	if (emac == NULL)
-		return 1;
+		return -1;
 	dev = malloc(sizeof(*dev));
 	if (dev == NULL) {
 		free(emac);
-		return 1;
+		return -1;
 	}
 	/* alignment as per Errata (64 bytes) is insufficient! */
 	emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);

From f87a6f27e61ead22fd87bd4f38eadad82dc94b66 Mon Sep 17 00:00:00 2001
From: Ilya Yanok <yanok@emcraft.com>
Date: Thu, 19 Aug 2010 11:09:06 +0200
Subject: [PATCH 10/15] mpc5xxx_fec: add call to reset_phy() after PHY
 initialization

Some boards need their board-specific PHY quirks to be called
to PHY to work normally. As mpc5xxx_fec driver uses on demand
PHY initialization and can even reinit PHY during normal operation
we can't count on reset_phy() call from arch/<arch>/lib/board.c
(it is most likely called _before_ we init the PHY from the
driver) so we need to add call to reset_phy() directly in the
driver.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 drivers/net/mpc5xxx_fec.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c
index c88e596c01..bc8c9222dc 100644
--- a/drivers/net/mpc5xxx_fec.c
+++ b/drivers/net/mpc5xxx_fec.c
@@ -249,6 +249,13 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 
 	mpc5xxx_fec_init_phy(dev, bis);
 
+	/*
+	 * Call board-specific PHY fixups (if any)
+	 */
+#ifdef CONFIG_RESET_PHY_R
+	reset_phy();
+#endif
+
 	/*
 	 * Initialize RxBD/TxBD rings
 	 */

From 3f91ec0fa1ceab413fa2e74b4ffd37ab505cc66c Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 11 Oct 2010 11:41:46 +1000
Subject: [PATCH 11/15] net: Fix emaclite driver to support little-endian
 microblaze

Support New emaclite AXI IP.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 drivers/net/xilinx_emaclite.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 0820daa2bb..74a201259b 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -322,7 +322,7 @@ int eth_rx (void)
 #endif
 	}
 	/* Get the length of the frame that arrived */
-	switch(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC)) &
+	switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
 			0xFFFF0000 ) >> 16) {
 		case 0x806:
 			length = 42 + 20; /* FIXME size of ARP */
@@ -330,7 +330,7 @@ int eth_rx (void)
 			break;
 		case 0x800:
 			length = 14 + 14 +
-			(((in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10)) &
+			(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0x10))) &
 			0xFFFF0000) >> 16); /* FIXME size of IP packet */
 			debug ("IP Packet\n");
 			break;

From bf6cb247a5df202fbed4fd43df477d863b68fbe1 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Thu, 30 Sep 2010 11:25:48 -0500
Subject: [PATCH 12/15] rarp: Condtionally compile rarp support

Most people don't use the 'rarpboot' command, so only enable it when
CONFIG_CMD_RARP is defined.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 common/cmd_net.c         |  2 ++
 include/config_cmd_all.h |  1 +
 net/Makefile             |  2 +-
 net/net.c                | 11 +++++++++--
 4 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/common/cmd_net.c b/common/cmd_net.c
index 3ffb9df1de..44d17db19c 100644
--- a/common/cmd_net.c
+++ b/common/cmd_net.c
@@ -54,6 +54,7 @@ U_BOOT_CMD(
 	"[loadAddress] [[hostIPaddr:]bootfilename]"
 );
 
+#ifdef CONFIG_CMD_RARP
 int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	return netboot_common (RARP, cmdtp, argc, argv);
@@ -64,6 +65,7 @@ U_BOOT_CMD(
 	"boot image via network using RARP/TFTP protocol",
 	"[loadAddress] [[hostIPaddr:]bootfilename]"
 );
+#endif
 
 #if defined(CONFIG_CMD_DHCP)
 int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index 746bf18f04..cdc5ff10fa 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -70,6 +70,7 @@
 #define CONFIG_CMD_PORTIO	/* Port I/O			*/
 #define CONFIG_CMD_REGINFO	/* Register dump		*/
 #define CONFIG_CMD_REISER	/* Reiserfs support		*/
+#define CONFIG_CMD_RARP		/* rarpboot support		*/
 #define CONFIG_CMD_RUN		/* run command in env variable	*/
 #define CONFIG_CMD_SAVEENV	/* saveenv			*/
 #define CONFIG_CMD_SAVES	/* save S record dump		*/
diff --git a/net/Makefile b/net/Makefile
index 4f819dd515..216d1ec959 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -32,7 +32,7 @@ COBJS-$(CONFIG_CMD_DNS)  += dns.o
 COBJS-$(CONFIG_CMD_NET)  += eth.o
 COBJS-$(CONFIG_CMD_NET)  += net.o
 COBJS-$(CONFIG_CMD_NFS)  += nfs.o
-COBJS-$(CONFIG_CMD_NET)  += rarp.o
+COBJS-$(CONFIG_CMD_RARP) += rarp.o
 COBJS-$(CONFIG_CMD_SNTP) += sntp.o
 COBJS-$(CONFIG_CMD_NET)  += tftp.o
 
diff --git a/net/net.c b/net/net.c
index 33fcd90cd4..d5a5429d1c 100644
--- a/net/net.c
+++ b/net/net.c
@@ -80,7 +80,9 @@
 #include <net.h>
 #include "bootp.h"
 #include "tftp.h"
+#ifdef CONFIG_CMD_RARP
 #include "rarp.h"
+#endif
 #include "nfs.h"
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
@@ -401,11 +403,13 @@ restart:
 			BootpRequest ();
 			break;
 
+#if defined(CONFIG_CMD_RARP)
 		case RARP:
 			RarpTry = 0;
 			NetOurIP = 0;
 			RarpRequest ();
 			break;
+#endif
 #if defined(CONFIG_CMD_PING)
 		case PING:
 			PingStart();
@@ -1492,6 +1496,7 @@ NetReceive(volatile uchar * inpkt, int len)
 		}
 		break;
 
+#ifdef CONFIG_CMD_RARP
 	case PROT_RARP:
 		debug("Got RARP\n");
 		arp = (ARP_t *)ip;
@@ -1515,7 +1520,7 @@ NetReceive(volatile uchar * inpkt, int len)
 			(*packetHandler)(0,0,0,0);
 		}
 		break;
-
+#endif
 	case PROT_IP:
 		debug("Got IP\n");
 		/* Before we start poking the header, make sure it is there */
@@ -1729,10 +1734,12 @@ static int net_check_prereq (proto_t protocol)
 		}
 		/* Fall through */
 
-	case DHCP:
+#ifdef CONFIG_CMD_RARP
 	case RARP:
+#endif
 	case BOOTP:
 	case CDP:
+	case DHCP:
 		if (memcmp (NetOurEther, "\0\0\0\0\0\0", 6) == 0) {
 #ifdef CONFIG_NET_MULTI
 			extern int eth_get_dev_index (void);

From 042272a6f2fce3bf610a84cbfde3676b53c0d8dd Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 11 Oct 2010 11:41:47 +1000
Subject: [PATCH 13/15] net: Move Emaclite to NET_MULTI

Emaclite was using old net api that's why
this patch move emaclite to NET_MULTI api.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 drivers/net/xilinx_emaclite.c | 84 ++++++++++++++++++++---------------
 include/netdev.h              |  1 +
 2 files changed, 48 insertions(+), 37 deletions(-)

diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 74a201259b..76af939e98 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -26,6 +26,7 @@
 #include <common.h>
 #include <net.h>
 #include <config.h>
+#include <malloc.h>
 #include <asm/io.h>
 
 #undef DEBUG
@@ -63,26 +64,19 @@
 #define XEL_RSR_RECV_IE_MASK		0x00000008UL
 
 typedef struct {
-	unsigned int baseaddress;	/* Base address for device (IPIF) */
-	unsigned int nexttxbuffertouse;	/* Next TX buffer to write to */
-	unsigned int nextrxbuffertouse;	/* Next RX buffer to read from */
-	unsigned char deviceid;		/* Unique ID of device - for future */
+	u32 baseaddress;	/* Base address for device (IPIF) */
+	u32 nexttxbuffertouse;	/* Next TX buffer to write to */
+	u32 nextrxbuffertouse;	/* Next RX buffer to read from */
+	uchar deviceid;		/* Unique ID of device - for future */
 } xemaclite;
 
 static xemaclite emaclite;
 
 static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
 
-/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/
-#ifdef CONFIG_ENV_IS_NOWHERE
-static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
-#else
-static u8 emacaddr[ENET_ADDR_LENGTH];
-#endif
-
-void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount)
+static void xemaclite_alignedread (u32 *srcptr, void *destptr, u32 bytecount)
 {
-	unsigned int i;
+	u32 i;
 	u32 alignbuffer;
 	u32 *to32ptr;
 	u32 *from32ptr;
@@ -107,9 +101,9 @@ void xemaclite_alignedread (u32 * srcptr, void *destptr, unsigned bytecount)
 	}
 }
 
-void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount)
+static void xemaclite_alignedwrite (void *srcptr, u32 destptr, u32 bytecount)
 {
-	unsigned i;
+	u32 i;
 	u32 alignbuffer;
 	u32 *to32ptr = (u32 *) destptr;
 	u32 *from32ptr;
@@ -134,23 +128,16 @@ void xemaclite_alignedwrite (void *srcptr, u32 destptr, unsigned bytecount)
 	*to32ptr++ = alignbuffer;
 }
 
-void eth_halt (void)
+static void emaclite_halt(struct eth_device *dev)
 {
 	debug ("eth_halt\n");
 }
 
-int eth_init (bd_t * bis)
+static int emaclite_init(struct eth_device *dev, bd_t *bis)
 {
-	uchar enetaddr[6];
-
 	debug ("EmacLite Initialization Started\n");
 	memset (&emaclite, 0, sizeof (xemaclite));
-	emaclite.baseaddress = XILINX_EMACLITE_BASEADDR;
-
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		memcpy(enetaddr, emacaddr, ENET_ADDR_LENGTH);
-		eth_setenv_enetaddr("ethaddr", enetaddr);
-	}
+	emaclite.baseaddress = dev->iobase;
 
 /*
  * TX - TX_PING & TX_PONG initialization
@@ -158,7 +145,7 @@ int eth_init (bd_t * bis)
 	/* Restart PING TX */
 	out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET, 0);
 	/* Copy MAC address */
-	xemaclite_alignedwrite (enetaddr,
+	xemaclite_alignedwrite (dev->enetaddr,
 		emaclite.baseaddress, ENET_ADDR_LENGTH);
 	/* Set the length */
 	out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
@@ -171,7 +158,7 @@ int eth_init (bd_t * bis)
 #ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
 	/* The same operation with PONG TX */
 	out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
-	xemaclite_alignedwrite (enetaddr, emaclite.baseaddress +
+	xemaclite_alignedwrite (dev->enetaddr, emaclite.baseaddress +
 		XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
 	out_be32 (emaclite.baseaddress + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
 	out_be32 (emaclite.baseaddress + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
@@ -194,7 +181,7 @@ int eth_init (bd_t * bis)
 	return 0;
 }
 
-int xemaclite_txbufferavailable (xemaclite * instanceptr)
+static int xemaclite_txbufferavailable (xemaclite *instanceptr)
 {
 	u32 reg;
 	u32 txpingbusy;
@@ -216,12 +203,12 @@ int xemaclite_txbufferavailable (xemaclite * instanceptr)
 	return (!(txpingbusy && txpongbusy));
 }
 
-int eth_send (volatile void *ptr, int len) {
+static int emaclite_send (struct eth_device *dev, volatile void *ptr, int len)
+{
+	u32 reg;
+	u32 baseaddress;
 
-	unsigned int reg;
-	unsigned int baseaddress;
-
-	unsigned maxtry = 1000;
+	u32 maxtry = 1000;
 
 	if (len > ENET_MAX_MTU)
 		len = ENET_MAX_MTU;
@@ -293,11 +280,11 @@ int eth_send (volatile void *ptr, int len) {
 	return 0;
 }
 
-int eth_rx (void)
+static int emaclite_recv(struct eth_device *dev)
 {
-	unsigned int length;
-	unsigned int reg;
-	unsigned int baseaddress;
+	u32 length;
+	u32 reg;
+	u32 baseaddress;
 
 	baseaddress = emaclite.baseaddress + emaclite.nextrxbuffertouse;
 	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
@@ -353,3 +340,26 @@ int eth_rx (void)
 	return 1;
 
 }
+
+int xilinx_emaclite_initialize (bd_t *bis, int base_addr)
+{
+	struct eth_device *dev;
+
+	dev = malloc(sizeof(*dev));
+	if (dev == NULL)
+		hang();
+
+	memset(dev, 0, sizeof(*dev));
+	sprintf(dev->name, "Xilinx_Emaclite");
+
+	dev->iobase = base_addr;
+	dev->priv = 0;
+	dev->init = emaclite_init;
+	dev->halt = emaclite_halt;
+	dev->send = emaclite_send;
+	dev->recv = emaclite_recv;
+
+	eth_register(dev);
+
+	return 0;
+}
diff --git a/include/netdev.h b/include/netdev.h
index 64e5816013..7f66419350 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -89,6 +89,7 @@ int smc91111_initialize(u8 dev_num, int base_addr);
 int tsi108_eth_initialize(bd_t *bis);
 int uec_standard_init(bd_t *bis);
 int uli526x_initialize(bd_t *bis);
+int xilinx_emaclite_initialize (bd_t *bis, int base_addr);
 int sh_eth_initialize(bd_t *bis);
 int dm9000_initialize(bd_t *bis);
 

From 7b37a27e14975f32528552deed453b56a4149818 Mon Sep 17 00:00:00 2001
From: Ben Gardiner <bengardiner@nanometrics.ca>
Date: Thu, 23 Sep 2010 09:58:43 -0400
Subject: [PATCH 14/15] davinci_emac: davinci_eth_set_mac_addr to
 ->write_hwaddr

This patch proposes to migrate the davinci_emac driver to using the
eth_device->write_hwaddr function pointer as suggested by Ben Warren.

All the davinci boards had the behaviour, prior to this patch, of
sync'ing the environment variable enetaddr with the MAC address read
from non-volatile storage on boot -- when the two locations disagreed,
the environment variable value took precendence. This patch keeps the
same behaviour but lets eth_initialize take care of it.

This patch refactors davinci_emac setup in the boards so that the MAC
address is read from non-volatile storage into the environment variable
and then the environment variable value is use in eth_intialize. The
only exception is the direct call to davinci_eth_set_mac_addr made by
the da830evm board init which was changed into an assignment of the
enetaddr field.

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Tested-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 arch/arm/include/asm/arch-davinci/emac_defs.h |  1 -
 arch/arm/lib/board.c                          | 19 -----
 board/davinci/common/misc.c                   | 41 +++-------
 board/davinci/common/misc.h                   |  2 +-
 board/davinci/da8xxevm/da830evm.c             | 12 ++-
 board/davinci/dm365evm/dm365evm.c             |  2 +-
 board/davinci/dvevm/dvevm.c                   |  2 +-
 board/davinci/sffsdr/sffsdr.c                 |  2 +-
 board/davinci/sonata/sonata.c                 |  2 +-
 drivers/net/davinci_emac.c                    | 80 +++++++++----------
 10 files changed, 61 insertions(+), 102 deletions(-)

diff --git a/arch/arm/include/asm/arch-davinci/emac_defs.h b/arch/arm/include/asm/arch-davinci/emac_defs.h
index 35a1585d17..76493a138a 100644
--- a/arch/arm/include/asm/arch-davinci/emac_defs.h
+++ b/arch/arm/include/asm/arch-davinci/emac_defs.h
@@ -367,7 +367,6 @@ typedef struct  {
 
 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
-void davinci_eth_set_mac_addr(const u_int8_t *addr);
 
 typedef struct
 {
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 5f2dfd08ac..22bd2c9b0e 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -409,15 +409,6 @@ void start_armboot (void)
 	enable_interrupts ();
 
 	/* Perform network card initialisation if necessary */
-#ifdef CONFIG_DRIVER_TI_EMAC
-	/* XXX: this needs to be moved to board init */
-extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
-	if (getenv ("ethaddr")) {
-		uchar enetaddr[6];
-		eth_getenv_enetaddr("ethaddr", enetaddr);
-		davinci_eth_set_mac_addr(enetaddr);
-	}
-#endif
 
 #if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
 	/* XXX: this needs to be moved to board init */
@@ -821,16 +812,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	enable_interrupts ();
 
 	/* Perform network card initialisation if necessary */
-#ifdef CONFIG_DRIVER_TI_EMAC
-	/* XXX: this needs to be moved to board init */
-extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
-	if (getenv ("ethaddr")) {
-		uchar enetaddr[6];
-		eth_getenv_enetaddr("ethaddr", enetaddr);
-		davinci_eth_set_mac_addr(enetaddr);
-	}
-#endif
-
 #if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
 	/* XXX: this needs to be moved to board init */
 	if (getenv ("ethaddr")) {
diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c
index 86a875eeaa..b60a46e96d 100644
--- a/board/davinci/common/misc.c
+++ b/board/davinci/common/misc.c
@@ -85,45 +85,22 @@ err:
 	return 0;
 }
 
-/* If there is a MAC address in the environment, and if it is not identical to
- * the MAC address in the EEPROM, then a warning is printed and the MAC address
- * from the environment is used.
- *
+/*
  * If there is no MAC address in the environment, then it will be initialized
  * (silently) from the value in the EEPROM.
  */
-void dv_configure_mac_address(uint8_t *rom_enetaddr)
+void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
 {
-	int i;
-	u_int8_t env_enetaddr[6];
-	char *tmp = getenv("ethaddr");
-	char *end;
-
-	/* Read Ethernet MAC address from the U-Boot environment.
-	 * If it is not defined, env_enetaddr[] will be cleared. */
-	for (i = 0; i < 6; i++) {
-		env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
-		if (tmp)
-			tmp = (*end) ? end+1 : end;
-	}
-
-	/* Check if EEPROM and U-Boot environment MAC addresses match. */
-	if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 &&
-	    memcmp(env_enetaddr, rom_enetaddr, 6) != 0) {
-		printf("Warning: MAC addresses don't match:\n");
-		printf("  EEPROM MAC address: %pM\n", rom_enetaddr);
-		printf("     \"ethaddr\" value: %pM\n", env_enetaddr) ;
-		debug("### Using MAC address from environment\n");
-	}
-	if (!tmp) {
-		char ethaddr[20];
+	uint8_t env_enetaddr[6];
 
+	eth_getenv_enetaddr_by_index(0, env_enetaddr);
+	if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) {
 		/* There is no MAC address in the environment, so we initialize
 		 * it from the value in the EEPROM. */
-		sprintf(ethaddr, "%pM", rom_enetaddr) ;
-		debug("### Setting environment from EEPROM MAC address = \"%s\"\n",
-		      ethaddr);
-		setenv("ethaddr", ethaddr);
+		debug("### Setting environment from EEPROM MAC address = "
+			"\"%pM\"\n",
+			env_enetaddr);
+		eth_setenv_enetaddr("ethaddr", rom_enetaddr);
 	}
 }
 
diff --git a/board/davinci/common/misc.h b/board/davinci/common/misc.h
index 329c369763..a6ac3b9a56 100644
--- a/board/davinci/common/misc.h
+++ b/board/davinci/common/misc.h
@@ -46,7 +46,7 @@ struct pinmux_resource {
 			  }
 
 int dvevm_read_mac_address(uint8_t *buf);
-void dv_configure_mac_address(uint8_t *rom_enetaddr);
+void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
 int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
 int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
 				    int n_items);
diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c
index 6baa8603f1..8a9f9884d6 100644
--- a/board/davinci/da8xxevm/da830evm.c
+++ b/board/davinci/da8xxevm/da830evm.c
@@ -196,19 +196,17 @@ int board_eth_init(bd_t *bis)
 {
 	u_int8_t mac_addr[6];
 	u_int8_t switch_start_cmd[2] = { 0x01, 0x23 };
+	struct eth_device *dev;
 
 	/* Read Ethernet MAC address from EEPROM */
 	if (dvevm_read_mac_address(mac_addr))
 		/* set address env if not already set */
-		dv_configure_mac_address(mac_addr);
+		davinci_sync_env_enetaddr(mac_addr);
 
 	/* read the address back from env */
 	if (!eth_getenv_enetaddr("ethaddr", mac_addr))
 		return -1;
 
-	/* provide the resulting addr to the driver */
-	davinci_eth_set_mac_addr(mac_addr);
-
 	/* enable the Ethernet switch in the 3 port PHY */
 	if (i2c_write(PHY_SW_I2C_ADDR, 0, 0,
 			switch_start_cmd, sizeof(switch_start_cmd))) {
@@ -222,6 +220,12 @@ int board_eth_init(bd_t *bis)
 		return -1;
 	}
 
+	dev = eth_get_dev();
+
+	/* provide the resulting addr to the driver */
+	memcpy(dev->enetaddr, mac_addr, 6);
+	dev->write_hwaddr(dev);
+
 	return 0;
 }
 #endif /* CONFIG_DRIVER_TI_EMAC */
diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c
index 290eb99749..85dbe2a9c3 100644
--- a/board/davinci/dm365evm/dm365evm.c
+++ b/board/davinci/dm365evm/dm365evm.c
@@ -68,7 +68,7 @@ int board_eth_init(bd_t *bis)
 
 	/* Read Ethernet MAC address from EEPROM */
 	if (dvevm_read_mac_address(eeprom_enetaddr))
-		dv_configure_mac_address(eeprom_enetaddr);
+		davinci_sync_env_enetaddr(eeprom_enetaddr);
 
 	davinci_emac_initialize();
 
diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c
index 98937a9620..073c21a8cc 100644
--- a/board/davinci/dvevm/dvevm.c
+++ b/board/davinci/dvevm/dvevm.c
@@ -71,7 +71,7 @@ int misc_init_r(void)
 
 	/* Read Ethernet MAC address from EEPROM if available. */
 	if (dvevm_read_mac_address(eeprom_enetaddr))
-		dv_configure_mac_address(eeprom_enetaddr);
+		davinci_sync_env_enetaddr(eeprom_enetaddr);
 
 	i2c_read(0x39, 0x00, 1, &video_mode, 1);
 
diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c
index c24b9e188c..657cf2b0d9 100644
--- a/board/davinci/sffsdr/sffsdr.c
+++ b/board/davinci/sffsdr/sffsdr.c
@@ -141,7 +141,7 @@ int misc_init_r(void)
 
 	/* Read Ethernet MAC address from EEPROM if available. */
 	if (sffsdr_read_mac_address(eeprom_enetaddr))
-		dv_configure_mac_address(eeprom_enetaddr);
+		davinci_sync_env_enetaddr(eeprom_enetaddr);
 
 	return(0);
 }
diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c
index 817970aeaa..1dc42c4087 100644
--- a/board/davinci/sonata/sonata.c
+++ b/board/davinci/sonata/sonata.c
@@ -70,7 +70,7 @@ int misc_init_r(void)
 
 	/* Read Ethernet MAC address from EEPROM if available. */
 	if (dvevm_read_mac_address(eeprom_enetaddr))
-		dv_configure_mac_address(eeprom_enetaddr);
+		davinci_sync_env_enetaddr(eeprom_enetaddr);
 
 	return(0);
 }
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 41a9910919..e06896fea7 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -65,21 +65,6 @@ void eth_mdio_enable(void)
 	davinci_eth_mdio_enable();
 }
 
-static u_int8_t davinci_eth_mac_addr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
-
-/*
- * This function must be called before emac_open() if you want to override
- * the default mac address.
- */
-void davinci_eth_set_mac_addr(const u_int8_t *addr)
-{
-	int i;
-
-	for (i = 0; i < sizeof (davinci_eth_mac_addr); i++) {
-		davinci_eth_mac_addr[i] = addr[i];
-	}
-}
-
 /* EMAC Addresses */
 static volatile emac_regs	*adap_emac = (emac_regs *)EMAC_BASE_ADDR;
 static volatile ewrap_regs	*adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
@@ -100,6 +85,43 @@ static volatile u_int8_t	active_phy_addr = 0xff;
 
 phy_t				phy;
 
+static int davinci_eth_set_mac_addr(struct eth_device *dev)
+{
+	unsigned long		mac_hi;
+	unsigned long		mac_lo;
+
+	/*
+	 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
+	 * receive)
+	 *  Using channel 0 only - other channels are disabled
+	 *  */
+	writel(0, &adap_emac->MACINDEX);
+	mac_hi = (dev->enetaddr[3] << 24) |
+		 (dev->enetaddr[2] << 16) |
+		 (dev->enetaddr[1] << 8)  |
+		 (dev->enetaddr[0]);
+	mac_lo = (dev->enetaddr[5] << 8) |
+		 (dev->enetaddr[4]);
+
+	writel(mac_hi, &adap_emac->MACADDRHI);
+#if defined(DAVINCI_EMAC_VERSION2)
+	writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
+	       &adap_emac->MACADDRLO);
+#else
+	writel(mac_lo, &adap_emac->MACADDRLO);
+#endif
+
+	writel(0, &adap_emac->MACHASH1);
+	writel(0, &adap_emac->MACHASH2);
+
+	/* Set source MAC address - REQUIRED */
+	writel(mac_hi, &adap_emac->MACSRCADDRHI);
+	writel(mac_lo, &adap_emac->MACSRCADDRLO);
+
+
+	return 0;
+}
+
 static void davinci_eth_mdio_enable(void)
 {
 	u_int32_t	clkdiv;
@@ -286,8 +308,6 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
 	dv_reg_p		addr;
 	u_int32_t		clkdiv, cnt;
 	volatile emac_desc	*rx_desc;
-	unsigned long		mac_hi;
-	unsigned long		mac_lo;
 
 	debug_emac("+ emac_open\n");
 
@@ -311,30 +331,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
 	writel(1, &adap_emac->TXCONTROL);
 	writel(1, &adap_emac->RXCONTROL);
 
-	/* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast receive) */
-	/* Using channel 0 only - other channels are disabled */
-	writel(0, &adap_emac->MACINDEX);
-	mac_hi = (davinci_eth_mac_addr[3] << 24) |
-		 (davinci_eth_mac_addr[2] << 16) |
-		 (davinci_eth_mac_addr[1] << 8)  |
-		 (davinci_eth_mac_addr[0]);
-	mac_lo = (davinci_eth_mac_addr[5] << 8) |
-		 (davinci_eth_mac_addr[4]);
-
-	writel(mac_hi, &adap_emac->MACADDRHI);
-#if defined(DAVINCI_EMAC_VERSION2)
-	writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
-	       &adap_emac->MACADDRLO);
-#else
-	writel(mac_lo, &adap_emac->MACADDRLO);
-#endif
-
-	writel(0, &adap_emac->MACHASH1);
-	writel(0, &adap_emac->MACHASH2);
-
-	/* Set source MAC address - REQUIRED */
-	writel(mac_hi, &adap_emac->MACSRCADDRHI);
-	writel(mac_lo, &adap_emac->MACSRCADDRLO);
+	davinci_eth_set_mac_addr(dev);
 
 	/* Set DMA 8 TX / 8 RX Head pointers to 0 */
 	addr = &adap_emac->TX0HDP;
@@ -636,6 +633,7 @@ int davinci_emac_initialize(void)
 	dev->halt = davinci_eth_close;
 	dev->send = davinci_eth_send_packet;
 	dev->recv = davinci_eth_rcv_packet;
+	dev->write_hwaddr = davinci_eth_set_mac_addr;
 
 	eth_register(dev);
 

From 1ca6d0df3ecb028e989f3489b95d021f4497477b Mon Sep 17 00:00:00 2001
From: Thomas Chou <thomas@wytron.com.tw>
Date: Wed, 6 Oct 2010 09:16:10 +0800
Subject: [PATCH 15/15] smc91111: add write_hwaddr

Add smc_write_hwaddr() to set mac address.
Clear dev before use.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 drivers/net/smc91111.c | 40 ++++++++++++++++++++++++----------------
 1 file changed, 24 insertions(+), 16 deletions(-)

diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c
index 54a1bfb2a9..ba9c67e4c9 100644
--- a/drivers/net/smc91111.c
+++ b/drivers/net/smc91111.c
@@ -654,6 +654,28 @@ again:
 	return length;
 }
 
+static int smc_write_hwaddr(struct eth_device *dev)
+{
+	int i;
+
+	swap_to(ETHERNET);
+	SMC_SELECT_BANK (dev, 1);
+#ifdef USE_32_BIT
+	for (i = 0; i < 6; i += 2) {
+		word address;
+
+		address = dev->enetaddr[i + 1] << 8;
+		address |= dev->enetaddr[i];
+		SMC_outw(dev, address, (ADDR0_REG + i));
+	}
+#else
+	for (i = 0; i < 6; i++)
+		SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
+#endif
+	swap_to(FLASH);
+	return 0;
+}
+
 /*
  * Open and Initialize the board
  *
@@ -662,8 +684,6 @@ again:
  */
 static int smc_init(struct eth_device *dev, bd_t *bd)
 {
-	int i;
-
 	swap_to(ETHERNET);
 
 	PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
@@ -680,20 +700,6 @@ static int smc_init(struct eth_device *dev, bd_t *bd)
 	/* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
 /*	SMC_SELECT_BANK(dev, 0); */
 /*	SMC_outw(dev, 0, RPC_REG); */
-	SMC_SELECT_BANK (dev, 1);
-
-#ifdef USE_32_BIT
-	for (i = 0; i < 6; i += 2) {
-		word address;
-
-		address = dev->enetaddr[i + 1] << 8;
-		address |= dev->enetaddr[i];
-		SMC_outw(dev, address, (ADDR0_REG + i));
-	}
-#else
-	for (i = 0; i < 6; i++)
-		SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
-#endif
 
 	printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
 
@@ -1360,6 +1366,7 @@ int smc91111_initialize(u8 dev_num, int base_addr)
 		return 0;
 	}
 
+	memset(dev, 0, sizeof(*dev));
 	priv->dev_num = dev_num;
 	dev->priv = priv;
 	dev->iobase = base_addr;
@@ -1374,6 +1381,7 @@ int smc91111_initialize(u8 dev_num, int base_addr)
 	dev->halt = smc_halt;
 	dev->send = smc_send;
 	dev->recv = smc_rcv;
+	dev->write_hwaddr = smc_write_hwaddr;
 	sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
 
 	eth_register(dev);