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ARM: DRA7: Fixup DSP OPP_HIGH clock rate on DRA76P/DRA77P SoCs
The commit 1b42ab3eda
("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock
frequencies based on OPP") added the core logic to update the kernel
device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on
a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx
family of SoCs.
The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though
provide a higher performance and can run at a higher clock frequency
of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the
correct clock rates on these SoCs. Note that this higher clock rate is
not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or
AM574x SoCs) that follow the ABZ package.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
parent
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1 changed files with 12 additions and 0 deletions
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@ -180,6 +180,14 @@ u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
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{750000000, 750000000, 500000000}, /* OPP_HIGH */
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{750000000, 750000000, 500000000}, /* OPP_HIGH */
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};
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};
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/* DSP clock rates on DRA76x ACD-package based SoCs */
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u32 dra76_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
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{}, /* OPP_LOW */
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{600000000, 600000000, 400000000}, /* OPP_NOM */
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{700000000, 700000000, 466666667}, /* OPP_OD */
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{850000000, 850000000, 566666667}, /* OPP_HIGH */
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};
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/* IVA voltage domain */
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/* IVA voltage domain */
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u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = {
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u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = {
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{}, /* OPP_LOW */
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{}, /* OPP_LOW */
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@ -257,6 +265,10 @@ static void ft_opp_clock_fixups(void *fdt, bd_t *bd)
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/* fixup DSP clocks */
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/* fixup DSP clocks */
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clk_names = dra7_opp_dsp_clk_names;
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clk_names = dra7_opp_dsp_clk_names;
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clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
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clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
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/* adjust for higher OPP_HIGH clock rate on DRA76xP/DRA77xP SoCs */
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if (is_dra76x_acd())
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clk_rates = dra76_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
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ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM);
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ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM);
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if (ret) {
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if (ret) {
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printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",
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printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",
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