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powerpc: Add T4160QDS
T4160QDS shares the same platform as T4240QDS. T4160 is a low power version of T4240, with eight e6500 cores, two DDR3 controllers, and slightly different SerDes protocols. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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2 changed files with 17 additions and 1 deletions
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@ -896,6 +896,9 @@ stxssa_4M powerpc mpc85xx stxssa stx
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T4240QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240
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T4240QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240
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T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
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T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
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T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
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T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
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T4160QDS powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160
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T4160QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
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T4160QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
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B4860QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860
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B4860QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860
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B4860QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
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B4860QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
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B4860QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
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B4860QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
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@ -791,8 +791,21 @@ unsigned long get_board_ddr_clk(void);
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#define __USB_PHY_TYPE utmi
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#define __USB_PHY_TYPE utmi
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/*
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* T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be
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* 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to
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* cacheline interleaving. It can be cacheline, page, bank, superbank.
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* See doc/README.fsl-ddr for details.
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*/
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#ifdef CONFIG_PPC_T4240
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#define CTRL_INTLV_PREFERED 3way_4KB
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#else
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#define CTRL_INTLV_PREFERED cacheline
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:ctlr_intlv=3way_4KB," \
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"hwconfig=fsl_ddr:" \
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"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
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"bank_intlv=auto;" \
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"bank_intlv=auto;" \
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"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
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"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
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"netdev=eth0\0" \
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"netdev=eth0\0" \
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