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x86: Override calculate_relocation_address to use the e820 map
Because calculate_relocation_address now uses the e820 map, it will be able to avoid addresses over 32 bits and regions that are at high addresses but not big enough for U-Boot. It also means we can remove the hack which limitted U-Boot's idea of the size of memory to less than 4GB. Also take into account the space needed for the heap and stack, so we avoid picking a very small region those areas might overlap with something it shouldn't. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
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2 changed files with 56 additions and 7 deletions
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@ -27,8 +27,9 @@
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#include <asm/e820.h>
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#include <asm/u-boot-x86.h>
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#include <asm/global_data.h>
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#include <asm/arch-coreboot/sysinfo.h>
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#include <asm/arch-coreboot/tables.h>
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#include <asm/processor.h>
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#include <asm/arch/sysinfo.h>
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#include <asm/arch/tables.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -51,6 +52,58 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
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return num_entries;
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}
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/*
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* This function looks for the highest region of memory lower than 4GB which
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* has enough space for U-Boot where U-Boot is aligned on a page boundary. It
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* overrides the default implementation found elsewhere which simply picks the
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* end of ram, wherever that may be. The location of the stack, the relocation
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* address, and how far U-Boot is moved by relocation are set in the global
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* data structure.
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*/
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int calculate_relocation_address(void)
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{
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const uint64_t uboot_size = (uintptr_t)&__bss_end -
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(uintptr_t)&__text_start;
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const uint64_t total_size = uboot_size + CONFIG_SYS_MALLOC_LEN +
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CONFIG_SYS_STACK_SIZE;
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uintptr_t dest_addr = 0;
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int i;
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for (i = 0; i < lib_sysinfo.n_memranges; i++) {
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struct memrange *memrange = &lib_sysinfo.memrange[i];
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/* Force U-Boot to relocate to a page aligned address. */
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uint64_t start = roundup(memrange->base, 1 << 12);
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uint64_t end = memrange->base + memrange->size;
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/* Ignore non-memory regions. */
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if (memrange->type != CB_MEM_RAM)
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continue;
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/* Filter memory over 4GB. */
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if (end > 0xffffffffULL)
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end = 0x100000000ULL;
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/* Skip this region if it's too small. */
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if (end - start < total_size)
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continue;
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/* Use this address if it's the largest so far. */
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if (end - uboot_size > dest_addr)
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dest_addr = end;
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}
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/* If no suitable area was found, return an error. */
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if (!dest_addr)
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return 1;
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dest_addr -= uboot_size;
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dest_addr &= ~((1 << 12) - 1);
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gd->relocaddr = dest_addr;
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gd->reloc_off = dest_addr - (uintptr_t)&__text_start;
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gd->start_addr_sp = dest_addr - CONFIG_SYS_MALLOC_LEN;
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return 0;
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}
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int dram_init_f(void)
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{
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int i;
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@ -60,10 +113,6 @@ int dram_init_f(void)
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struct memrange *memrange = &lib_sysinfo.memrange[i];
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unsigned long long end = memrange->base + memrange->size;
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/* Ignore memory over 4GB, we can't use it. */
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if (memrange->base > 0xffffffff)
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continue;
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if (memrange->type == CB_MEM_RAM && end > ram_size)
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ram_size = end;
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}
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@ -1100,7 +1100,7 @@ gr_cpci_ax2000 sparc leon3 - gaisler
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gr_ep2s60 sparc leon3 - gaisler
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grsim sparc leon3 - gaisler
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gr_xc3s_1500 sparc leon3 - gaisler
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coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0xFC0000
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coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0x01110000
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eNET x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x38040000
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eNET_SRAM x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x19000000
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# Target ARCH CPU Board name Vendor SoC Options
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