mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 21:21:37 +00:00
spl: add NAND Library to new SPL
Adds NAND library to SPL. Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
parent
bb085b87e5
commit
12c2f1ee3c
7 changed files with 288 additions and 5 deletions
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@ -60,3 +60,4 @@ CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o)
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CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o)
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CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o)
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CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o)
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CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
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@ -26,12 +26,18 @@ include $(TOPDIR)/config.mk
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LIB := $(obj)libnand.o
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ifdef CONFIG_CMD_NAND
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_SPL_NAND_SIMPLE
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COBJS-y += nand_spl_simple.o
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endif
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else
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COBJS-y += nand.o
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COBJS-y += nand_base.o
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COBJS-y += nand_bbt.o
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COBJS-y += nand_ecc.o
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COBJS-y += nand_ids.o
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COBJS-y += nand_util.o
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endif
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COBJS-y += nand_ecc.o
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COBJS-y += nand_base.o
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COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o
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COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
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@ -213,7 +213,7 @@ static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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*
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* Default read function for 8bit buswith
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*/
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static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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int i;
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struct nand_chip *chip = mtd->priv;
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@ -269,7 +269,7 @@ static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
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*
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* Default read function for 16bit buswith
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*/
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static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
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void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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int i;
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struct nand_chip *chip = mtd->priv;
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245
drivers/mtd/nand/nand_spl_simple.c
Normal file
245
drivers/mtd/nand/nand_spl_simple.c
Normal file
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@ -0,0 +1,245 @@
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/*
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* (C) Copyright 2006-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <nand.h>
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#include <asm/io.h>
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static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
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static nand_info_t mtd;
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static struct nand_chip nand_chip;
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#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
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/*
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* NAND command for small page NAND devices (512)
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*/
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static int nand_command(int block, int page, uint32_t offs,
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u8 cmd)
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{
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struct nand_chip *this = mtd.priv;
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int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
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while (!this->dev_ready(&mtd))
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;
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/* Begin command latch cycle */
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this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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/* Set ALE and clear CLE to start address cycle */
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/* Column address */
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this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
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this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
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this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
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NAND_CTRL_ALE); /* A[24:17] */
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#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
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/* One more address cycle for devices > 32MiB */
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this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
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NAND_CTRL_ALE); /* A[28:25] */
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#endif
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/* Latch in address */
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this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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/*
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* Wait a while for the data to be ready
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*/
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while (!this->dev_ready(&mtd))
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;
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return 0;
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}
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#else
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/*
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* NAND command for large page NAND devices (2k)
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*/
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static int nand_command(int block, int page, uint32_t offs,
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u8 cmd)
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{
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struct nand_chip *this = mtd.priv;
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int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
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void (*hwctrl)(struct mtd_info *mtd, int cmd,
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unsigned int ctrl) = this->cmd_ctrl;
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while (!this->dev_ready(&mtd))
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;
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/* Emulate NAND_CMD_READOOB */
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if (cmd == NAND_CMD_READOOB) {
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offs += CONFIG_SYS_NAND_PAGE_SIZE;
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cmd = NAND_CMD_READ0;
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}
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/* Shift the offset from byte addressing to word addressing. */
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if (this->options & NAND_BUSWIDTH_16)
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offs >>= 1;
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/* Begin command latch cycle */
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hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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/* Set ALE and clear CLE to start address cycle */
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/* Column address */
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hwctrl(&mtd, offs & 0xff,
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NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
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hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
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/* Row address */
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hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
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hwctrl(&mtd, ((page_addr >> 8) & 0xff),
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NAND_CTRL_ALE); /* A[27:20] */
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#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
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/* One more address cycle for devices > 128MiB */
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hwctrl(&mtd, (page_addr >> 16) & 0x0f,
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NAND_CTRL_ALE); /* A[31:28] */
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#endif
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/* Latch in address */
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hwctrl(&mtd, NAND_CMD_READSTART,
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NAND_CTRL_CLE | NAND_CTRL_CHANGE);
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hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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/*
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* Wait a while for the data to be ready
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*/
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while (!this->dev_ready(&mtd))
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;
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return 0;
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}
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#endif
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static int nand_is_bad_block(int block)
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{
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struct nand_chip *this = mtd.priv;
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nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
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NAND_CMD_READOOB);
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/*
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* Read one byte (or two if it's a 16 bit chip).
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*/
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if (this->options & NAND_BUSWIDTH_16) {
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if (readw(this->IO_ADDR_R) != 0xffff)
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return 1;
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} else {
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if (readb(this->IO_ADDR_R) != 0xff)
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return 1;
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}
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return 0;
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}
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static int nand_read_page(int block, int page, void *dst)
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{
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struct nand_chip *this = mtd.priv;
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u_char *ecc_calc;
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u_char *ecc_code;
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u_char *oob_data;
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int i;
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int eccsize = CONFIG_SYS_NAND_ECCSIZE;
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int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
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int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
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uint8_t *p = dst;
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int stat;
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nand_command(block, page, 0, NAND_CMD_READ0);
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/* No malloc available for now, just use some temporary locations
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* in SDRAM
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*/
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ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
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ecc_code = ecc_calc + 0x100;
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oob_data = ecc_calc + 0x200;
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for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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this->ecc.hwctl(&mtd, NAND_ECC_READ);
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this->read_buf(&mtd, p, eccsize);
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this->ecc.calculate(&mtd, p, &ecc_calc[i]);
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}
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this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
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/* Pick the ECC bytes out of the oob data */
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for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
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ecc_code[i] = oob_data[nand_ecc_pos[i]];
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eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
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p = dst;
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for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
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/* No chance to do something with the possible error message
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* from correct_data(). We just hope that all possible errors
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* are corrected by this routine.
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*/
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stat = this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
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}
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return 0;
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}
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int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
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{
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unsigned int block, lastblock;
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unsigned int page;
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/*
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* offs has to be aligned to a page address!
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*/
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block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
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lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
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page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
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while (block <= lastblock) {
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if (!nand_is_bad_block(block)) {
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/*
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* Skip bad blocks
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*/
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while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
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nand_read_page(block, page, dst);
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dst += CONFIG_SYS_NAND_PAGE_SIZE;
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page++;
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}
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page = 0;
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} else {
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lastblock++;
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}
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block++;
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}
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return 0;
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}
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/* nand_init() - initialize data to make nand usable by SPL */
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void nand_init(void)
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{
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/*
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* Init board specific nand support
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*/
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mtd.priv = &nand_chip;
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nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
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(void __iomem *)CONFIG_SYS_NAND_BASE;
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nand_chip.options = 0;
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board_nand_init(&nand_chip);
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if (nand_chip.select_chip)
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nand_chip.select_chip(&mtd, 0);
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}
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/* Unselect after operation */
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void nand_deselect(void)
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{
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if (nand_chip.select_chip)
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nand_chip.select_chip(&mtd, -1);
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}
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@ -61,6 +61,14 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
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writeb(cmd, this->IO_ADDR_W);
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}
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#ifdef CONFIG_SPL_BUILD
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/* Check wait pin as dev ready indicator */
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int omap_spl_dev_ready(struct mtd_info *mtd)
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{
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return gpmc_cfg->status & (1 << 8);
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}
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#endif
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/*
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* omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
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* GPMC controller
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@ -224,6 +232,7 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
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}
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}
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#ifndef CONFIG_SPL_BUILD
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/*
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* omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
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* The default is to come up on s/w ecc
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@ -280,6 +289,7 @@ void omap_nand_switch_ecc(int32_t hardware)
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nand->options &= ~NAND_OWN_BUFFERS;
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}
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#endif /* CONFIG_SPL_BUILD */
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/*
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* Board-specific NAND initialization. The following members of the
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nand->chip_delay = 100;
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/* Default ECC mode */
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#ifndef CONFIG_SPL_BUILD
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nand->ecc.mode = NAND_ECC_SOFT;
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#else
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.layout = &hw_nand_oob;
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nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
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nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
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nand->ecc.hwctl = omap_enable_hwecc;
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nand->ecc.correct = omap_correct_data;
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nand->ecc.calculate = omap_calculate_ecc;
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omap_hwecc_init(nand);
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if (nand->options & NAND_BUSWIDTH_16)
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nand->read_buf = nand_read_buf16;
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else
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nand->read_buf = nand_read_buf;
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nand->dev_ready = omap_spl_dev_ready;
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#endif
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return 0;
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}
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@ -132,9 +132,12 @@ int nand_lock( nand_info_t *meminfo, int tight );
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int nand_unlock( nand_info_t *meminfo, ulong start, ulong length );
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int nand_get_lock_status(nand_info_t *meminfo, loff_t offset);
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void nand_spl_load_image(loff_t offs, unsigned int size, uchar *dst);
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int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst);
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void nand_deselect(void);
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void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
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void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
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#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
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void board_nand_select_device(struct nand_chip *nand, int chip);
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#endif
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@ -46,6 +46,7 @@ LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o
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LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o
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LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o
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LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
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LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
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ifeq ($(SOC),omap3)
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LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
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