mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-17 12:41:32 +00:00
* Patch by Pierre Aubert, 26 Feb 2004
add IDE support for MPC5200 * Patch by Masami Komiya, 26 Feb 2004: add autoload via NFS * Patch by Stephen Williams Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses elsewhere in the source.
This commit is contained in:
parent
11dadd547c
commit
132ba5fdc5
12 changed files with 211 additions and 22 deletions
12
CHANGELOG
12
CHANGELOG
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@ -2,6 +2,16 @@
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Changes for U-Boot 1.0.2:
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======================================================================
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* Patch by Pierre Aubert, 26 Feb 2004
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add IDE support for MPC5200
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* Patch by Masami Komiya, 26 Feb 2004:
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add autoload via NFS
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* Patch by Stephen Williams
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Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses
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elsewhere in the source.
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* Patch by Steven Scholz, 25 Feb 2004:
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- Timeouts in FPGA code should be based on CFG_HZ
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- Minor cleanup in code for Altera FPGA ACEX1K
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@ -15,7 +25,7 @@ Changes for U-Boot 1.0.2:
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* Patch by Markus Pietrek, 24 Feb 2004:
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NS9750 DevBoard added
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* Patch by Pierre AUBERT, 24 Feb 2004
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* Patch by Pierre Aubert, 24 Feb 2004
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add USB support for MPC5200
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* Patch by Steven Scholz, 24 Feb 2004:
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@ -23,7 +23,7 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*
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***********************************************************************/
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#ifdef CONFIG_STATUS_LED
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@ -37,6 +37,9 @@
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#ifdef CONFIG_8xx
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# include <mpc8xx.h>
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#endif
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#ifdef CONFIG_MPC5xxx
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#include <mpc5xxx.h>
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#endif
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#include <ide.h>
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#include <ata.h>
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#ifdef CONFIG_STATUS_LED
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@ -27,8 +27,8 @@ LIB = lib$(CPU).a
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START = start.o
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ASOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
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OBJS = i2c.o traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
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loadtask.o fec.o pci_mpc5200.o usb_ohci.o
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OBJS = i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \
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loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o
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all: .depend $(START) $(ASOBJS) $(LIB)
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93
cpu/mpc5xxx/ide.c
Normal file
93
cpu/mpc5xxx/ide.c
Normal file
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@ -0,0 +1,93 @@
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/*
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* (C) Copyright 2004
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* Pierre AUBERT, Staubli Faverges, <p.aubert@staubli.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Init is derived from Linux code.
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*/
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#include <common.h>
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#ifdef CFG_CMD_IDE
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#include <mpc5xxx.h>
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#define CALC_TIMING(t) (t + period - 1) / period
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#define GPIO_PSC1_4 0x01000000ul
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int ide_preinit (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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long period, t0, t1, t2_8, t2_16, t4, ta;
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vu_long reg;
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struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA;
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reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG;
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reg = (reg & ~0x03000000ul) | 0x01000000ul;
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*(vu_long *) MPC5XXX_GPS_PORT_CONFIG = reg;
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/* All sample codes do that... */
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*(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0;
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/* Configure and reset host */
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*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY |
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MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
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udelay (10);
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*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;
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/* Disable prefetch on Commbus */
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psdma->PtdCntrl |= 1;
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/* Init timings : we use PIO mode 0 timings */
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period = 1000000000 / gd->ipb_clk; /* period in ns */
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t0 = CALC_TIMING (600);
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t2_8 = CALC_TIMING (290);
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t2_16 = CALC_TIMING (165);
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reg = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8);
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*(vu_long *) MPC5XXX_ATA_PIO1 = reg;
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t4 = CALC_TIMING (30);
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t1 = CALC_TIMING (70);
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ta = CALC_TIMING (35);
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reg = (t4 << 24) | (t1 << 16) | (ta << 8);
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*(vu_long *) MPC5XXX_ATA_PIO2 = reg;
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#if defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET)
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/* Configure PSC1_4 as GPIO output for ATA reset */
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*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
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#endif /* defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET) */
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return (0);
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}
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#if defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET)
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void ide_set_reset (int idereset)
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{
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if (idereset) {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
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} else {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
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}
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}
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#endif /* defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET) */
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#endif /* CFG_CMD_IDE */
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@ -81,6 +81,10 @@
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#endif
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/* USB */
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#if 1
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#define CONFIG_USB_OHCI
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/*
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* Supported commands
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*/
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
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CFG_CMD_I2C | CFG_CMD_EEPROM | \
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_EEPROM | \
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CFG_CMD_FAT | \
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CFG_CMD_I2C | \
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CFG_CMD_IDE | \
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ADD_PCI_CMD | \
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ADD_USB_CMD)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#define CFG_RESET_ADDRESS 0xff000000
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff Supports IDE harddisk
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#define CONFIG_IDE_RESET /* reset for ide supported */
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#define CONFIG_IDE_PREINIT
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
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/* Offset for data I/O */
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#define CFG_ATA_DATA_OFFSET (0x0060)
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/* Offset for normal register accesses */
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#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET (0x005c)
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/* Interval between registers */
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#define CFG_ATA_STRIDE 4
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#endif /* __CONFIG_H */
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#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
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#endif
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/* older kernels need clock in MHz newer in Hz */
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/* #define CONFIG_CLOCKS_IN_MHZ 1 *//* clocks passsed to Linux in MHz */
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/* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */
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#undef CONFIG_CLOCKS_IN_MHZ
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#define CONFIG_BOOTDELAY 10
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/*#define CONFIG_DRAM_SPEED 66 *//* MHz */
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/*#define CONFIG_DRAM_SPEED 66 */ /* MHz */
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_FLASH | \
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
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#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */
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/*#define CONFIG_133MHZ_DRAM 1 *//* For 133 MHZ DRAM only !!!!!!!!!!! */
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/*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */
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#if defined (CONFIG_MPC8245)
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/* Bit-field values for PMCR2. */
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#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
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#define MPC5XXX_GPT (CFG_MBAR + 0x0600)
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#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
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#define MPC5XXX_WU_GPIO (CFG_MBAR + 0x0c00)
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#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
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#define MPC5XXX_USB (CFG_MBAR + 0x1000)
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#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
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#endif
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#define MPC5XXX_FEC (CFG_MBAR + 0x3000)
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#define MPC5XXX_ATA (CFG_MBAR + 0x3A00)
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#define MPC5XXX_I2C1 (CFG_MBAR + 0x3D00)
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#define MPC5XXX_I2C2 (CFG_MBAR + 0x3D40)
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/* GPIO registers */
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#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
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/* WakeUp GPIO registers */
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#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000)
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#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004)
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#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008)
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#define MPC5XXX_WU_GPIO_DATA (MPC5XXX_WU_GPIO + 0x000c)
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/* PCI registers */
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#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
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#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
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#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
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#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
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/* ATA registers */
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#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)
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#define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008)
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#define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C)
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#define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C)
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/* I2Cn control register bits */
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#define I2C_EN 0x80
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#define I2C_IEN 0x40
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#define PSC_MODE_ONE_STOP 0x07
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#define PSC_MODE_TWO_STOP 0x0f
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/* ATA config fields */
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#define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine
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reset */
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#define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
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#define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt
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in PIO */
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#define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports
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IORDY protocol */
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#ifndef __ASSEMBLY__
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struct mpc5xxx_psc {
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volatile u8 mode; /* PSC + 0x00 */
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/* Must happen after interrupts are initialized since
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* an irq handler gets installed
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*/
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#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
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#if CONFIG_SERIAL_SOFTWARE_FIFO
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serial_buffered_init();
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#endif
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@ -577,7 +577,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
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*/
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timer_init();
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#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
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#if CONFIG_SERIAL_SOFTWARE_FIFO
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serial_buffered_init();
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#endif
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@ -874,7 +874,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
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/* Must happen after interrupts are initialized since
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* an irq handler gets installed
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*/
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#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
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#if CONFIG_SERIAL_SOFTWARE_FIFO
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serial_buffered_init();
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#endif
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40
net/bootp.c
40
net/bootp.c
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@ -331,13 +331,21 @@ BootpHandler(uchar * pkt, unsigned dest, unsigned src, unsigned len)
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debug ("Got good BOOTP\n");
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if (((s = getenv("autoload")) != NULL) && (*s == 'n')) {
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/*
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* Just use BOOTP to configure system;
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* Do not use TFTP to load the bootfile.
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*/
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NetState = NETLOOP_SUCCESS;
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return;
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if ((s = getenv("autoload")) != NULL) {
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if (*s == 'n') {
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/*
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* Just use BOOTP to configure system;
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* Do not use TFTP to load the bootfile.
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*/
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NetState = NETLOOP_SUCCESS;
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return;
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} else if (strcmp(s, "NFS") == 0) {
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/*
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* Use NFS to load the bootfile.
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*/
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NfsStart();
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return;
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}
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}
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TftpStart();
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printf("\n");
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/* Obey the 'autoload' setting */
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if (((s = getenv("autoload")) != NULL) && (*s == 'n')) {
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NetState = NETLOOP_SUCCESS;
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return;
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if ((s = getenv("autoload")) != NULL) {
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if (*s == 'n') {
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/*
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* Just use BOOTP to configure system;
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* Do not use TFTP to load the bootfile.
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*/
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NetState = NETLOOP_SUCCESS;
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return;
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} else if (strcmp(s, "NFS") == 0) {
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/*
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* Use NFS to load the bootfile.
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*/
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NfsStart();
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return;
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}
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}
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TftpStart();
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return;
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Loading…
Add table
Reference in a new issue