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mmc: fsl_esdhc_imx: fix the mask for tuning start point
According the RM, the bit[6~0] of register ESDHC_TUNING_CTRL is
TUNING_START_TAP, bit[7] of this register is to disable the command
CRC check for standard tuning. So fix it here.
Fixes: fa33d20749
("mmc: split fsl_esdhc driver for i.MX")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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1 changed files with 1 additions and 1 deletions
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@ -203,7 +203,7 @@
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#define ESDHC_STD_TUNING_EN BIT(24)
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/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
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#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
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#define ESDHC_TUNING_START_TAP_MASK 0xff
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#define ESDHC_TUNING_START_TAP_MASK 0x7f
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#define ESDHC_TUNING_STEP_MASK 0x00070000
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#define ESDHC_TUNING_STEP_SHIFT 16
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