mirror of
https://github.com/Fishwaldo/u-boot.git
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x86: ivybridge: Convert to use the common SDRAM code
Adjust the existing implementation to use the new common SDRAM init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
65dd1507e3
commit
147ba41d29
1 changed files with 83 additions and 311 deletions
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@ -25,6 +25,7 @@
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#include <asm/global_data.h>
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#include <asm/intel_regs.h>
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#include <asm/mrccache.h>
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#include <asm/mrc_common.h>
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#include <asm/mtrr.h>
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#include <asm/pci.h>
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#include <asm/report_platform.h>
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@ -40,57 +41,14 @@ DECLARE_GLOBAL_DATA_PTR;
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#define CMOS_OFFSET_MRC_SEED_S3 156
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#define CMOS_OFFSET_MRC_SEED_CHK 160
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/*
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* This function looks for the highest region of memory lower than 4GB which
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* has enough space for U-Boot where U-Boot is aligned on a page boundary.
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* It overrides the default implementation found elsewhere which simply
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* picks the end of ram, wherever that may be. The location of the stack,
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* the relocation address, and how far U-Boot is moved by relocation are
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* set in the global data structure.
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*/
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ulong board_get_usable_ram_top(ulong total_size)
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{
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struct memory_info *info = &gd->arch.meminfo;
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uintptr_t dest_addr = 0;
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struct memory_area *largest = NULL;
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int i;
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/* Find largest area of memory below 4GB */
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for (i = 0; i < info->num_areas; i++) {
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struct memory_area *area = &info->area[i];
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if (area->start >= 1ULL << 32)
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continue;
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if (!largest || area->size > largest->size)
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largest = area;
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}
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/* If no suitable area was found, return an error. */
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assert(largest);
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if (!largest || largest->size < (2 << 20))
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panic("No available memory found for relocation");
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dest_addr = largest->start + largest->size;
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return (ulong)dest_addr;
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return mrc_common_board_get_usable_ram_top(total_size);
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}
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void dram_init_banksize(void)
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{
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struct memory_info *info = &gd->arch.meminfo;
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int num_banks;
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int i;
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for (i = 0, num_banks = 0; i < info->num_areas; i++) {
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struct memory_area *area = &info->area[i];
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if (area->start >= 1ULL << 32)
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continue;
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gd->bd->bi_dram[num_banks].start = area->start;
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gd->bd->bi_dram[num_banks].size = area->size;
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num_banks++;
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}
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mrc_common_dram_init_banksize();
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}
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static int read_seed_from_cmos(struct pei_data *pei_data)
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@ -217,164 +175,10 @@ int misc_init_r(void)
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return 0;
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}
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static const char *const ecc_decoder[] = {
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"inactive",
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"active on IO",
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"disabled on IO",
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"active"
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};
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/*
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* Dump in the log memory controller configuration as read from the memory
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* controller registers.
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*/
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static void report_memory_config(void)
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static void post_system_agent_init(struct udevice *dev, struct udevice *me_dev,
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struct pei_data *pei_data)
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{
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u32 addr_decoder_common, addr_decode_ch[2];
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int i;
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addr_decoder_common = readl(MCHBAR_REG(0x5000));
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addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
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addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
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debug("memcfg DDR3 clock %d MHz\n",
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(readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
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debug("memcfg channel assignment: A: %d, B % d, C % d\n",
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addr_decoder_common & 3,
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(addr_decoder_common >> 2) & 3,
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(addr_decoder_common >> 4) & 3);
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for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
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u32 ch_conf = addr_decode_ch[i];
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debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
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debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
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debug(" enhanced interleave mode %s\n",
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((ch_conf >> 22) & 1) ? "on" : "off");
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debug(" rank interleave %s\n",
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((ch_conf >> 21) & 1) ? "on" : "off");
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debug(" DIMMA %d MB width x%d %s rank%s\n",
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((ch_conf >> 0) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? 16 : 8,
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((ch_conf >> 17) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? "" : ", selected");
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debug(" DIMMB %d MB width x%d %s rank%s\n",
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((ch_conf >> 8) & 0xff) * 256,
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((ch_conf >> 20) & 1) ? 16 : 8,
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((ch_conf >> 18) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? ", selected" : "");
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}
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}
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static void post_system_agent_init(struct pei_data *pei_data)
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{
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/* If PCIe init is skipped, set the PEG clock gating */
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if (!pei_data->pcie_init)
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setbits_le32(MCHBAR_REG(0x7010), 1);
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}
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static asmlinkage void console_tx_byte(unsigned char byte)
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{
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#ifdef DEBUG
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putc(byte);
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#endif
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}
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static int recovery_mode_enabled(void)
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{
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return false;
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}
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/**
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* Find the PEI executable in the ROM and execute it.
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*
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* @dev: Northbridge device
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* @pei_data: configuration data for UEFI PEI reference code
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*/
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int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
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struct pei_data *pei_data)
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{
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unsigned version;
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const char *data;
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uint16_t done;
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int ret;
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report_platform_info(dev);
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/* Wait for ME to be ready */
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ret = intel_early_me_init(me_dev);
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if (ret)
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return ret;
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ret = intel_early_me_uma_size(me_dev);
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if (ret < 0)
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return ret;
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debug("Starting UEFI PEI System Agent\n");
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/*
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* Do not pass MRC data in for recovery mode boot,
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* Always pass it in for S3 resume.
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*/
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if (!recovery_mode_enabled() ||
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pei_data->boot_mode == PEI_BOOT_RESUME) {
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ret = prepare_mrc_cache(pei_data);
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if (ret)
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debug("prepare_mrc_cache failed: %d\n", ret);
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}
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/* If MRC data is not found we cannot continue S3 resume. */
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if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
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debug("Giving up in sdram_initialize: No MRC data\n");
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reset_cpu(0);
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}
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/* Pass console handler in pei_data */
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pei_data->tx_byte = console_tx_byte;
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debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
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data = (char *)CONFIG_X86_MRC_ADDR;
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if (data) {
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int rv;
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int (*func)(struct pei_data *);
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ulong start;
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debug("Calling MRC at %p\n", data);
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post_code(POST_PRE_MRC);
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start = get_timer(0);
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func = (int (*)(struct pei_data *))data;
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rv = func(pei_data);
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post_code(POST_MRC);
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if (rv) {
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switch (rv) {
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case -1:
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printf("PEI version mismatch.\n");
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break;
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case -2:
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printf("Invalid memory frequency.\n");
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break;
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default:
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printf("MRC returned %x.\n", rv);
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}
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printf("Nonzero MRC return value.\n");
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return -EFAULT;
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}
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debug("MRC execution time %lu ms\n", get_timer(start));
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} else {
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printf("UEFI PEI System Agent not found.\n");
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return -ENOSYS;
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}
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#if CONFIG_USBDEBUG
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/* mrc.bin reconfigures USB, so reinit it to have debug */
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early_usbdebug_init();
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#endif
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version = readl(MCHBAR_REG(0x5034));
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debug("System Agent Version %d.%d.%d Build %d\n",
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version >> 24 , (version >> 16) & 0xff,
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(version >> 8) & 0xff, version & 0xff);
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debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
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pei_data->mrc_output);
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/*
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* Send ME init done for SandyBridge here. This is done inside the
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@ -387,23 +191,14 @@ int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
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else
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intel_me_status(me_dev);
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post_system_agent_init(pei_data);
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report_memory_config();
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/* If PCIe init is skipped, set the PEG clock gating */
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if (!pei_data->pcie_init)
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setbits_le32(MCHBAR_REG(0x7010), 1);
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}
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/* S3 resume: don't save scrambler seed or MRC data */
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if (pei_data->boot_mode != PEI_BOOT_RESUME) {
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/*
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* This will be copied to SDRAM in reserve_arch(), then written
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* to SPI flash in mrccache_save()
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*/
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gd->arch.mrc_output = (char *)pei_data->mrc_output;
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gd->arch.mrc_output_len = pei_data->mrc_output_len;
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ret = write_seeds_to_cmos(pei_data);
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if (ret)
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debug("Failed to write seeds to CMOS: %d\n", ret);
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}
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return 0;
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static int recovery_mode_enabled(void)
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{
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return false;
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}
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int reserve_arch(void)
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@ -411,87 +206,16 @@ int reserve_arch(void)
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return mrccache_reserve();
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}
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static int copy_spd(struct pei_data *peid)
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static int copy_spd(struct udevice *dev, struct pei_data *peid)
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{
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const int gpio_vector[] = {41, 42, 43, 10, -1};
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int spd_index;
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const void *blob = gd->fdt_blob;
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int node, spd_node;
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int ret, i;
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const void *data;
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int ret;
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for (i = 0; ; i++) {
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if (gpio_vector[i] == -1)
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break;
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ret = gpio_requestf(gpio_vector[i], "spd_id%d", i);
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if (ret) {
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debug("%s: Could not request gpio %d\n", __func__,
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gpio_vector[i]);
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return ret;
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}
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}
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spd_index = gpio_get_values_as_int(gpio_vector);
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debug("spd index %d\n", spd_index);
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node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD);
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if (node < 0) {
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printf("SPD data not found.\n");
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return -ENOENT;
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}
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ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data);
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if (ret)
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return ret;
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for (spd_node = fdt_first_subnode(blob, node);
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spd_node > 0;
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spd_node = fdt_next_subnode(blob, spd_node)) {
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const char *data;
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int len;
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if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
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continue;
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data = fdt_getprop(blob, spd_node, "data", &len);
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if (len < sizeof(peid->spd_data[0])) {
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printf("Missing SPD data\n");
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return -EINVAL;
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}
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debug("Using SDRAM SPD data for '%s'\n",
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fdt_get_name(blob, spd_node, NULL));
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memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
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break;
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}
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if (spd_node < 0) {
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printf("No SPD data found for index %d\n", spd_index);
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return -ENOENT;
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}
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return 0;
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}
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/**
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* add_memory_area() - Add a new usable memory area to our list
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*
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* Note: @start and @end must not span the first 4GB boundary
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*
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* @info: Place to store memory info
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* @start: Start of this memory area
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* @end: End of this memory area + 1
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*/
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static int add_memory_area(struct memory_info *info,
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uint64_t start, uint64_t end)
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{
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struct memory_area *ptr;
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if (info->num_areas == CONFIG_NR_DRAM_BANKS)
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return -ENOSPC;
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ptr = &info->area[info->num_areas];
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ptr->start = start;
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ptr->size = end - start;
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info->total_memory += ptr->size;
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if (ptr->start < (1ULL << 32))
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info->total_32bit_memory += ptr->size;
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debug("%d: memory %llx size %llx, total now %llx / %llx\n",
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info->num_areas, ptr->start, ptr->size,
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info->total_32bit_memory, info->total_memory);
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info->num_areas++;
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memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
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return 0;
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}
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@ -610,10 +334,10 @@ static int sdram_find(struct udevice *dev)
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debug("Available memory below 4GB: %lluM\n", tomk >> 10);
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/* Report the memory regions */
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add_memory_area(info, 1 << 20, 2 << 28);
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add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
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add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
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add_memory_area(info, 1ULL << 32, touud);
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mrc_add_memory_area(info, 1 << 20, 2 << 28);
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mrc_add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
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mrc_add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
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mrc_add_memory_area(info, 1ULL << 32, touud);
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/* Add MTRRs for memory */
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mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
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@ -682,7 +406,7 @@ static void rcba_config(void)
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int dram_init(void)
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{
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struct pei_data pei_data __aligned(8) = {
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struct pei_data _pei_data __aligned(8) = {
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.pei_version = PEI_VERSION,
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.mchbar = MCH_BASE_ADDRESS,
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.dmibar = DEFAULT_DMIBAR,
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@ -735,6 +459,7 @@ int dram_init(void)
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{ 0, 4, 0x0000 }, /* P13= Empty */
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},
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};
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struct pei_data *pei_data = &_pei_data;
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struct udevice *dev, *me_dev;
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int ret;
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@ -744,27 +469,74 @@ int dram_init(void)
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ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
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if (ret)
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return ret;
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debug("Boot mode %d\n", gd->arch.pei_boot_mode);
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debug("mrc_input %p\n", pei_data.mrc_input);
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pei_data.boot_mode = gd->arch.pei_boot_mode;
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ret = copy_spd(&pei_data);
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if (!ret)
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ret = sdram_initialise(dev, me_dev, &pei_data);
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ret = copy_spd(dev, pei_data);
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if (ret)
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return ret;
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pei_data->boot_mode = gd->arch.pei_boot_mode;
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debug("Boot mode %d\n", gd->arch.pei_boot_mode);
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debug("mrc_input %p\n", pei_data->mrc_input);
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rcba_config();
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quick_ram_check();
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/*
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* Do not pass MRC data in for recovery mode boot,
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* Always pass it in for S3 resume.
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*/
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if (!recovery_mode_enabled() ||
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pei_data->boot_mode == PEI_BOOT_RESUME) {
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ret = prepare_mrc_cache(pei_data);
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if (ret)
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debug("prepare_mrc_cache failed: %d\n", ret);
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}
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writew(0xCAFE, MCHBAR_REG(SSKPD));
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/* If MRC data is not found we cannot continue S3 resume. */
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if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
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debug("Giving up in sdram_initialize: No MRC data\n");
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reset_cpu(0);
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}
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post_code(POST_DRAM);
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/* Pass console handler in pei_data */
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pei_data->tx_byte = sdram_console_tx_byte;
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/* Wait for ME to be ready */
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ret = intel_early_me_init(me_dev);
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if (ret)
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return ret;
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ret = intel_early_me_uma_size(me_dev);
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if (ret < 0)
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return ret;
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ret = mrc_common_init(dev, pei_data, false);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = sdram_find(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
gd->ram_size = gd->arch.meminfo.total_32bit_memory;
|
||||
|
||||
debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
|
||||
pei_data->mrc_output);
|
||||
|
||||
post_system_agent_init(dev, me_dev, pei_data);
|
||||
report_memory_config();
|
||||
|
||||
/* S3 resume: don't save scrambler seed or MRC data */
|
||||
if (pei_data->boot_mode != PEI_BOOT_RESUME) {
|
||||
/*
|
||||
* This will be copied to SDRAM in reserve_arch(), then written
|
||||
* to SPI flash in mrccache_save()
|
||||
*/
|
||||
gd->arch.mrc_output = (char *)pei_data->mrc_output;
|
||||
gd->arch.mrc_output_len = pei_data->mrc_output_len;
|
||||
ret = write_seeds_to_cmos(pei_data);
|
||||
if (ret)
|
||||
debug("Failed to write seeds to CMOS: %d\n", ret);
|
||||
}
|
||||
|
||||
writew(0xCAFE, MCHBAR_REG(SSKPD));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
rcba_config();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue