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mx35: Clean up lowlevel_init
Clean up mx35 lowlevel_init: - Indent with tabs. - Fix comments. - Use defined values instead of literal constants. - Use defined macros instead of duplicating code. - Use macro parameters with default values instead of #define'd configs. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Benoît Thébaudeau
Stefano Babic
parent
bd23b22bad
commit
151d63cb91
4 changed files with 103 additions and 285 deletions
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@ -19,122 +19,121 @@
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* MA 02111-1307 USA
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*/
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#include <asm/arch/imx-regs.h>
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#include <generated/asm-offsets.h>
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#include <asm/macro.h>
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/*
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* AIPS setup - Only setup MPROTx registers.
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* The PACR default values are good.
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*
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* Default argument values:
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* - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
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* user-mode.
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* - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
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* SDMA to access them.
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*/
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.macro init_aips
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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.macro init_aips mpr=0x77777777, opacr=0x00000000
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =AIPS_MPR_CONFIG
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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ldr r0, =AIPS2_BASE_ADDR
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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ldr r1, =\mpr
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str r1, [r0, #AIPS_MPR_0_7]
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str r1, [r0, #AIPS_MPR_8_15]
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ldr r2, =AIPS2_BASE_ADDR
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str r1, [r2, #AIPS_MPR_0_7]
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str r1, [r2, #AIPS_MPR_8_15]
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =AIPS_OPACR_CONFIG
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str r1, [r0, #0x40]
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str r1, [r0, #0x44]
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str r1, [r0, #0x48]
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str r1, [r0, #0x4C]
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str r1, [r0, #0x50]
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ldr r0, =AIPS2_BASE_ADDR
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str r1, [r0, #0x40]
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str r1, [r0, #0x44]
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str r1, [r0, #0x48]
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str r1, [r0, #0x4C]
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str r1, [r0, #0x50]
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/* Did not change the AIPS control registers access type. */
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ldr r1, =\opacr
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str r1, [r0, #AIPS_OPACR_0_7]
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str r1, [r0, #AIPS_OPACR_8_15]
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str r1, [r0, #AIPS_OPACR_16_23]
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str r1, [r0, #AIPS_OPACR_24_31]
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str r1, [r0, #AIPS_OPACR_32_39]
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str r1, [r2, #AIPS_OPACR_0_7]
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str r1, [r2, #AIPS_OPACR_8_15]
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str r1, [r2, #AIPS_OPACR_16_23]
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str r1, [r2, #AIPS_OPACR_24_31]
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str r1, [r2, #AIPS_OPACR_32_39]
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.endm
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/* MAX (Multi-Layer AHB Crossbar Switch) setup */
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.macro init_max
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/*
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* MAX (Multi-Layer AHB Crossbar Switch) setup
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*
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* Default argument values:
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* - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
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* - SGPCR: always park on last master
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* - MGPCR: restore default values
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*/
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.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
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ldr r0, =MAX_BASE_ADDR
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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ldr r1, =MAX_MPR_CONFIG
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str r1, [r0, #0x000] /* for S0 */
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str r1, [r0, #0x100] /* for S1 */
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str r1, [r0, #0x200] /* for S2 */
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str r1, [r0, #0x300] /* for S3 */
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str r1, [r0, #0x400] /* for S4 */
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/* SGPCR - always park on last master */
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ldr r1, =MAX_SGPCR_CONFIG
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str r1, [r0, #0x010] /* for S0 */
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str r1, [r0, #0x110] /* for S1 */
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str r1, [r0, #0x210] /* for S2 */
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str r1, [r0, #0x310] /* for S3 */
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str r1, [r0, #0x410] /* for S4 */
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/* MGPCR - restore default values */
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ldr r1, =MAX_MGPCR_CONFIG
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str r1, [r0, #0x800] /* for M0 */
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str r1, [r0, #0x900] /* for M1 */
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str r1, [r0, #0xA00] /* for M2 */
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str r1, [r0, #0xB00] /* for M3 */
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str r1, [r0, #0xC00] /* for M4 */
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str r1, [r0, #0xD00] /* for M5 */
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ldr r1, =\mpr
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str r1, [r0, #MAX_MPR0] /* for S0 */
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str r1, [r0, #MAX_MPR1] /* for S1 */
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str r1, [r0, #MAX_MPR2] /* for S2 */
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str r1, [r0, #MAX_MPR3] /* for S3 */
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str r1, [r0, #MAX_MPR4] /* for S4 */
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ldr r1, =\sgpcr
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str r1, [r0, #MAX_SGPCR0] /* for S0 */
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str r1, [r0, #MAX_SGPCR1] /* for S1 */
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str r1, [r0, #MAX_SGPCR2] /* for S2 */
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str r1, [r0, #MAX_SGPCR3] /* for S3 */
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str r1, [r0, #MAX_SGPCR4] /* for S4 */
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ldr r1, =\mgpcr
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str r1, [r0, #MAX_MGPCR0] /* for M0 */
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str r1, [r0, #MAX_MGPCR1] /* for M1 */
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str r1, [r0, #MAX_MGPCR2] /* for M2 */
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str r1, [r0, #MAX_MGPCR3] /* for M3 */
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str r1, [r0, #MAX_MGPCR4] /* for M4 */
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str r1, [r0, #MAX_MGPCR5] /* for M5 */
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.endm
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/* M3IF setup */
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.macro init_m3if
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/* Configure M3IF registers */
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ldr r1, =M3IF_BASE_ADDR
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/*
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* M3IF Control Register (M3IFCTL)
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/*
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* M3IF setup
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*
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* Default argument values:
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* - CTL:
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
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* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
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* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
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* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000
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* MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000
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* MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
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* MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
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* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
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* MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000
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* ------------
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* 0x00000040
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*/
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ldr r0, =M3IF_CONFIG
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str r0, [r1] /* M3IF control reg */
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.macro init_m3if ctl=0x00000040
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/* M3IF Control Register (M3IFCTL) */
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write32 M3IF_BASE_ADDR, \ctl
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.endm
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.macro core_init
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mrc 15, 0, r1, c1, c0, 0
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mrc p15, 0, r1, c1, c0, 0
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mrc 15, 0, r0, c1, c0, 1
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/* Set branch prediction enable */
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #7
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mcr 15, 0, r0, c1, c0, 1
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orr r1, r1, #(1<<11)
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mcr p15, 0, r0, c1, c0, 1
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orr r1, r1, #1 << 11
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/* Set unaligned access enable */
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orr r1, r1, #(1<<22)
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orr r1, r1, #1 << 22
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/* Set low int latency enable */
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orr r1, r1, #(1<<21)
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orr r1, r1, #1 << 21
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mcr 15, 0, r1, c1, c0, 0
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mcr p15, 0, r1, c1, c0, 0
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mov r0, #0
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/* Set branch prediction enable */
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mcr 15, 0, r0, c15, c2, 4
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mcr p15, 0, r0, c15, c2, 4
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mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
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mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
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mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
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mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */
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mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */
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mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
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/*
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* initializes very early AIPS
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* Then it also initializes Multi-Layer AHB Crossbar Switch,
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* M3IF
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* Also setup the Peripheral Port Remap register inside the core
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*/
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ldr r0, =0x40000015 /* start from AIPS 2GB region */
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/* Setup the Peripheral Port Memory Remap Register */
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ldr r0, =0x40000015 /* Start from AIPS 2-GB region */
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mcr p15, 0, r0, c15, c2, 4
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.endm
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@ -22,47 +22,6 @@
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*/
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#include <config.h>
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#include <asm-offsets.h>
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#include <asm/arch/imx-regs.h>
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#include <generated/asm-offsets.h>
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/*
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* Configuration for the flea3 board.
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* These defines are used by the included macros and must
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* be defined first
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*/
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#define AIPS_MPR_CONFIG 0x77777777
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#define AIPS_OPACR_CONFIG 0x00000000
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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#define MAX_MPR_CONFIG 0x00302154
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/* SGPCR - always park on last master */
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#define MAX_SGPCR_CONFIG 0x00000010
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/* MGPCR - restore default values */
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#define MAX_MGPCR_CONFIG 0x00000000
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/*
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* M3IF Control Register (M3IFCTL)
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
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* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
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* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
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* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
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* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
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* ------------
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* 0x00000040
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*/
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#define M3IF_CONFIG 0x00000040
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#define CCM_PDR0_CONFIG 0x00801000
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/*
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* includes MX35 utility macros
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*/
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#include <asm/arch/lowlevel_macro.S>
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.globl lowlevel_init
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@ -23,6 +23,7 @@
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#include <asm/arch/imx-regs.h>
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#include <generated/asm-offsets.h>
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#include "mx35pdk.h"
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#include <asm/arch/lowlevel_macro.S>
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/*
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* return soc version
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@ -40,91 +41,6 @@
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addne \ret, \ret, #0x10
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.endm
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/*
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* AIPS setup - Only setup MPROTx registers.
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* The PACR default values are good.
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*/
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.macro init_aips
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =AIPS_MPR_CONFIG
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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ldr r0, =AIPS2_BASE_ADDR
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =AIPS_OPACR_CONFIG
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str r1, [r0, #0x40]
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str r1, [r0, #0x44]
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str r1, [r0, #0x48]
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str r1, [r0, #0x4C]
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str r1, [r0, #0x50]
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ldr r0, =AIPS2_BASE_ADDR
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str r1, [r0, #0x40]
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str r1, [r0, #0x44]
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str r1, [r0, #0x48]
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str r1, [r0, #0x4C]
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str r1, [r0, #0x50]
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.endm
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/* MAX (Multi-Layer AHB Crossbar Switch) setup */
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.macro init_max
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ldr r0, =MAX_BASE_ADDR
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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ldr r1, =MAX_MPR_CONFIG
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str r1, [r0, #0x000] /* for S0 */
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str r1, [r0, #0x100] /* for S1 */
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str r1, [r0, #0x200] /* for S2 */
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str r1, [r0, #0x300] /* for S3 */
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str r1, [r0, #0x400] /* for S4 */
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/* SGPCR - always park on last master */
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ldr r1, =MAX_SGPCR_CONFIG
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str r1, [r0, #0x010] /* for S0 */
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str r1, [r0, #0x110] /* for S1 */
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str r1, [r0, #0x210] /* for S2 */
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str r1, [r0, #0x310] /* for S3 */
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str r1, [r0, #0x410] /* for S4 */
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/* MGPCR - restore default values */
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ldr r1, =MAX_MGPCR_CONFIG
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str r1, [r0, #0x800] /* for M0 */
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str r1, [r0, #0x900] /* for M1 */
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str r1, [r0, #0xA00] /* for M2 */
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str r1, [r0, #0xB00] /* for M3 */
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str r1, [r0, #0xC00] /* for M4 */
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str r1, [r0, #0xD00] /* for M5 */
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.endm
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/* M3IF setup */
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.macro init_m3if
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/* Configure M3IF registers */
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ldr r1, =M3IF_BASE_ADDR
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/*
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* M3IF Control Register (M3IFCTL)
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
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* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
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* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
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* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
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* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
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* ------------
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* 0x00000040
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*/
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ldr r0, =M3IF_CONFIG
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str r0, [r1] /* M3IF control reg */
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.endm
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/* CPLD on CS5 setup */
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.macro init_debug_board
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ldr r0, =DBG_BASE_ADDR
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@ -210,38 +126,7 @@
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lowlevel_init:
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mov r10, lr
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mrc 15, 0, r1, c1, c0, 0
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mrc 15, 0, r0, c1, c0, 1
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orr r0, r0, #7
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mcr 15, 0, r0, c1, c0, 1
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orr r1, r1, #(1<<11)
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/* Set unaligned access enable */
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orr r1, r1, #(1<<22)
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/* Set low int latency enable */
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orr r1, r1, #(1<<21)
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mcr 15, 0, r1, c1, c0, 0
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mov r0, #0
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/* Set branch prediction enable */
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mcr 15, 0, r0, c15, c2, 4
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mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
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mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
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mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
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/*
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* initializes very early AIPS
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* Then it also initializes Multi-Layer AHB Crossbar Switch,
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* M3IF
|
||||
* Also setup the Peripheral Port Remap register inside the core
|
||||
*/
|
||||
ldr r0, =0x40000015 /* start from AIPS 2GB region */
|
||||
mcr p15, 0, r0, c15, c2, 4
|
||||
core_init
|
||||
|
||||
init_aips
|
||||
|
||||
|
|
|
|||
|
|
@ -26,31 +26,6 @@
|
|||
#ifndef __BOARD_MX35_3STACK_H
|
||||
#define __BOARD_MX35_3STACK_H
|
||||
|
||||
#define AIPS_MPR_CONFIG 0x77777777
|
||||
#define AIPS_OPACR_CONFIG 0x00000000
|
||||
|
||||
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
|
||||
#define MAX_MPR_CONFIG 0x00302154
|
||||
/* SGPCR - always park on last master */
|
||||
#define MAX_SGPCR_CONFIG 0x00000010
|
||||
/* MGPCR - restore default values */
|
||||
#define MAX_MGPCR_CONFIG 0x00000000
|
||||
|
||||
/*
|
||||
* M3IF Control Register (M3IFCTL)
|
||||
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
|
||||
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
|
||||
* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
|
||||
* ------------
|
||||
* 0x00000040
|
||||
*/
|
||||
#define M3IF_CONFIG 0x00000040
|
||||
|
||||
#define DBG_BASE_ADDR WEIM_CTRL_CS5
|
||||
#define DBG_CSCR_U_CONFIG 0x0000D843
|
||||
#define DBG_CSCR_L_CONFIG 0x22252521
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue