From a1f95ff7d7bae4d4dac59aa6d53f3625af43765e Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Wed, 17 Jan 2018 16:13:00 +0530 Subject: [PATCH 01/15] armv8: lsch3: Add serdes and DDR voltage setup Adds SERDES voltage and reset SERDES lanes API and makes enable/disable DDR controller support 0.9V API common. Signed-off-by: Ashish Kumar Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- .../armv8/fsl-layerscape/fsl_lsch3_serdes.c | 287 ++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 39 +++ .../asm/arch-fsl-layerscape/fsl_serdes.h | 2 +- .../asm/arch-fsl-layerscape/immap_lsch3.h | 34 +++ .../arm/include/asm/arch-fsl-layerscape/soc.h | 1 + 5 files changed, 362 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 179cac6e49..9ee0dd23e9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -158,6 +158,293 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, serdes_prtcl_map[NONE] = 1; } +__weak int get_serdes_volt(void) +{ + return -1; +} + +__weak int set_serdes_volt(int svdd) +{ + return -1; +} + +#define LNAGCR0_RT_RSTB 0x00600000 + +#define RSTCTL_RESET_MASK 0x000000E0 + +#define RSTCTL_RSTREQ 0x80000000 +#define RSTCTL_RST_DONE 0x40000000 +#define RSTCTL_RSTERR 0x20000000 + +#define RSTCTL_SDEN 0x00000020 +#define RSTCTL_SDRST_B 0x00000040 +#define RSTCTL_PLLRST_B 0x00000080 + +#define TCALCR_CALRST_B 0x08000000 + +struct serdes_prctl_info { + u32 id; + u32 mask; + u32 shift; +}; + +struct serdes_prctl_info srds_prctl_info[] = { +#ifdef CONFIG_SYS_FSL_SRDS_1 + {.id = 1, + .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK, + .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT + }, + +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + {.id = 2, + .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK, + .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT + }, +#endif + {} /* NULL ENTRY */ +}; + +static int get_serdes_prctl_info_idx(u32 serdes_id) +{ + int pos = 0; + struct serdes_prctl_info *srds_info; + + /* loop until NULL ENTRY defined by .id=0 */ + for (srds_info = srds_prctl_info; srds_info->id != 0; + srds_info++, pos++) { + if (srds_info->id == serdes_id) + return pos; + } + + return -1; +} + +static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg, + struct ccsr_serdes __iomem *serdes_base, + bool cmplt) +{ + int i, pos; + u32 cfg_tmp; + + pos = get_serdes_prctl_info_idx(serdes_id); + if (pos == -1) { + printf("invalid serdes_id %d\n", serdes_id); + return; + } + + cfg_tmp = cfg & srds_prctl_info[pos].mask; + cfg_tmp >>= srds_prctl_info[pos].shift; + + for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { + if (cmplt) + setbits_le32(&serdes_base->lane[i].gcr0, + LNAGCR0_RT_RSTB); + else + clrbits_le32(&serdes_base->lane[i].gcr0, + LNAGCR0_RT_RSTB); + } +} + +static void do_pll_reset(u32 cfg, + struct ccsr_serdes __iomem *serdes_base) +{ + int i; + + for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) { + clrbits_le32(&serdes_base->bank[i].rstctl, + RSTCTL_RESET_MASK); + udelay(1); + + setbits_le32(&serdes_base->bank[i].rstctl, + RSTCTL_RSTREQ); + } + udelay(1); +} + +static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base) +{ + clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B); + clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B); +} + +static void do_rx_tx_cal_reset_comp(u32 cfg, int i, + struct ccsr_serdes __iomem *serdes_base) +{ + if (!(cfg == 0x3 && i == 1)) { + udelay(1); + setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B); + setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B); + } + udelay(1); +} + +static void do_pll_reset_done(u32 cfg, + struct ccsr_serdes __iomem *serdes_base) +{ + int i; + u32 reg = 0; + + for (i = 0; i < 2; i++) { + reg = in_le32(&serdes_base->bank[i].pllcr0); + if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) { + setbits_le32(&serdes_base->bank[i].rstctl, + RSTCTL_RST_DONE); + } + } +} + +static void do_serdes_enable(u32 cfg, + struct ccsr_serdes __iomem *serdes_base) +{ + int i; + + for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) { + setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN); + udelay(1); + + setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B); + udelay(1); + /* Take the Rx/Tx calibration out of reset */ + do_rx_tx_cal_reset_comp(cfg, i, serdes_base); + } +} + +static void do_pll_lock(u32 cfg, + struct ccsr_serdes __iomem *serdes_base) +{ + int i; + u32 reg = 0; + + for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) { + /* if the PLL is not locked, set RST_ERR */ + reg = in_le32(&serdes_base->bank[i].pllcr0); + if (!((reg >> 23) & 0x1)) { + setbits_le32(&serdes_base->bank[i].rstctl, + RSTCTL_RSTERR); + } else { + udelay(1); + setbits_le32(&serdes_base->bank[i].rstctl, + RSTCTL_SDRST_B); + udelay(1); + } + } +} + +int setup_serdes_volt(u32 svdd) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_serdes __iomem *serdes1_base = + (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR; + u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); +#ifdef CONFIG_SYS_FSL_SRDS_2 + struct ccsr_serdes __iomem *serdes2_base = + (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000); + u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); +#endif + u32 cfg_tmp; + int svdd_cur, svdd_tar; + int ret = 1; + + /* Only support switch SVDD to 900mV */ + if (svdd != 900) + return -EINVAL; + + /* Scale up to the LTC resolution is 1/4096V */ + svdd = (svdd * 4096) / 1000; + + svdd_tar = svdd; + svdd_cur = get_serdes_volt(); + if (svdd_cur < 0) + return -EINVAL; + + debug("%s: current SVDD: %x; target SVDD: %x\n", + __func__, svdd_cur, svdd_tar); + if (svdd_cur == svdd_tar) + return 0; + + /* Put the all enabled lanes in reset */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false); +#endif + +#ifdef CONFIG_SYS_FSL_SRDS_2 + do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false); +#endif + + /* Put the all enabled PLL in reset */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = cfg_rcwsrds1 & 0x3; + do_pll_reset(cfg_tmp, serdes1_base); +#endif + +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = cfg_rcwsrds1 & 0xC; + cfg_tmp >>= 2; + do_pll_reset(cfg_tmp, serdes2_base); +#endif + + /* Put the Rx/Tx calibration into reset */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + do_rx_tx_cal_reset(serdes1_base); +#endif + +#ifdef CONFIG_SYS_FSL_SRDS_2 + do_rx_tx_cal_reset(serdes2_base); +#endif + + ret = set_serdes_volt(svdd); + if (ret < 0) { + printf("could not change SVDD\n"); + ret = -1; + } + + /* For each PLL that’s not disabled via RCW enable the SERDES */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = cfg_rcwsrds1 & 0x3; + do_serdes_enable(cfg_tmp, serdes1_base); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = cfg_rcwsrds1 & 0xC; + cfg_tmp >>= 2; + do_serdes_enable(cfg_tmp, serdes2_base); +#endif + + /* Wait for at at least 625us, ensure the PLLs being reset are locked */ + udelay(800); + +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = cfg_rcwsrds1 & 0x3; + do_pll_lock(cfg_tmp, serdes1_base); +#endif + +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = cfg_rcwsrds1 & 0xC; + cfg_tmp >>= 2; + do_pll_lock(cfg_tmp, serdes2_base); +#endif + /* Take the all enabled lanes out of reset */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true); +#endif + + /* For each PLL being reset, and achieved PLL lock set RST_DONE */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = cfg_rcwsrds1 & 0x3; + do_pll_reset_done(cfg_tmp, serdes1_base); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = cfg_rcwsrds1 & 0xC; + cfg_tmp >>= 2; + do_pll_reset_done(cfg_tmp, serdes2_base); +#endif + + return ret; +} + void fsl_serdes_init(void) { #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index dc4a437344..b9f837d58d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -363,6 +363,45 @@ int sata_init(void) } #endif +/* Get VDD in the unit mV from voltage ID */ +int get_core_volt_from_fuse(void) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + int vdd; + u32 fusesr; + u8 vid; + + /* get the voltage ID from fuse status register */ + fusesr = in_le32(&gur->dcfg_fusesr); + debug("%s: fusesr = 0x%x\n", __func__, fusesr); + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; + if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; + } + debug("%s: VID = 0x%x\n", __func__, vid); + switch (vid) { + case 0x00: /* VID isn't supported */ + vdd = -EINVAL; + debug("%s: The VID feature is not supported\n", __func__); + break; + case 0x08: /* 0.9V silicon */ + vdd = 900; + break; + case 0x10: /* 1.0V silicon */ + vdd = 1000; + break; + default: /* Other core voltage */ + vdd = -EINVAL; + debug("%s: The VID(%x) isn't supported\n", __func__, vid); + break; + } + debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); + + return vdd; +} + #elif defined(CONFIG_FSL_LSCH2) #ifdef CONFIG_SCSI_AHCI_PLAT int sata_init(void) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 12fd6b8bdf..9becdf305d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -164,6 +164,7 @@ void fsl_rgmii_init(void); #ifdef CONFIG_FSL_LSCH2 const char *serdes_clock_to_string(u32 clock); int get_serdes_protocol(void); +#endif #ifdef CONFIG_SYS_HAS_SERDES /* Get the volt of SVDD in unit mV */ int get_serdes_volt(void); @@ -172,6 +173,5 @@ int set_serdes_volt(int svdd); /* The target volt of SVDD in unit mV */ int setup_serdes_volt(u32 svdd); #endif -#endif #endif /* __FSL_SERDES_H__ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 957e23b02a..47e8b5a62e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -387,5 +387,39 @@ struct ccsr_reset { u32 ip_rev2; /* 0xbfc */ }; +struct ccsr_serdes { + struct { + u32 rstctl; /* Reset Control Register */ + u32 pllcr0; /* PLL Control Register 0 */ + u32 pllcr1; /* PLL Control Register 1 */ + u32 pllcr2; /* PLL Control Register 2 */ + u32 pllcr3; /* PLL Control Register 3 */ + u32 pllcr4; /* PLL Control Register 4 */ + u32 pllcr5; /* PLL Control Register 5 */ + u8 res[0x20 - 0x1c]; + } bank[2]; + u8 res1[0x90 - 0x40]; + u32 srdstcalcr; /* TX Calibration Control */ + u32 srdstcalcr1; /* TX Calibration Control1 */ + u8 res2[0xa0 - 0x98]; + u32 srdsrcalcr; /* RX Calibration Control */ + u32 srdsrcalcr1; /* RX Calibration Control1 */ + u8 res3[0xb0 - 0xa8]; + u32 srdsgr0; /* General Register 0 */ + u8 res4[0x800 - 0xb4]; + struct serdes_lane { + u32 gcr0; /* General Control Register 0 */ + u32 gcr1; /* General Control Register 1 */ + u32 gcr2; /* General Control Register 2 */ + u32 ssc0; /* Speed Switch Control 0 */ + u32 rec0; /* Receive Equalization Control 0 */ + u32 rec1; /* Receive Equalization Control 1 */ + u32 tec0; /* Transmit Equalization Control 0 */ + u32 ssc1; /* Speed Switch Control 1 */ + u8 res1[0x840 - 0x820]; + } lane[8]; + u8 res5[0x19fc - 0xa00]; +}; + #endif /*__ASSEMBLY__*/ #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 1e65e4e114..cb760b5b38 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -121,6 +121,7 @@ struct ccsr_ahci { #ifdef CONFIG_FSL_LSCH3 void fsl_lsch3_early_init_f(void); +int get_core_volt_from_fuse(void); #elif defined(CONFIG_FSL_LSCH2) void fsl_lsch2_early_init_f(void); int setup_chip_volt(void); From c535ad4e91662e4be41d216251739aef84108757 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Wed, 17 Jan 2018 16:13:01 +0530 Subject: [PATCH 02/15] board: common:vid: Add LS1088A VID Supported voltage values Adds below voltage values supported by LS1088A Soc: 1.025V(default), 0.9875V, 0.9750V, 0.9V, 1.0V, 1.0125V, 1.0250V. Signed-off-by: Ashish Kumar Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- board/freescale/common/vid.c | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index d6d1bfc861..bf63ce007a 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -295,6 +295,43 @@ int adjust_vdd(ulong vdd_override) int ret, i2caddress; unsigned long vdd_string_override; char *vdd_string; +#ifdef CONFIG_ARCH_LS1088A + static const uint16_t vdd[32] = { + 10250, + 9875, + 9750, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 9000, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 10000, /* 1.0000V */ + 10125, + 10250, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; + +#else static const uint16_t vdd[32] = { 10500, 0, /* reserved */ @@ -329,6 +366,7 @@ int adjust_vdd(ulong vdd_override) 0, /* reserved */ 0, /* reserved */ }; +#endif struct vdd_drive { u8 vid; unsigned voltage; From 3607570b11838efee524ad76ccae207afd92fe5a Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Wed, 17 Jan 2018 16:13:02 +0530 Subject: [PATCH 03/15] board: common: vid: Add board specific vdd adjust API Adds a board specific API namely board_adjust_vdd which is required to define the board VDD adjust settings. Signed-off-by: Ashish Kumar Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- board/freescale/common/vid.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index bf63ce007a..89904c199c 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -33,6 +33,14 @@ int __weak board_vdd_drop_compensation(void) return 0; } +/* + * Board specific settings for specific voltage value + */ +int __weak board_adjust_vdd(int vdd) +{ + return 0; +} + /* * Get the i2c address configuration for the IR regulator chip * @@ -470,6 +478,11 @@ int adjust_vdd(ulong vdd_override) vdd_last = set_voltage(i2caddress, vdd_current); } + if (board_adjust_vdd(vdd_target) < 0) { + ret = -1; + goto exit; + } + if (vdd_last > 0) printf("VID: Core voltage after adjustment is at %d mV\n", vdd_last); From 9458316a3a39092ed51f2b8c4880b157e7f4739f Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Wed, 17 Jan 2018 16:13:03 +0530 Subject: [PATCH 04/15] board: common: vid: Move IR chip specific code in flag Moves IR chip (IR36021) specific code in flag to resolve compilation issue where it is not present. For example, LS1088A is having a new LTC3882 voltage chip. Signed-off-by: Ashish Kumar Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- board/freescale/common/vid.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 89904c199c..f68068eaf8 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -41,6 +41,8 @@ int __weak board_adjust_vdd(int vdd) return 0; } +#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ + defined(CONFIG_VOL_MONITOR_IR36021_READ) /* * Get the i2c address configuration for the IR regulator chip * @@ -73,6 +75,7 @@ static int find_ir_chip_on_i2c(void) } return -1; } +#endif /* Maximum loop count waiting for new voltage to take effect */ #define MAX_LOOP_WAIT_NEW_VOL 100 @@ -184,6 +187,7 @@ static int read_voltage(int i2caddress) return voltage_read; } +#ifdef CONFIG_VOL_MONITOR_IR36021_SET /* * We need to calculate how long before the voltage stops to drop * or increase. It returns with the loop count. Each loop takes @@ -243,7 +247,6 @@ static int wait_for_voltage_stable(int i2caddress) return vdd_current; } -#ifdef CONFIG_VOL_MONITOR_IR36021_SET /* Set the voltage to the IR chip */ static int set_voltage_to_IR(int i2caddress, int vdd) { @@ -298,7 +301,12 @@ int adjust_vdd(ulong vdd_override) int re_enable = disable_interrupts(); struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 fusesr; +#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ + defined(CONFIG_VOL_MONITOR_IR36021_READ) u8 vid, buf; +#else + u8 vid; +#endif int vdd_target, vdd_current, vdd_last; int ret, i2caddress; unsigned long vdd_string_override; @@ -386,6 +394,8 @@ int adjust_vdd(ulong vdd_override) ret = -1; goto exit; } +#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ + defined(CONFIG_VOL_MONITOR_IR36021_READ) ret = find_ir_chip_on_i2c(); if (ret < 0) { printf("VID: Could not find voltage regulator on I2C.\n"); @@ -410,6 +420,7 @@ int adjust_vdd(ulong vdd_override) ret = -1; goto exit; } +#endif /* get the voltage ID from fuse status register */ fusesr = in_le32(&gur->dcfg_fusesr); @@ -549,6 +560,8 @@ int adjust_vdd(ulong vdd_override) ret = -1; goto exit; } +#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ + defined(CONFIG_VOL_MONITOR_IR36021_READ) ret = find_ir_chip_on_i2c(); if (ret < 0) { printf("VID: Could not find voltage regulator on I2C.\n"); @@ -573,6 +586,7 @@ int adjust_vdd(ulong vdd_override) ret = -1; goto exit; } +#endif /* get the voltage ID from fuse status register */ fusesr = in_be32(&gur->dcfg_fusesr); @@ -683,6 +697,8 @@ static int print_vdd(void) debug("VID : I2c failed to switch channel\n"); return -1; } +#if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ + defined(CONFIG_VOL_MONITOR_IR36021_READ) ret = find_ir_chip_on_i2c(); if (ret < 0) { printf("VID: Could not find voltage regulator on I2C.\n"); @@ -691,6 +707,7 @@ static int print_vdd(void) i2caddress = ret; debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); } +#endif /* * Read voltage monitor to check real voltage. From 6f2d0a50204842019763dac62c17a4cdb10cc6d3 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Wed, 17 Jan 2018 16:13:04 +0530 Subject: [PATCH 05/15] Kconfig: Add LTC3882 voltage regulator config Adds below LTC3882 voltage regulator config: CONFIG_VOL_MONITOR_LTC3882_READ CONFIG_VOL_MONITOR_LTC3882_SET Signed-off-by: Ashish Kumar Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- board/freescale/common/Kconfig | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index 280f7d46b8..8b89c10aba 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -20,3 +20,19 @@ config CMD_ESBC_VALIDATE esbc_validate - validate signature using RSA verification esbc_halt - put the core in spin loop (Secure Boot Only) + +config VOL_MONITOR_LTC3882_READ + depends on VID + bool "Enable the LTC3882 voltage monitor read" + default n + help + This option enables LTC3882 voltage monitor read + functionality. It is used by common VID driver. + +config VOL_MONITOR_LTC3882_SET + depends on VID + bool "Enable the LTC3882 voltage monitor set" + default n + help + This option enables LTC3882 voltage monitor set + functionality. It is used by common VID driver. From 23a12cb3d05ee2caa860bee7b6f0ebcb40afacce Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Wed, 17 Jan 2018 16:13:05 +0530 Subject: [PATCH 06/15] board: common: vid: Add support for LTC3882 voltage regulator chip Restructures common driver to support LTC3882 voltage regulator chip. Signed-off-by: Ashish Kumar Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- .../asm/arch-fsl-layerscape/immap_lsch3.h | 9 ++- board/freescale/common/vid.c | 77 +++++++++++++++++++ include/configs/ls1088aqds.h | 16 ++++ include/configs/ls1088ardb.h | 15 ++++ 4 files changed, 115 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 47e8b5a62e..642df2f50a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -201,10 +201,15 @@ struct ccsr_gur { u32 gpporcr3; u32 gpporcr4; u8 res_030[0x60-0x30]; -#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F -#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F +#if defined(CONFIG_ARCH_LS1088A) +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25 +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20 +#else +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2 +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7 +#endif u32 dcfg_fusesr; /* Fuse status register */ u8 res_064[0x70-0x64]; u32 devdisr; /* Device disable control 1 */ diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index f68068eaf8..a9451c5c6e 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -174,6 +174,36 @@ static int read_voltage_from_IR(int i2caddress) } #endif +#ifdef CONFIG_VOL_MONITOR_LTC3882_READ +/* read the current value of the LTC Regulator Voltage */ +static int read_voltage_from_LTC(int i2caddress) +{ + int ret, vcode = 0; + u8 chan = PWM_CHANNEL0; + + /* select the PAGE 0 using PMBus commands PAGE for VDD*/ + ret = i2c_write(I2C_VOL_MONITOR_ADDR, + PMBUS_CMD_PAGE, 1, &chan, 1); + if (ret) { + printf("VID: failed to select VDD Page 0\n"); + return ret; + } + + /*read the output voltage using PMBus command READ_VOUT*/ + ret = i2c_read(I2C_VOL_MONITOR_ADDR, + PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); + if (ret) { + printf("VID: failed to read the volatge\n"); + return ret; + } + + /* Scale down to the real mV as LTC resolution is 1/4096V,rounding up */ + vcode = DIV_ROUND_UP(vcode * 1000, 4096); + + return vcode; +} +#endif + static int read_voltage(int i2caddress) { int voltage_read; @@ -181,6 +211,8 @@ static int read_voltage(int i2caddress) voltage_read = read_voltage_from_INA220(i2caddress); #elif defined CONFIG_VOL_MONITOR_IR36021_READ voltage_read = read_voltage_from_IR(i2caddress); +#elif defined CONFIG_VOL_MONITOR_LTC3882_READ + voltage_read = read_voltage_from_LTC(i2caddress); #else return -1; #endif @@ -281,6 +313,43 @@ static int set_voltage_to_IR(int i2caddress, int vdd) debug("VID: Current voltage is %d mV\n", vdd_last); return vdd_last; } + +#endif + +#ifdef CONFIG_VOL_MONITOR_LTC3882_SET +/* this function sets the VDD and returns the value set */ +static int set_voltage_to_LTC(int i2caddress, int vdd) +{ + int ret, vdd_last, vdd_target = vdd; + + /* Scale up to the LTC resolution is 1/4096V */ + vdd = (vdd * 4096) / 1000; + + /* 5-byte buffer which needs to be sent following the + * PMBus command PAGE_PLUS_WRITE. + */ + u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, + vdd & 0xFF, (vdd & 0xFF00) >> 8}; + + /* Write the desired voltage code to the regulator */ + ret = i2c_write(I2C_VOL_MONITOR_ADDR, + PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); + if (ret) { + printf("VID: I2C failed to write to the volatge regulator\n"); + return -1; + } + + /* Wait for the volatge to get to the desired value */ + do { + vdd_last = read_voltage_from_LTC(i2caddress); + if (vdd_last < 0) { + printf("VID: Couldn't read sensor abort VID adjust\n"); + return -1; + } + } while (vdd_last != vdd_target); + + return vdd_last; +} #endif static int set_voltage(int i2caddress, int vdd) @@ -289,6 +358,8 @@ static int set_voltage(int i2caddress, int vdd) #ifdef CONFIG_VOL_MONITOR_IR36021_SET vdd_last = set_voltage_to_IR(i2caddress, vdd); +#elif defined CONFIG_VOL_MONITOR_LTC3882_SET + vdd_last = set_voltage_to_LTC(i2caddress, vdd); #else #error Specific voltage monitor must be defined #endif @@ -472,6 +543,11 @@ int adjust_vdd(ulong vdd_override) } vdd_current = vdd_last; debug("VID: Core voltage is currently at %d mV\n", vdd_last); + +#ifdef CONFIG_VOL_MONITOR_LTC3882_SET + /* Set the target voltage */ + vdd_last = vdd_current = set_voltage(i2caddress, vdd_target); +#else /* * Adjust voltage to at or one step above target. * As measurements are less precise than setting the values @@ -489,6 +565,7 @@ int adjust_vdd(ulong vdd_override) vdd_last = set_voltage(i2caddress, vdd_current); } +#endif if (board_adjust_vdd(vdd_target) < 0) { ret = -1; goto exit; diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 8fbf89001e..ff2f916e56 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -279,6 +279,22 @@ unsigned long get_board_ddr_clk(void); #define I2C_MUX_CH_DEFAULT 0x8 #define I2C_MUX_CH5 0xD +#define I2C_MUX_CH_VOL_MONITOR 0xA + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x63 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +/* PM Bus commands code for LTC3882*/ +#define PMBUS_CMD_PAGE 0x0 +#define PMBUS_CMD_READ_VOUT 0x8B +#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 +#define PMBUS_CMD_VOUT_COMMAND 0x21 + +#define PWM_CHANNEL0 0x0 + /* * RTC configuration */ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index d0066e3551..4c290c5cbe 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -225,6 +225,21 @@ #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define I2C_MUX_CH_VOL_MONITOR 0xA +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x63 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +/* PM Bus commands code for LTC3882*/ +#define PMBUS_CMD_PAGE 0x0 +#define PMBUS_CMD_READ_VOUT 0x8B +#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 +#define PMBUS_CMD_VOUT_COMMAND 0x21 + +#define PWM_CHANNEL0 0x0 + /* * I2C bus multiplexer */ From 554d33f3db3cdbb02f440ab3b667ff2bc3cfa2b1 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Wed, 17 Jan 2018 16:13:06 +0530 Subject: [PATCH 07/15] ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs Sets DDR configuration parameter cdr1 before all other settings to support case 0.9v VDD is enabled for some SoCs Signed-off-by: Ashish Kumar Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- drivers/ddr/fsl/fsl_ddr_gen4.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 058c9b9da8..b3a27ec5a8 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -95,6 +95,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (step == 2) goto step2; + /* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/ + ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); + if (regs->ddr_eor) ddr_out32(&ddr->eor, regs->ddr_eor); @@ -183,7 +186,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); - ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); #ifdef CONFIG_DEEP_SLEEP if (is_warm_boot()) { ddr_out32(&ddr->sdram_cfg_2, From 75ad48153f29d54359a47bc06be6a64fbecead56 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Wed, 17 Jan 2018 16:13:07 +0530 Subject: [PATCH 08/15] ls1088a: ddr: configure DDR for 0.9v for VID support When VID feature is supported, check the contents of fuse register and configure DDR operate at 0.9v. Signed-off-by: Ashish Kumar Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- board/freescale/ls1088a/ddr.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/board/freescale/ls1088a/ddr.c b/board/freescale/ls1088a/ddr.c index e24bfd557c..2240454ec8 100644 --- a/board/freescale/ls1088a/ddr.c +++ b/board/freescale/ls1088a/ddr.c @@ -13,6 +13,23 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) +static void fsl_ddr_setup_0v9_volt(memctl_options_t *popts) +{ + int vdd; + + vdd = get_core_volt_from_fuse(); + /* Nothing to do for silicons doesn't support VID */ + if (vdd < 0) + return; + + if (vdd == 900) { + popts->ddr_cdr1 |= DDR_CDR1_V0PT9_EN; + debug("VID: configure DDR to support 900 mV\n"); + } +} +#endif + void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) @@ -87,6 +104,10 @@ found: popts->addr_hash = 1; popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); +#if defined(CONFIG_VID) && (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) + fsl_ddr_setup_0v9_volt(popts); +#endif + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; } From 1fab98fb90b0350210ac6938cb61647c66dcf0f7 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Wed, 17 Jan 2018 16:13:08 +0530 Subject: [PATCH 09/15] common: board_f: vid: Add VID specific API to adjust core voltage Adds a VID specific API in init_sequence_f and spl code flow namely init_func_vid which is required to adjust core voltage. VID specific code is required in spl, hence moving flag CONFIG_VID out of spl flags. Signed-off-by: Ashish Kumar Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 +++ board/freescale/common/Makefile | 2 +- common/board_f.c | 10 ++++++++++ include/common.h | 3 +++ 4 files changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 1c694e7c67..4093d15e56 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -84,6 +84,9 @@ void board_init_f(ulong dummy) #ifdef CONFIG_SPL_I2C_SUPPORT i2c_init_all(); +#endif +#ifdef CONFIG_VID + init_func_vid(); #endif dram_init(); #ifdef CONFIG_SPL_FSL_LS_PPA diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index e13cb2063c..939e9c66a5 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -23,8 +23,8 @@ obj-$(CONFIG_FMAN_ENET) += fman.o obj-$(CONFIG_FSL_PIXIS) += pixis.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o -obj-$(CONFIG_VID) += vid.o endif +obj-$(CONFIG_VID) += vid.o obj-$(CONFIG_FSL_QIXIS) += qixis.o obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o ifndef CONFIG_SPL_BUILD diff --git a/common/board_f.c b/common/board_f.c index 0bdce64ca5..7f594d9eaf 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -200,6 +200,13 @@ static int init_func_i2c(void) } #endif +#if defined(CONFIG_VID) +__weak int init_func_vid(void) +{ + return 0; +} +#endif + #if defined(CONFIG_HARD_SPI) static int init_func_spi(void) { @@ -801,6 +808,9 @@ static const init_fnc_t init_sequence_f[] = { #if defined(CONFIG_SYS_I2C) init_func_i2c, #endif +#if defined(CONFIG_VID) && !defined(CONFIG_SPL) + init_func_vid, +#endif #if defined(CONFIG_HARD_SPI) init_func_spi, #endif diff --git a/include/common.h b/include/common.h index 436200044f..0fe9439a93 100644 --- a/include/common.h +++ b/include/common.h @@ -364,6 +364,9 @@ int embedded_dtb_select(void); int misc_init_f (void); int misc_init_r (void); +#if defined(CONFIG_VID) +int init_func_vid(void); +#endif /* common/exports.c */ void jumptable_init(void); From ef0789b7c6444578561e3f333194660de944877e Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Wed, 17 Jan 2018 16:13:09 +0530 Subject: [PATCH 10/15] ls1088a: Add VID support for QDS and RDB platforms This patch adds the support for VID on LS1088AQDS and LS1088ARDB systems. It reads the fusesr register and changes the VDD accordingly by adjusting the voltage via LTC3882 regulator. This patch also takes care of the special case of 0.9V VDD is present in fusesr register. In that case,it also changes the SERDES voltage by disabling the SERDES, changing the SVDD and then re-enabling SERDES. Signed-off-by: Raghav Dogra Signed-off-by: Ashish Kumar Signed-off-by: Amrita Kumari Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- board/freescale/ls1088a/ls1088a.c | 127 ++++++++++++++++++++++++++++++ include/configs/ls1088aqds.h | 11 +++ include/configs/ls1088ardb.h | 12 +++ 3 files changed, 150 insertions(+) diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index d12bcaed8f..188f76dcd2 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -19,9 +19,13 @@ #include #include #include +#include +#include #include "../common/qixis.h" #include "ls1088a_qixis.h" +#include "../common/vid.h" +#include DECLARE_GLOBAL_DATA_PTR; @@ -51,6 +55,16 @@ unsigned long long get_qixis_addr(void) } #endif +#if defined(CONFIG_VID) +int init_func_vid(void) +{ + if (adjust_vdd(0) < 0) + printf("core voltage not adjusted\n"); + + return 0; +} +#endif + #if !defined(CONFIG_SPL_BUILD) int checkboard(void) { @@ -323,6 +337,119 @@ int misc_init_r(void) } #endif +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel); +} + +#ifdef CONFIG_TARGET_LS1088AQDS +/* read the current value(SVDD) of the LTM Regulator Voltage */ +int get_serdes_volt(void) +{ + int ret, vcode = 0; + u8 chan = PWM_CHANNEL0; + + /* Select the PAGE 0 using PMBus commands PAGE for VDD */ + ret = i2c_write(I2C_SVDD_MONITOR_ADDR, + PMBUS_CMD_PAGE, 1, &chan, 1); + if (ret) { + printf("VID: failed to select VDD Page 0\n"); + return ret; + } + + /* Read the output voltage using PMBus command READ_VOUT */ + ret = i2c_read(I2C_SVDD_MONITOR_ADDR, + PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2); + if (ret) { + printf("VID: failed to read the volatge\n"); + return ret; + } + + return vcode; +} + +int set_serdes_volt(int svdd) +{ + int ret, vdd_last; + u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND, + svdd & 0xFF, (svdd & 0xFF00) >> 8}; + + /* Write the desired voltage code to the SVDD regulator */ + ret = i2c_write(I2C_SVDD_MONITOR_ADDR, + PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5); + if (ret) { + printf("VID: I2C failed to write to the volatge regulator\n"); + return -1; + } + + /* Wait for the volatge to get to the desired value */ + do { + vdd_last = get_serdes_volt(); + if (vdd_last < 0) { + printf("VID: Couldn't read sensor abort VID adjust\n"); + return -1; + } + } while (vdd_last != svdd); + + return 1; +} +#else +int get_serdes_volt(void) +{ + return 0; +} + +int set_serdes_volt(int svdd) +{ + int ret; + u8 brdcfg4; + + printf("SVDD changing of RDB\n"); + + /* Read the BRDCFG54 via CLPD */ + ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR, + QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); + if (ret) { + printf("VID: I2C failed to read the CPLD BRDCFG4\n"); + return -1; + } + + brdcfg4 = brdcfg4 | 0x08; + + /* Write to the BRDCFG4 */ + ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, + QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); + if (ret) { + debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n"); + return -1; + } + + /* Wait for the volatge to get to the desired value */ + udelay(10000); + + return 1; +} +#endif + +/* this function disables the SERDES, changes the SVDD Voltage and enables it*/ +int board_adjust_vdd(int vdd) +{ + int ret = 0; + + debug("%s: vdd = %d\n", __func__, vdd); + + /* Special settings to be performed when voltage is 900mV */ + if (vdd == 900) { + ret = setup_serdes_volt(vdd); + if (ret < 0) { + ret = -1; + goto exit; + } + } +exit: + return ret; +} + int board_init(void) { init_final_memctl_regs(); diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index ff2f916e56..bf76ed4d25 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -286,6 +286,17 @@ unsigned long get_board_ddr_clk(void); #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 +#define I2C_SVDD_MONITOR_ADDR 0x4F + +#define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" +#define CONFIG_VID + +/* The lowest and highest voltage allowed for LS1088AQDS */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +#define CONFIG_VOL_MONITOR_LTC3882_SET +#define CONFIG_VOL_MONITOR_LTC3882_READ /* PM Bus commands code for LTC3882*/ #define PMBUS_CMD_PAGE 0x0 diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 4c290c5cbe..7b046e1f22 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -151,6 +151,7 @@ #endif #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_BRDCFG4_OFFSET 0x54 #define QIXIS_LBMAP_SWITCH 2 #define QIXIS_QMAP_MASK 0xe0 #define QIXIS_QMAP_SHIFT 5 @@ -231,6 +232,17 @@ #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 +#define I2C_SVDD_MONITOR_ADDR 0x4F + +#define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv" +#define CONFIG_VID + +/* The lowest and highest voltage allowed for LS1088ARDB */ +#define VDD_MV_MIN 819 +#define VDD_MV_MAX 1212 + +#define CONFIG_VOL_MONITOR_LTC3882_SET +#define CONFIG_VOL_MONITOR_LTC3882_READ /* PM Bus commands code for LTC3882*/ #define PMBUS_CMD_PAGE 0x0 From 980d61a270963be0fe439273136b68c859fe3858 Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Wed, 17 Jan 2018 16:13:10 +0530 Subject: [PATCH 11/15] armv8: ls1088a: vid: Compiling VID specific functions for SPL Enables and compiles VID specific functions for SPL. Signed-off-by: Pankit Garg Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- board/freescale/ls1088a/ls1088a.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 188f76dcd2..0769e9069b 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -221,6 +221,7 @@ unsigned long get_board_ddr_clk(void) return 66666666; } +#endif int select_i2c_ch_pca9547(u8 ch) { @@ -235,6 +236,7 @@ int select_i2c_ch_pca9547(u8 ch) return 0; } +#if !defined(CONFIG_SPL_BUILD) void board_retimer_init(void) { u8 reg; @@ -336,6 +338,7 @@ int misc_init_r(void) return 0; } #endif +#endif int i2c_multiplexer_select_vid_channel(u8 channel) { @@ -450,6 +453,7 @@ exit: return ret; } +#if !defined(CONFIG_SPL_BUILD) int board_init(void) { init_final_memctl_regs(); From 6d48d1c4b45fe8d308c45115946a5730b102f3ab Mon Sep 17 00:00:00 2001 From: Pankaj Bansal Date: Thu, 18 Jan 2018 09:43:33 +0530 Subject: [PATCH 12/15] ARM: dts: Freescale: re-license device tree files under GPLv2+/X11 The current GPL only licensing on the device trees makes it very impractical for other software components licensed under another license. To make it easier to reuse them, re-license the the device trees for Freescale (now NXP) SoCs and boards under GPLv2+/X11 dual license. Same trend is followed in linux. Cc: Priyanka Jain Cc: Mingkai Hu Cc: York Sun Signed-off-by: Pankaj Bansal Reviewed-by: York Sun --- arch/arm/dts/fsl-ls1012a-frdm.dts | 2 +- arch/arm/dts/fsl-ls1012a-frdm.dtsi | 2 +- arch/arm/dts/fsl-ls1012a-qds.dts | 2 +- arch/arm/dts/fsl-ls1012a-qds.dtsi | 2 +- arch/arm/dts/fsl-ls1012a-rdb.dts | 2 +- arch/arm/dts/fsl-ls1012a-rdb.dtsi | 4 +--- arch/arm/dts/fsl-ls1012a.dtsi | 2 +- arch/arm/dts/fsl-ls1043a-qds-duart.dts | 2 +- arch/arm/dts/fsl-ls1043a-qds-lpuart.dts | 2 +- arch/arm/dts/fsl-ls1043a-qds.dtsi | 4 +--- arch/arm/dts/fsl-ls1043a-rdb.dts | 4 +--- arch/arm/dts/fsl-ls1043a.dtsi | 4 +--- arch/arm/dts/fsl-ls1046a-qds-duart.dts | 2 +- arch/arm/dts/fsl-ls1046a-qds-lpuart.dts | 2 +- arch/arm/dts/fsl-ls1046a-qds.dtsi | 4 +--- arch/arm/dts/fsl-ls1046a-rdb.dts | 4 +--- arch/arm/dts/fsl-ls1046a.dtsi | 4 +--- arch/arm/dts/fsl-ls1088a-qds.dts | 2 +- arch/arm/dts/fsl-ls1088a-rdb.dts | 2 +- arch/arm/dts/fsl-ls1088a.dtsi | 2 +- arch/arm/dts/fsl-ls2080a-qds.dts | 2 +- arch/arm/dts/fsl-ls2080a-rdb.dts | 2 +- arch/arm/dts/fsl-ls2080a.dtsi | 2 +- arch/arm/dts/fsl-ls2081a-rdb.dts | 2 +- arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 2 +- 25 files changed, 25 insertions(+), 39 deletions(-) diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts index 983e599b9b..6ea5f82ec4 100644 --- a/arch/arm/dts/fsl-ls1012a-frdm.dts +++ b/arch/arm/dts/fsl-ls1012a-frdm.dts @@ -3,7 +3,7 @@ * * Copyright 2016, Freescale Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi index 25dcdd2929..d453f5daca 100644 --- a/arch/arm/dts/fsl-ls1012a-frdm.dtsi +++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi @@ -3,7 +3,7 @@ * * Copyright 2016, Freescale Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /include/ "fsl-ls1012a.dtsi" diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts index 76db36ca39..ccc9023e39 100644 --- a/arch/arm/dts/fsl-ls1012a-qds.dts +++ b/arch/arm/dts/fsl-ls1012a-qds.dts @@ -1,7 +1,7 @@ /* * Copyright 2016 Freescale Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi index d17cd99ed9..908fbedf03 100644 --- a/arch/arm/dts/fsl-ls1012a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi @@ -1,7 +1,7 @@ /* * Copyright 2016 Freescale Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /include/ "fsl-ls1012a.dtsi" diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts index f683812c30..400cd9e7e8 100644 --- a/arch/arm/dts/fsl-ls1012a-rdb.dts +++ b/arch/arm/dts/fsl-ls1012a-rdb.dts @@ -3,7 +3,7 @@ * * Copyright 2016, Freescale Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi index bf407aeb94..c4b6adffb8 100644 --- a/arch/arm/dts/fsl-ls1012a-rdb.dtsi +++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi @@ -3,9 +3,7 @@ * * Copyright 2016, Freescale Semiconductor * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * SPDX-License-Identifier: GPL-2.0+ X11 */ /include/ "fsl-ls1012a.dtsi" diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 23b3cec434..215e095c32 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -1,7 +1,7 @@ /* * Copyright 2016 Freescale Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /include/ "skeleton64.dtsi" diff --git a/arch/arm/dts/fsl-ls1043a-qds-duart.dts b/arch/arm/dts/fsl-ls1043a-qds-duart.dts index 2124e38504..cf53ab0025 100644 --- a/arch/arm/dts/fsl-ls1043a-qds-duart.dts +++ b/arch/arm/dts/fsl-ls1043a-qds-duart.dts @@ -3,7 +3,7 @@ * * Copyright (C) 2015, Freescale Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts index 18adb97d18..118c45deef 100644 --- a/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts +++ b/arch/arm/dts/fsl-ls1043a-qds-lpuart.dts @@ -3,7 +3,7 @@ * * Copyright (C) 2015, Freescale Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi index 21011720dd..9611619b59 100644 --- a/arch/arm/dts/fsl-ls1043a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi @@ -5,9 +5,7 @@ * * Mingkai Hu * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * SPDX-License-Identifier: GPL-2.0+ X11 */ /include/ "fsl-ls1043a.dtsi" diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts index f271e714b1..27670a8629 100644 --- a/arch/arm/dts/fsl-ls1043a-rdb.dts +++ b/arch/arm/dts/fsl-ls1043a-rdb.dts @@ -5,9 +5,7 @@ * * Mingkai Hu * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index fe6698f161..3cc20774c1 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -5,9 +5,7 @@ * * Mingkai Hu * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * SPDX-License-Identifier: GPL-2.0+ X11 */ /include/ "skeleton64.dtsi" diff --git a/arch/arm/dts/fsl-ls1046a-qds-duart.dts b/arch/arm/dts/fsl-ls1046a-qds-duart.dts index 10a95ea025..9a4b84fedb 100644 --- a/arch/arm/dts/fsl-ls1046a-qds-duart.dts +++ b/arch/arm/dts/fsl-ls1046a-qds-duart.dts @@ -3,7 +3,7 @@ * * Copyright (C) 2016, Freescale Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts index 21243d0766..1c4d362656 100644 --- a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts +++ b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts @@ -3,7 +3,7 @@ * * Copyright (C) 2016, Freescale Semiconductor * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index a49ca08d88..4e1920be87 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -5,9 +5,7 @@ * * Mingkai Hu * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * SPDX-License-Identifier: GPL-2.0+ X11 */ /include/ "fsl-ls1046a.dtsi" diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts index 49024541e3..646e4772c1 100644 --- a/arch/arm/dts/fsl-ls1046a-rdb.dts +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -5,9 +5,7 @@ * * Mingkai Hu * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 408e81e415..f46707d320 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -5,9 +5,7 @@ * * Mingkai Hu * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. + * SPDX-License-Identifier: GPL-2.0+ X11 */ /include/ "skeleton64.dtsi" diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts index 9b7bef42b8..225c7c53c7 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dts +++ b/arch/arm/dts/fsl-ls1088a-qds.dts @@ -3,7 +3,7 @@ * * Copyright 2017 NXP * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts index 30ceed8212..7b6ca1d49e 100644 --- a/arch/arm/dts/fsl-ls1088a-rdb.dts +++ b/arch/arm/dts/fsl-ls1088a-rdb.dts @@ -3,7 +3,7 @@ * * Copyright 2017 NXP * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 64b4fcf12b..f8f8654e15 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -3,7 +3,7 @@ * * Copyright 2017 NXP * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ / { diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index 0a7f1ffb2d..b85b802ee6 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -3,7 +3,7 @@ * * Copyright 2013-2015 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls2080a-rdb.dts b/arch/arm/dts/fsl-ls2080a-rdb.dts index 1a1813bdbf..04b1a71016 100644 --- a/arch/arm/dts/fsl-ls2080a-rdb.dts +++ b/arch/arm/dts/fsl-ls2080a-rdb.dts @@ -3,7 +3,7 @@ * * Copyright 2013-2015 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 79047d502b..69273a9836 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -3,7 +3,7 @@ * * Copyright 2013-2015 Freescale Semiconductor, Inc. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ / { diff --git a/arch/arm/dts/fsl-ls2081a-rdb.dts b/arch/arm/dts/fsl-ls2081a-rdb.dts index aa4aa68c9c..ef668a3432 100644 --- a/arch/arm/dts/fsl-ls2081a-rdb.dts +++ b/arch/arm/dts/fsl-ls2081a-rdb.dts @@ -5,7 +5,7 @@ * * Copyright 2017 NXP * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts index 3230e7ed7d..9e3875d8c0 100644 --- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts +++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts @@ -5,7 +5,7 @@ * * Copyright 2017 NXP * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; From d7af2baa49c60c097d77986f49d7c2db06080c8e Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Wed, 17 Jan 2018 10:03:45 -0200 Subject: [PATCH 13/15] crypto/fsl: Fix HW accelerated hash commands The hash command function were not flushing the dcache before passing data to CAAM/DMA and not invalidating the dcache when getting data back. Due the data cache incoherency, HW accelerated hash commands used to fail with CAAM errors like "Invalid KEY Command". Check if pbuf and pout buffers are properly aligned to the cache line size and flush/invalidate the memory regions to address this issue. This solution is based in a previous work from Clemens Gruber in commit 598e9dccc75d ("crypto/fsl: fix BLOB encapsulation and decapsulation") Reported-by: Anatolij Gustschin Signed-off-by: Breno Lima Reviewed-by: York Sun --- common/hash.c | 7 ++++++- drivers/crypto/fsl/fsl_hash.c | 20 +++++++++++++++++++- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/common/hash.c b/common/hash.c index cf4d70f852..69d53ed251 100644 --- a/common/hash.c +++ b/common/hash.c @@ -390,7 +390,7 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, if (multi_hash()) { struct hash_algo *algo; - uint8_t output[HASH_MAX_DIGEST_SIZE]; + u8 *output; uint8_t vsum[HASH_MAX_DIGEST_SIZE]; void *buf; @@ -405,6 +405,9 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, return 1; } + output = memalign(ARCH_DMA_MINALIGN, + sizeof(uint32_t) * HASH_MAX_DIGEST_SIZE); + buf = map_sysmem(addr, len); algo->hash_func_ws(buf, len, output, algo->chunk_size); unmap_sysmem(buf); @@ -440,6 +443,8 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, store_result(algo, output, *argv, flags & HASH_FLAG_ENV); } + unmap_sysmem(output); + } /* Horrible code size hack for boards that just want crc32 */ diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index a63eba389d..9373a39931 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -7,6 +7,7 @@ #include #include +#include #include "jobdesc.h" #include "desc.h" #include "jr.h" @@ -163,20 +164,37 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len, { int ret = 0; uint32_t *desc; + unsigned int size; - desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); + desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); return -ENOMEM; } + if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) || + !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) { + puts("Error: Address arguments are not aligned\n"); + return -EINVAL; + } + + size = ALIGN(buf_len, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)pbuf, (unsigned long)pbuf + size); + inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout, driver_hash[algo].alg_type, driver_hash[algo].digestsize, 0); + size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); + ret = run_descriptor_jr(desc); + size = ALIGN(driver_hash[algo].digestsize, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)pout, + (unsigned long)pout + size); + free(desc); return ret; } From fe997689c33b2c36a6eb7b704177a774b3c9131f Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Wed, 17 Jan 2018 12:16:36 +0530 Subject: [PATCH 14/15] fsl: common: qixis: Add ifc and emmc switching via qixis Currently only SD, NAND can be secondary boot sources controlled by FPGA/CPLD via qixis commands. For SoC like LS1088 IFC-NOR can be secondary boot source, while QSPI-NOR is the primary. Add options in qixis to switch to other boot sources including ifc and emmc. Signed-off-by: Ashish Kumar Reviewed-by: York Sun --- board/freescale/common/qixis.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 24459f8635..844c00a9e3 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -234,6 +234,28 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar QIXIS_WRITE(rcfg_ctl, 0x21); #else printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "ifc") == 0) { +#ifdef QIXIS_LBMAP_IFC + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_IFC); + set_rcw_src(QIXIS_RCW_SRC_IFC); + QIXIS_WRITE(rcfg_ctl, 0x20); + QIXIS_WRITE(rcfg_ctl, 0x21); +#else + printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "emmc") == 0) { +#ifdef QIXIS_LBMAP_EMMC + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_EMMC); + set_rcw_src(QIXIS_RCW_SRC_EMMC); + QIXIS_WRITE(rcfg_ctl, 0x20); + QIXIS_WRITE(rcfg_ctl, 0x21); +#else + printf("Not implemented\n"); #endif } else if (strcmp(argv[1], "sd_qspi") == 0) { #ifdef QIXIS_LBMAP_SD_QSPI From 6c8945ec41cb7bff27fbacc88316e3e557c20240 Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Wed, 17 Jan 2018 12:16:37 +0530 Subject: [PATCH 15/15] armv8: ls1088a: Add IFC and eMMC as qixis boot sources Add macro QIXIS_LBMAP_EMMC, QIXIS_LBMAP_IFC, QIXIS_RCW_SRC_IFC, QIXIS_RCW_SRC_EMMC to enable IFC and eMMC as boot sources for qixis commands. Signed-off-by: Ashish Kumar [YS: Modify subject and add commit message] Reviewed-by: York Sun --- include/configs/ls1088aqds.h | 4 ++++ include/configs/ls1088ardb.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index bf76ed4d25..5674a5d207 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -170,9 +170,13 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_DFLTBANK 0x0e #define QIXIS_LBMAP_ALTBANK 0x2e #define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_EMMC 0x00 +#define QIXIS_LBMAP_IFC 0x00 #define QIXIS_LBMAP_SD_QSPI 0x0e #define QIXIS_LBMAP_QSPI 0x0e +#define QIXIS_RCW_SRC_IFC 0x25 #define QIXIS_RCW_SRC_SD 0x40 +#define QIXIS_RCW_SRC_EMMC 0x41 #define QIXIS_RCW_SRC_QSPI 0x62 #define QIXIS_RST_CTL_RESET 0x41 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 7b046e1f22..a6271f5ae2 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -160,9 +160,11 @@ #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x20 #define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_EMMC 0x00 #define QIXIS_LBMAP_SD_QSPI 0x00 #define QIXIS_LBMAP_QSPI 0x00 #define QIXIS_RCW_SRC_SD 0x40 +#define QIXIS_RCW_SRC_EMMC 0x41 #define QIXIS_RCW_SRC_QSPI 0x62 #define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20