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board: phytec: phycore_imx8mm: Clean up spl

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Remove not needed code in the spl board code.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
This commit is contained in:
Teresa Remmet 2021-10-06 11:56:46 +02:00 • committed by Stefano Babic
parent f254a46809
commit 163089ca57
1 changed files with 1 additions and 18 deletions
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19
board/phytec/phycore_imx8mm/spl.c
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@ -12,8 +12,6 @@
#include <asm/global_data.h> #include <asm/global_data.h>
#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/iomux-v3.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <hang.h> #include <hang.h>
#include <init.h> #include <init.h>
#include <log.h> #include <log.h>
@ -39,7 +37,7 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
} }
} }
void spl_dram_init(void) static void spl_dram_init(void)
{ {
ddr_init(&dram_timing); ddr_init(&dram_timing);
} }
@ -54,15 +52,10 @@ void spl_board_init(void)
puts("Normal Boot\n"); puts("Normal Boot\n");
} }
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name) int board_fit_config_name_match(const char *name)
{ {
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0; return 0;
} }
#endif
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE)
@ -91,7 +84,6 @@ int board_early_init_f(void)
void board_init_f(ulong dummy) void board_init_f(ulong dummy)
{ {
struct udevice *dev;
int ret; int ret;
arch_cpu_init(); arch_cpu_init();
@ -100,8 +92,6 @@ void board_init_f(ulong dummy)
board_early_init_f(); board_early_init_f();
timer_init();
preloader_console_init(); preloader_console_init();
/* Clear the BSS. */ /* Clear the BSS. */
@ -113,13 +103,6 @@ void board_init_f(ulong dummy)
hang(); hang();
} }
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000", &dev);
if (ret < 0) {
printf("Failed to find clock node. Check device tree\n");
hang();
}
enable_tzc380(); enable_tzc380();
/* DDR initialization */ /* DDR initialization */