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ARM: dts: rmobile: Import R8A7790 DTS from Linux 4.15-rc8
Import the Renesas R8A7790 DTS and headers from upstream Linux kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
319202640a
commit
16b6e4aa37
5 changed files with 2769 additions and 0 deletions
856
arch/arm/dts/r8a7790-lager.dts
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856
arch/arm/dts/r8a7790-lager.dts
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@ -0,0 +1,856 @@
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/*
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* Device Tree Source for the Lager board
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*
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* Copyright (C) 2013-2014 Renesas Solutions Corp.
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* Copyright (C) 2014 Cogent Embedded, Inc.
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* Copyright (C) 2015-2016 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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/*
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* SSI-AK4643
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*
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* SW1: 1: AK4643
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* 2: CN22
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* 3: ADV7511
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*
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* This command is required when Playback/Capture
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*
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* amixer set "LINEOUT Mixer DACL" on
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* amixer set "DVC Out" 100%
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* amixer set "DVC In" 100%
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*
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* You can use Mute
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*
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* amixer set "DVC Out Mute" on
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* amixer set "DVC In Mute" on
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*
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* You can use Volume Ramp
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*
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* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
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* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
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* amixer set "DVC Out Ramp" on
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* aplay xxx.wav &
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* amixer set "DVC Out" 80% // Volume Down
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* amixer set "DVC Out" 100% // Volume Up
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*/
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/dts-v1/;
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#include "r8a7790.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "Lager";
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compatible = "renesas,lager", "renesas,r8a7790";
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aliases {
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serial0 = &scif0;
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serial1 = &scifa1;
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i2c8 = &gpioi2c1;
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i2c10 = &i2cexio0;
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i2c11 = &i2cexio1;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
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stdout-path = "serial0:115200n8";
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x40000000>;
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};
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memory@140000000 {
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device_type = "memory";
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reg = <1 0x40000000 0 0xc0000000>;
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};
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lbsc {
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#address-cells = <1>;
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#size-cells = <1>;
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};
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keyboard {
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compatible = "gpio-keys";
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one {
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linux,code = <KEY_1>;
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label = "SW2-1";
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wakeup-source;
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debounce-interval = <20>;
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gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
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};
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two {
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linux,code = <KEY_2>;
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label = "SW2-2";
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wakeup-source;
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debounce-interval = <20>;
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gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
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};
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three {
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linux,code = <KEY_3>;
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label = "SW2-3";
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wakeup-source;
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debounce-interval = <20>;
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gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
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};
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four {
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linux,code = <KEY_4>;
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label = "SW2-4";
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wakeup-source;
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debounce-interval = <20>;
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gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led6 {
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gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
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};
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led7 {
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gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
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};
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led8 {
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gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
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};
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};
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fixedregulator3v3: regulator-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vcc_sdhi0: regulator-vcc-sdhi0 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI0 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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vccq_sdhi0: regulator-vccq-sdhi0 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI0 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1
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1800000 0>;
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};
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vcc_sdhi2: regulator-vcc-sdhi2 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI2 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio5 25 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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vccq_sdhi2: regulator-vccq-sdhi2 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI2 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1
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1800000 0>;
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};
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audio_clock: audio_clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <11289600>;
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};
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rsnd_ak4643: sound {
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compatible = "simple-audio-card";
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simple-audio-card,format = "left_j";
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simple-audio-card,bitclock-master = <&sndcodec>;
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simple-audio-card,frame-master = <&sndcodec>;
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sndcpu: simple-audio-card,cpu {
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sound-dai = <&rcar_sound>;
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};
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sndcodec: simple-audio-card,codec {
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sound-dai = <&ak4643>;
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clocks = <&audio_clock>;
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};
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};
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vga-encoder {
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compatible = "adi,adv7123";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7123_in: endpoint {
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remote-endpoint = <&du_out_rgb>;
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};
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};
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port@1 {
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reg = <1>;
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adv7123_out: endpoint {
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remote-endpoint = <&vga_in>;
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};
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};
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};
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};
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vga {
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compatible = "vga-connector";
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port {
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vga_in: endpoint {
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remote-endpoint = <&adv7123_out>;
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};
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};
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};
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hdmi-in {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con_in: endpoint {
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remote-endpoint = <&adv7612_in>;
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};
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};
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};
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hdmi-out {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con_out: endpoint {
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remote-endpoint = <&adv7511_out>;
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};
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};
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};
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x2_clk: x2-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <148500000>;
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};
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x13_clk: x13-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <148500000>;
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};
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gpioi2c1: i2c-8 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "i2c-gpio";
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status = "disabled";
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gpios = <&gpio1 17 GPIO_ACTIVE_HIGH /* sda */
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&gpio1 16 GPIO_ACTIVE_HIGH /* scl */
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>;
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i2c-gpio,delay-us = <5>;
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};
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/*
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* IIC0/I2C0 is routed to EXIO connector A, pins 114 (SCL) + 116 (SDA) only.
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* We use the I2C demuxer, so the desired IP core can be selected at runtime
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* depending on the use case (e.g. DMA with IIC0 or slave support with I2C0).
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* Note: For testing the I2C slave feature, it is convenient to connect this
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* bus with IIC3 on pins 110 (SCL) + 112 (SDA), select I2C0 at runtime, and
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* instantiate the slave device at runtime according to the documentation.
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* You can then communicate with the slave via IIC3.
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*
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* IIC0/I2C0 does not appear to support fallback to GPIO.
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*/
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i2cexio0: i2c-10 {
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compatible = "i2c-demux-pinctrl";
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i2c-parent = <&iic0>, <&i2c0>;
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i2c-bus-name = "i2c-exio0";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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/*
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* IIC1/I2C1 is routed to EXIO connector A, pins 78 (SCL) + 80 (SDA).
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* This is similar to the arangement described for i2cexio0 (above)
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* with a fallback to GPIO also provided.
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*/
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i2cexio1: i2c-11 {
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compatible = "i2c-demux-pinctrl";
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i2c-parent = <&iic1>, <&i2c1>, <&gpioi2c1>;
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i2c-bus-name = "i2c-exio1";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&du {
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pinctrl-0 = <&du_pins>;
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pinctrl-names = "default";
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status = "okay";
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clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
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<&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
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<&x13_clk>, <&x2_clk>;
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clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
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"dclkin.0", "dclkin.1";
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ports {
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port@0 {
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endpoint {
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remote-endpoint = <&adv7123_in>;
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};
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};
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port@1 {
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endpoint {
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remote-endpoint = <&adv7511_in>;
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};
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};
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port@2 {
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lvds_connector: endpoint {
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};
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};
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};
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};
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&extal_clk {
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clock-frequency = <20000000>;
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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du_pins: du {
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groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
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function = "du";
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};
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scif0_pins: scif0 {
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groups = "scif0_data";
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function = "scif0";
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};
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scif_clk_pins: scif_clk {
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groups = "scif_clk";
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function = "scif_clk";
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};
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ether_pins: ether {
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groups = "eth_link", "eth_mdio", "eth_rmii";
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function = "eth";
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};
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phy1_pins: phy1 {
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groups = "intc_irq0";
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function = "intc";
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};
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scifa1_pins: scifa1 {
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groups = "scifa1_data";
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function = "scifa1";
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};
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sdhi0_pins: sd0 {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <3300>;
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};
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sdhi0_pins_uhs: sd0_uhs {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <1800>;
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};
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sdhi2_pins: sd2 {
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groups = "sdhi2_data4", "sdhi2_ctrl";
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function = "sdhi2";
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power-source = <3300>;
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};
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sdhi2_pins_uhs: sd2_uhs {
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groups = "sdhi2_data4", "sdhi2_ctrl";
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function = "sdhi2";
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power-source = <1800>;
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};
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mmc1_pins: mmc1 {
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groups = "mmc1_data8", "mmc1_ctrl";
|
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function = "mmc1";
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};
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qspi_pins: qspi {
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groups = "qspi_ctrl", "qspi_data4";
|
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function = "qspi";
|
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};
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msiof1_pins: msiof1 {
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groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
|
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"msiof1_tx";
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function = "msiof1";
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
|
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function = "i2c0";
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};
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iic0_pins: iic0 {
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groups = "iic0";
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function = "iic0";
|
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};
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i2c1_pins: i2c1 {
|
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groups = "i2c1";
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function = "i2c1";
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};
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iic1_pins: iic1 {
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groups = "iic1";
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function = "iic1";
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};
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|
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iic2_pins: iic2 {
|
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groups = "iic2";
|
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function = "iic2";
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};
|
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iic3_pins: iic3 {
|
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groups = "iic3";
|
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function = "iic3";
|
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};
|
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|
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hsusb_pins: hsusb {
|
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groups = "usb0_ovc_vbus";
|
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function = "usb0";
|
||||
};
|
||||
|
||||
usb0_pins: usb0 {
|
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groups = "usb0";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
usb1_pins: usb1 {
|
||||
groups = "usb1";
|
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function = "usb1";
|
||||
};
|
||||
|
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usb2_pins: usb2 {
|
||||
groups = "usb2";
|
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function = "usb2";
|
||||
};
|
||||
|
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vin0_pins: vin0 {
|
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groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
|
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function = "vin0";
|
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};
|
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|
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vin1_pins: vin1 {
|
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groups = "vin1_data8", "vin1_clk";
|
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function = "vin1";
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
|
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function = "ssi";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clk_a";
|
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function = "audio_clk";
|
||||
};
|
||||
};
|
||||
|
||||
ðer {
|
||||
pinctrl-0 = <ðer_pins &phy1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy-handle = <&phy1>;
|
||||
renesas,ether-link-active-low;
|
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status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
micrel,led-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cmt0 {
|
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status = "okay";
|
||||
};
|
||||
|
||||
&mmcif1 {
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&fixedregulator3v3>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
flash: flash@0 {
|
||||
compatible = "spansion,s25fl512s", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <30000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "loader";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
read-only;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "user";
|
||||
reg = <0x00040000 0x00400000>;
|
||||
read-only;
|
||||
};
|
||||
partition@440000 {
|
||||
label = "flash";
|
||||
reg = <0x00440000 0x03bc0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&scif0 {
|
||||
pinctrl-0 = <&scif0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scifa1 {
|
||||
pinctrl-0 = <&scifa1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <14745600>;
|
||||
};
|
||||
|
||||
&msiof1 {
|
||||
pinctrl-0 = <&msiof1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
pmic: pmic@0 {
|
||||
compatible = "renesas,r2a11302ft";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <6000000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-1 = <&sdhi2_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi2>;
|
||||
vqmmc-supply = <&vccq_sdhi2>;
|
||||
cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
|
||||
sd-uhs-sdr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_dvfs>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "i2c-exio0";
|
||||
};
|
||||
|
||||
&iic0 {
|
||||
pinctrl-0 = <&iic0_pins>;
|
||||
pinctrl-names = "i2c-exio0";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "i2c-exio1";
|
||||
};
|
||||
|
||||
&iic1 {
|
||||
pinctrl-0 = <&iic1_pins>;
|
||||
pinctrl-names = "i2c-exio1";
|
||||
};
|
||||
|
||||
&iic2 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&iic2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
clock-frequency = <100000>;
|
||||
|
||||
ak4643: codec@12 {
|
||||
compatible = "asahi-kasei,ak4643";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180";
|
||||
reg = <0x20>;
|
||||
remote = <&vin1>;
|
||||
|
||||
port {
|
||||
adv7180: endpoint {
|
||||
bus-width = <8>;
|
||||
remote-endpoint = <&vin1ep0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&du_out_lvds0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in@4c {
|
||||
compatible = "adi,adv7612";
|
||||
reg = <0x4c>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
|
||||
default-input = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7612_in: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
adv7612_out: endpoint {
|
||||
remote-endpoint = <&vin0ep2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iic3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&iic3_pins>;
|
||||
status = "okay";
|
||||
|
||||
pmic@58 {
|
||||
compatible = "dlg,da9063";
|
||||
reg = <0x58>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
|
||||
rtc {
|
||||
compatible = "dlg,da9063-rtc";
|
||||
};
|
||||
|
||||
wdt {
|
||||
compatible = "dlg,da9063-watchdog";
|
||||
};
|
||||
};
|
||||
|
||||
vdd_dvfs: regulator@68 {
|
||||
compatible = "dlg,da9210";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&irqc0>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&pci0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pci1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&xhci {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb2_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&pci2 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&usb2_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&hsusb_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* HDMI video input */
|
||||
&vin0 {
|
||||
pinctrl-0 = <&vin0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
vin0ep2: endpoint {
|
||||
remote-endpoint = <&adv7612_out>;
|
||||
bus-width = <24>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
pclk-sample = <1>;
|
||||
data-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* composite video input */
|
||||
&vin1 {
|
||||
pinctrl-0 = <&vin1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vin1ep0: endpoint {
|
||||
remote-endpoint = <&adv7180>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src2 &dvc0>;
|
||||
capture = <&ssi1 &src3 &dvc1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
1665
arch/arm/dts/r8a7790.dtsi
Normal file
1665
arch/arm/dts/r8a7790.dtsi
Normal file
File diff suppressed because it is too large
Load diff
162
include/dt-bindings/clock/r8a7790-clock.h
Normal file
162
include/dt-bindings/clock/r8a7790-clock.h
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* Copyright 2013 Ideas On Board SPRL
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7790_H__
|
||||
|
||||
/* CPG */
|
||||
#define R8A7790_CLK_MAIN 0
|
||||
#define R8A7790_CLK_PLL0 1
|
||||
#define R8A7790_CLK_PLL1 2
|
||||
#define R8A7790_CLK_PLL3 3
|
||||
#define R8A7790_CLK_LB 4
|
||||
#define R8A7790_CLK_QSPI 5
|
||||
#define R8A7790_CLK_SDH 6
|
||||
#define R8A7790_CLK_SD0 7
|
||||
#define R8A7790_CLK_SD1 8
|
||||
#define R8A7790_CLK_Z 9
|
||||
#define R8A7790_CLK_RCAN 10
|
||||
#define R8A7790_CLK_ADSP 11
|
||||
|
||||
/* MSTP0 */
|
||||
#define R8A7790_CLK_MSIOF0 0
|
||||
|
||||
/* MSTP1 */
|
||||
#define R8A7790_CLK_VCP1 0
|
||||
#define R8A7790_CLK_VCP0 1
|
||||
#define R8A7790_CLK_VPC1 2
|
||||
#define R8A7790_CLK_VPC0 3
|
||||
#define R8A7790_CLK_JPU 6
|
||||
#define R8A7790_CLK_SSP1 9
|
||||
#define R8A7790_CLK_TMU1 11
|
||||
#define R8A7790_CLK_3DG 12
|
||||
#define R8A7790_CLK_2DDMAC 15
|
||||
#define R8A7790_CLK_FDP1_2 17
|
||||
#define R8A7790_CLK_FDP1_1 18
|
||||
#define R8A7790_CLK_FDP1_0 19
|
||||
#define R8A7790_CLK_TMU3 21
|
||||
#define R8A7790_CLK_TMU2 22
|
||||
#define R8A7790_CLK_CMT0 24
|
||||
#define R8A7790_CLK_TMU0 25
|
||||
#define R8A7790_CLK_VSP1_DU1 27
|
||||
#define R8A7790_CLK_VSP1_DU0 28
|
||||
#define R8A7790_CLK_VSP1_R 30
|
||||
#define R8A7790_CLK_VSP1_S 31
|
||||
|
||||
/* MSTP2 */
|
||||
#define R8A7790_CLK_SCIFA2 2
|
||||
#define R8A7790_CLK_SCIFA1 3
|
||||
#define R8A7790_CLK_SCIFA0 4
|
||||
#define R8A7790_CLK_MSIOF2 5
|
||||
#define R8A7790_CLK_SCIFB0 6
|
||||
#define R8A7790_CLK_SCIFB1 7
|
||||
#define R8A7790_CLK_MSIOF1 8
|
||||
#define R8A7790_CLK_MSIOF3 15
|
||||
#define R8A7790_CLK_SCIFB2 16
|
||||
#define R8A7790_CLK_SYS_DMAC1 18
|
||||
#define R8A7790_CLK_SYS_DMAC0 19
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A7790_CLK_IIC2 0
|
||||
#define R8A7790_CLK_TPU0 4
|
||||
#define R8A7790_CLK_MMCIF1 5
|
||||
#define R8A7790_CLK_SCIF2 10
|
||||
#define R8A7790_CLK_SDHI3 11
|
||||
#define R8A7790_CLK_SDHI2 12
|
||||
#define R8A7790_CLK_SDHI1 13
|
||||
#define R8A7790_CLK_SDHI0 14
|
||||
#define R8A7790_CLK_MMCIF0 15
|
||||
#define R8A7790_CLK_IIC0 18
|
||||
#define R8A7790_CLK_PCIEC 19
|
||||
#define R8A7790_CLK_IIC1 23
|
||||
#define R8A7790_CLK_SSUSB 28
|
||||
#define R8A7790_CLK_CMT1 29
|
||||
#define R8A7790_CLK_USBDMAC0 30
|
||||
#define R8A7790_CLK_USBDMAC1 31
|
||||
|
||||
/* MSTP4 */
|
||||
#define R8A7790_CLK_IRQC 7
|
||||
#define R8A7790_CLK_INTC_SYS 8
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A7790_CLK_AUDIO_DMAC1 1
|
||||
#define R8A7790_CLK_AUDIO_DMAC0 2
|
||||
#define R8A7790_CLK_ADSP_MOD 6
|
||||
#define R8A7790_CLK_THERMAL 22
|
||||
#define R8A7790_CLK_PWM 23
|
||||
|
||||
/* MSTP7 */
|
||||
#define R8A7790_CLK_EHCI 3
|
||||
#define R8A7790_CLK_HSUSB 4
|
||||
#define R8A7790_CLK_HSCIF1 16
|
||||
#define R8A7790_CLK_HSCIF0 17
|
||||
#define R8A7790_CLK_SCIF1 20
|
||||
#define R8A7790_CLK_SCIF0 21
|
||||
#define R8A7790_CLK_DU2 22
|
||||
#define R8A7790_CLK_DU1 23
|
||||
#define R8A7790_CLK_DU0 24
|
||||
#define R8A7790_CLK_LVDS1 25
|
||||
#define R8A7790_CLK_LVDS0 26
|
||||
|
||||
/* MSTP8 */
|
||||
#define R8A7790_CLK_MLB 2
|
||||
#define R8A7790_CLK_VIN3 8
|
||||
#define R8A7790_CLK_VIN2 9
|
||||
#define R8A7790_CLK_VIN1 10
|
||||
#define R8A7790_CLK_VIN0 11
|
||||
#define R8A7790_CLK_ETHERAVB 12
|
||||
#define R8A7790_CLK_ETHER 13
|
||||
#define R8A7790_CLK_SATA1 14
|
||||
#define R8A7790_CLK_SATA0 15
|
||||
|
||||
/* MSTP9 */
|
||||
#define R8A7790_CLK_GPIO5 7
|
||||
#define R8A7790_CLK_GPIO4 8
|
||||
#define R8A7790_CLK_GPIO3 9
|
||||
#define R8A7790_CLK_GPIO2 10
|
||||
#define R8A7790_CLK_GPIO1 11
|
||||
#define R8A7790_CLK_GPIO0 12
|
||||
#define R8A7790_CLK_RCAN1 15
|
||||
#define R8A7790_CLK_RCAN0 16
|
||||
#define R8A7790_CLK_QSPI_MOD 17
|
||||
#define R8A7790_CLK_IICDVFS 26
|
||||
#define R8A7790_CLK_I2C3 28
|
||||
#define R8A7790_CLK_I2C2 29
|
||||
#define R8A7790_CLK_I2C1 30
|
||||
#define R8A7790_CLK_I2C0 31
|
||||
|
||||
/* MSTP10 */
|
||||
#define R8A7790_CLK_SSI_ALL 5
|
||||
#define R8A7790_CLK_SSI9 6
|
||||
#define R8A7790_CLK_SSI8 7
|
||||
#define R8A7790_CLK_SSI7 8
|
||||
#define R8A7790_CLK_SSI6 9
|
||||
#define R8A7790_CLK_SSI5 10
|
||||
#define R8A7790_CLK_SSI4 11
|
||||
#define R8A7790_CLK_SSI3 12
|
||||
#define R8A7790_CLK_SSI2 13
|
||||
#define R8A7790_CLK_SSI1 14
|
||||
#define R8A7790_CLK_SSI0 15
|
||||
#define R8A7790_CLK_SCU_ALL 17
|
||||
#define R8A7790_CLK_SCU_DVC1 18
|
||||
#define R8A7790_CLK_SCU_DVC0 19
|
||||
#define R8A7790_CLK_SCU_CTU1_MIX1 20
|
||||
#define R8A7790_CLK_SCU_CTU0_MIX0 21
|
||||
#define R8A7790_CLK_SCU_SRC9 22
|
||||
#define R8A7790_CLK_SCU_SRC8 23
|
||||
#define R8A7790_CLK_SCU_SRC7 24
|
||||
#define R8A7790_CLK_SCU_SRC6 25
|
||||
#define R8A7790_CLK_SCU_SRC5 26
|
||||
#define R8A7790_CLK_SCU_SRC4 27
|
||||
#define R8A7790_CLK_SCU_SRC3 28
|
||||
#define R8A7790_CLK_SCU_SRC2 29
|
||||
#define R8A7790_CLK_SCU_SRC1 30
|
||||
#define R8A7790_CLK_SCU_SRC0 31
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
|
||||
52
include/dt-bindings/clock/r8a7790-cpg-mssr.h
Normal file
52
include/dt-bindings/clock/r8a7790-cpg-mssr.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a7790 CPG Core Clocks */
|
||||
#define R8A7790_CLK_Z 0
|
||||
#define R8A7790_CLK_Z2 1
|
||||
#define R8A7790_CLK_ZG 2
|
||||
#define R8A7790_CLK_ZTR 3
|
||||
#define R8A7790_CLK_ZTRD2 4
|
||||
#define R8A7790_CLK_ZT 5
|
||||
#define R8A7790_CLK_ZX 6
|
||||
#define R8A7790_CLK_ZS 7
|
||||
#define R8A7790_CLK_HP 8
|
||||
#define R8A7790_CLK_I 9
|
||||
#define R8A7790_CLK_B 10
|
||||
#define R8A7790_CLK_LB 11
|
||||
#define R8A7790_CLK_P 12
|
||||
#define R8A7790_CLK_CL 13
|
||||
#define R8A7790_CLK_M2 14
|
||||
#define R8A7790_CLK_ADSP 15
|
||||
#define R8A7790_CLK_IMP 16
|
||||
#define R8A7790_CLK_ZB3 17
|
||||
#define R8A7790_CLK_ZB3D2 18
|
||||
#define R8A7790_CLK_DDR 19
|
||||
#define R8A7790_CLK_SDH 20
|
||||
#define R8A7790_CLK_SD0 21
|
||||
#define R8A7790_CLK_SD1 22
|
||||
#define R8A7790_CLK_SD2 23
|
||||
#define R8A7790_CLK_SD3 24
|
||||
#define R8A7790_CLK_MMC0 25
|
||||
#define R8A7790_CLK_MMC1 26
|
||||
#define R8A7790_CLK_MP 27
|
||||
#define R8A7790_CLK_SSP 28
|
||||
#define R8A7790_CLK_SSPRS 29
|
||||
#define R8A7790_CLK_QSPI 30
|
||||
#define R8A7790_CLK_CP 31
|
||||
#define R8A7790_CLK_RCAN 32
|
||||
#define R8A7790_CLK_R 33
|
||||
#define R8A7790_CLK_OSC 34
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
|
||||
34
include/dt-bindings/power/r8a7790-sysc.h
Normal file
34
include/dt-bindings/power/r8a7790-sysc.h
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A7790_PD_CA15_CPU0 0
|
||||
#define R8A7790_PD_CA15_CPU1 1
|
||||
#define R8A7790_PD_CA15_CPU2 2
|
||||
#define R8A7790_PD_CA15_CPU3 3
|
||||
#define R8A7790_PD_CA7_CPU0 5
|
||||
#define R8A7790_PD_CA7_CPU1 6
|
||||
#define R8A7790_PD_CA7_CPU2 7
|
||||
#define R8A7790_PD_CA7_CPU3 8
|
||||
#define R8A7790_PD_CA15_SCU 12
|
||||
#define R8A7790_PD_SH_4A 16
|
||||
#define R8A7790_PD_RGX 20
|
||||
#define R8A7790_PD_CA7_SCU 21
|
||||
#define R8A7790_PD_IMP 24
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A7790_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */
|
||||
Loading…
Add table
Reference in a new issue