mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-21 22:51:37 +00:00
Merge git://git.denx.de/u-boot-fsl-qoriq
- Support of NXP's LX2160RDB and LX2160QDS platform - Enable SATA DM model for NXP's ARM SoCs
This commit is contained in:
Tom Rini
commit
176b32cd4f
99 changed files with 3140 additions and 33 deletions
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@ -1083,6 +1083,32 @@ config TARGET_LS2081ARDB
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development platform that supports the QorIQ LS2081A/LS2041A
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Layerscape Architecture processor.
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config TARGET_LX2160ARDB
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bool "Support lx2160ardb"
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select ARCH_LX2160A
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select ARCH_MISC_INIT
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select ARM64
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select ARMV8_MULTIENTRY
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select BOARD_LATE_INIT
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help
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Support for NXP LX2160ARDB platform.
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The lx2160ardb (LX2160A Reference design board (RDB)
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is a high-performance development platform that supports the
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QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
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config TARGET_LX2160AQDS
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bool "Support lx2160aqds"
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select ARCH_LX2160A
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select ARCH_MISC_INIT
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select ARM64
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select ARMV8_MULTIENTRY
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select BOARD_LATE_INIT
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help
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Support for NXP LX2160AQDS platform.
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The lx2160aqds (LX2160A QorIQ Development System (QDS)
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is a high-performance development platform that supports the
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QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
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config TARGET_HIKEY
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bool "Support HiKey 96boards Consumer Edition Platform"
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select ARM64
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@ -1237,6 +1263,7 @@ config TARGET_LS1043AQDS
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select BOARD_LATE_INIT
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select SUPPORT_SPL
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imply SCSI
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imply SCSI_AHCI
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help
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Support for Freescale LS1043AQDS platform.
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@ -1248,7 +1275,6 @@ config TARGET_LS1043ARDB
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select BOARD_EARLY_INIT_F
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select BOARD_LATE_INIT
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select SUPPORT_SPL
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imply SCSI
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help
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Support for Freescale LS1043ARDB platform.
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@ -1555,6 +1581,7 @@ source "board/freescale/ls1046ardb/Kconfig"
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source "board/freescale/ls1012aqds/Kconfig"
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source "board/freescale/ls1012ardb/Kconfig"
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source "board/freescale/ls1012afrdm/Kconfig"
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source "board/freescale/lx2160a/Kconfig"
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source "board/freescale/mx35pdk/Kconfig"
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source "board/freescale/s32v234evb/Kconfig"
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source "board/grinn/chiliboard/Kconfig"
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@ -106,7 +106,8 @@ config PSCI_RESET
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!TARGET_LS1012AFRWY && \
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!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
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!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
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!TARGET_LS2081ARDB && \
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!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
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!TARGET_LX2160AQDS && \
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!ARCH_UNIPHIER && !TARGET_S32V234EVB
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help
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Most armv8 systems have PSCI support enabled in EL3, either through
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@ -2,6 +2,7 @@ config ARCH_LS1012A
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bool
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select ARMV8_SET_SMPEN
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select ARM_ERRATA_855873 if !TFABOOT
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select FSL_LAYERSCAPE
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select FSL_LSCH2
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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@ -23,6 +24,7 @@ config ARCH_LS1043A
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bool
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select ARMV8_SET_SMPEN
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select ARM_ERRATA_855873 if !TFABOOT
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select FSL_LAYERSCAPE
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select FSL_LSCH2
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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@ -49,13 +51,12 @@ config ARCH_LS1043A
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select SYS_I2C_MXC_I2C2
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select SYS_I2C_MXC_I2C3
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select SYS_I2C_MXC_I2C4
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imply SCSI
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imply SCSI_AHCI
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imply CMD_PCI
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config ARCH_LS1046A
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bool
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select ARMV8_SET_SMPEN
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select FSL_LAYERSCAPE
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select FSL_LSCH2
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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@ -90,6 +91,7 @@ config ARCH_LS1088A
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bool
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select ARMV8_SET_SMPEN
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select ARM_ERRATA_855873 if !TFABOOT
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select FSL_LAYERSCAPE
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select FSL_LSCH3
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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@ -113,6 +115,8 @@ config ARCH_LS1088A
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select SYS_FSL_SRDS_1
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select SYS_FSL_SRDS_2
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select FSL_TZASC_1
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select FSL_TZASC_400
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select FSL_TZPC_BP147
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select ARCH_EARLY_INIT_R
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select BOARD_EARLY_INIT_F
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select SYS_I2C_MXC
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@ -130,6 +134,7 @@ config ARCH_LS2080A
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select ARM_ERRATA_828024
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select ARM_ERRATA_829520
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select ARM_ERRATA_833471
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select FSL_LAYERSCAPE
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select FSL_LSCH3
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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@ -145,6 +150,8 @@ config ARCH_LS2080A
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select SYS_FSL_SRDS_2
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select FSL_TZASC_1
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select FSL_TZASC_2
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select FSL_TZASC_400
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select FSL_TZPC_BP147
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select SYS_FSL_ERRATUM_A008336 if !TFABOOT
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select SYS_FSL_ERRATUM_A008511 if !TFABOOT
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select SYS_FSL_ERRATUM_A008514 if !TFABOOT
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@ -230,6 +237,9 @@ config FSL_MC_ENET
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menu "Layerscape architecture"
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depends on FSL_LSCH2 || FSL_LSCH3
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config FSL_LAYERSCAPE
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bool
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config FSL_PCIE_COMPAT
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string "PCIe compatible of Kernel DT"
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depends on PCIE_LAYERSCAPE
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@ -346,6 +356,12 @@ config MAX_CPUS
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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config EMC2305
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bool "Fan controller"
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help
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Enable the EMC2305 fan controller for configuration of fan
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speed.
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config SECURE_BOOT
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bool "Secure Boot"
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help
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@ -404,6 +420,11 @@ config FSL_TZASC_1
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config FSL_TZASC_2
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bool
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config FSL_TZASC_400
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bool
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config FSL_TZPC_BP147
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bool
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endmenu
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menu "Layerscape clock tree configuration"
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@ -1099,15 +1099,29 @@ int arch_early_init_r(void)
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printf("Did not wake secondary cores\n");
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}
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#ifdef CONFIG_SYS_FSL_HAS_RGMII
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fsl_rgmii_init();
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#endif
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config_core_prefetch();
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#ifdef CONFIG_SYS_HAS_SERDES
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fsl_serdes_init();
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#endif
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#ifdef CONFIG_SYS_FSL_HAS_RGMII
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/* some dpmacs in armv8a based freescale layerscape SOCs can be
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* configured via both serdes(sgmii, xfi, xlaui etc) bits and via
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* EC*_PMUX(rgmii) bits in RCW.
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* e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
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* serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
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* Now if a dpmac is enabled by serdes bits then it takes precedence
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* over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
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* that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
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* then the dpmac is SGMII and not RGMII.
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*
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* Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
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* fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
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* or not? if it is (fsl_serdes_init has already enabled the dpmac),
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* then don't enable it.
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*/
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fsl_rgmii_init();
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#endif
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#ifdef CONFIG_FMAN_ENET
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fman_enet_init();
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#endif
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@ -548,12 +548,32 @@ void fsl_serdes_init(void)
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#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
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int i , j;
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#ifdef CONFIG_ARCH_LX2160A
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for (i = XFI1, j = 1; i <= XFI14; i++, j++)
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xfi_dpmac[i] = j;
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for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
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sgmii_dpmac[i] = j;
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for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
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a25gaui_dpmac[i] = j;
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for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
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xlaui_dpmac[i] = j;
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for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
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caui2_dpmac[i] = j;
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for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
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caui4_dpmac[i] = j;
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#else
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for (i = XFI1, j = 1; i <= XFI8; i++, j++)
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xfi_dpmac[i] = j;
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for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
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sgmii_dpmac[i] = j;
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#endif
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_1
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serdes_init(FSL_SRDS_1,
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@ -246,7 +246,9 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
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fsl-ls2081a-rdb.dtb \
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fsl-ls2088a-rdb-qspi.dtb \
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fsl-ls1088a-rdb.dtb \
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fsl-ls1088a-qds.dtb
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fsl-ls1088a-qds.dtb \
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fsl-lx2160a-rdb.dtb \
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fsl-lx2160a-qds.dtb
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dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
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fsl-ls1043a-qds-lpuart.dtb \
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fsl-ls1043a-rdb.dtb \
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17
arch/arm/dts/fsl-lx2160a-qds.dts
Normal file
17
arch/arm/dts/fsl-lx2160a-qds.dts
Normal file
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@ -0,0 +1,17 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source
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*
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* Copyright 2018-2019 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-lx2160a.dtsi"
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/ {
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model = "NXP Layerscape LX2160AQDS Board";
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compatible = "fsl,lx2160aqds", "fsl,lx2160a";
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};
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44
arch/arm/dts/fsl-lx2160a-rdb.dts
Normal file
44
arch/arm/dts/fsl-lx2160a-rdb.dts
Normal file
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@ -0,0 +1,44 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160ARDB device tree source
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*
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* Author: Priyanka Jain <priyanka.jain@nxp.com>
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* Sriram Dash <sriram.dash@nxp.com>
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*
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* Copyright 2018 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-lx2160a.dtsi"
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/ {
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model = "NXP Layerscape LX2160ARDB Board";
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compatible = "fsl,lx2160ardb", "fsl,lx2160a";
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};
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&esdhc0 {
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status = "okay";
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};
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&esdhc1 {
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status = "okay";
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};
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&sata0 {
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status = "okay";
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};
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&sata1 {
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status = "okay";
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};
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&sata2 {
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status = "okay";
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};
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&sata3 {
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status = "okay";
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};
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@ -89,7 +89,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2110000 0x0 0x10000>;
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interrupts = <0 240 0x4>; /* Level high type */
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interrupts = <0 26 0x4>; /* Level high type */
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num-cs = <6>;
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};
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@ -115,4 +115,65 @@
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interrupts = <0 81 0x4>; /* Level high type */
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dr_mode = "host";
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};
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esdhc0: esdhc@2140000 {
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compatible = "fsl,esdhc";
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reg = <0x0 0x2140000 0x0 0x10000>;
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interrupts = <0 28 0x4>; /* Level high type */
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clocks = <&clockgen 4 1>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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little-endian;
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bus-width = <4>;
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status = "disabled";
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};
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esdhc1: esdhc@2150000 {
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compatible = "fsl,esdhc";
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reg = <0x0 0x2150000 0x0 0x10000>;
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interrupts = <0 63 0x4>; /* Level high type */
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clocks = <&clockgen 4 1>;
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voltage-ranges = <1800 1800 3300 3300>;
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sdhci,auto-cmd12;
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non-removable;
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little-endian;
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bus-width = <4>;
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status = "disabled";
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};
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sata0: sata@3200000 {
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compatible = "fsl,ls2080a-ahci";
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reg = <0x0 0x3200000 0x0 0x10000>;
|
||||
interrupts = <0 133 4>;
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clocks = <&clockgen 4 3>;
|
||||
status = "disabled";
|
||||
|
||||
};
|
||||
|
||||
sata1: sata@3210000 {
|
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compatible = "fsl,ls2080a-ahci";
|
||||
reg = <0x0 0x3210000 0x0 0x10000>;
|
||||
interrupts = <0 136 4>;
|
||||
clocks = <&clockgen 4 3>;
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status = "disabled";
|
||||
|
||||
};
|
||||
|
||||
sata2: sata@3220000 {
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compatible = "fsl,ls2080a-ahci";
|
||||
reg = <0x0 0x3220000 0x0 0x10000>;
|
||||
interrupts = <0 97 4>;
|
||||
clocks = <&clockgen 4 3>;
|
||||
status = "disabled";
|
||||
|
||||
};
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||||
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||||
sata3: sata@3230000 {
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||||
compatible = "fsl,ls2080a-ahci";
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reg = <0x0 0x3230000 0x0 0x10000>;
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||||
interrupts = <0 100 4>;
|
||||
clocks = <&clockgen 4 3>;
|
||||
status = "disabled";
|
||||
|
||||
};
|
||||
};
|
||||
|
|
|
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|
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@ -26,7 +26,6 @@
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|||
#ifndef L1_CACHE_BYTES
|
||||
#define L1_CACHE_SHIFT 6
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||||
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
|
||||
#define CONFIG_FSL_TZASC_400
|
||||
#endif
|
||||
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||||
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
||||
|
|
@ -121,8 +120,6 @@
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|||
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
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||||
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
|
||||
#define CONFIG_GICV3
|
||||
#define CONFIG_FSL_TZPC_BP147
|
||||
#define CONFIG_FSL_TZASC_400
|
||||
#define CONFIG_SYS_PAGE_SIZE 0x10000
|
||||
|
||||
#define SRDS_MAX_LANES 4
|
||||
|
|
|
|||
|
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@ -42,7 +42,11 @@
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|||
#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
|
||||
#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
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||||
#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
|
||||
#ifndef CONFIG_ARCH_LX2160A
|
||||
#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
|
||||
#else
|
||||
#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000
|
||||
#endif
|
||||
#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
|
||||
#ifdef CONFIG_NXP_LSCH3_2
|
||||
#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* LayerScape Internal Memory Map
|
||||
*
|
||||
* Copyright 2017-2018 NXP
|
||||
* Copyright 2017-2019 NXP
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
|
|
@ -350,6 +350,14 @@ struct ccsr_gur {
|
|||
#define FSL_CHASSIS3_SRDS1_REGSR 29
|
||||
#define FSL_CHASSIS3_SRDS2_REGSR 29
|
||||
#define FSL_CHASSIS3_SRDS3_REGSR 29
|
||||
#define FSL_CHASSIS3_RCWSR12_REGSR 12
|
||||
#define FSL_CHASSIS3_RCWSR13_REGSR 13
|
||||
#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000
|
||||
#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
|
||||
#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038
|
||||
#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
|
||||
#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00
|
||||
#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9
|
||||
#elif defined(CONFIG_ARCH_LS1088A)
|
||||
#define FSL_CHASSIS3_EC1_REGSR 26
|
||||
#define FSL_CHASSIS3_EC2_REGSR 26
|
||||
|
|
|
|||
|
|
@ -85,6 +85,7 @@ relocate_done:
|
|||
isb sy
|
||||
4: ldp x0, x1, [sp, #16]
|
||||
bl __asm_flush_dcache_range
|
||||
bl __asm_flush_l3_dcache
|
||||
5: ldp x29, x30, [sp],#32
|
||||
ret
|
||||
ENDPROC(relocate_code)
|
||||
|
|
|
|||
|
|
@ -64,6 +64,8 @@ obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
|
|||
|
||||
obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
|
||||
|
||||
obj-$(CONFIG_EMC2305) += emc2305.o
|
||||
|
||||
# deal with common files for P-series corenet based devices
|
||||
obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/
|
||||
obj-$(CONFIG_TARGET_P3041DS) += p_corenet/
|
||||
|
|
|
|||
41
board/freescale/common/emc2305.c
Normal file
41
board/freescale/common/emc2305.c
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include "emc2305.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void set_fan_speed(u8 data)
|
||||
{
|
||||
u8 index;
|
||||
u8 Fan[NUM_OF_FANS] = {I2C_EMC2305_FAN1,
|
||||
I2C_EMC2305_FAN2,
|
||||
I2C_EMC2305_FAN3,
|
||||
I2C_EMC2305_FAN4,
|
||||
I2C_EMC2305_FAN5};
|
||||
|
||||
for (index = 0; index < NUM_OF_FANS; index++) {
|
||||
if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, &data, 1) != 0) {
|
||||
printf("Error: failed to change fan speed @%x\n",
|
||||
Fan[index]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void emc2305_init(void)
|
||||
{
|
||||
u8 data;
|
||||
|
||||
data = I2C_EMC2305_CMD;
|
||||
if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, &data, 1) != 0)
|
||||
printf("Error: failed to configure EMC2305\n");
|
||||
}
|
||||
23
board/freescale/common/emc2305.h
Normal file
23
board/freescale/common/emc2305.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __EMC2305_H_
|
||||
#define __EMC2305_H_
|
||||
|
||||
#define I2C_EMC2305_CONF 0x20
|
||||
#define I2C_EMC2305_FAN1 0x30
|
||||
#define I2C_EMC2305_FAN2 0x40
|
||||
#define I2C_EMC2305_FAN3 0x50
|
||||
#define I2C_EMC2305_FAN4 0x60
|
||||
#define I2C_EMC2305_FAN5 0x70
|
||||
|
||||
#define NUM_OF_FANS 5
|
||||
|
||||
void emc2305_init(void);
|
||||
void set_fan_speed(u8 data);
|
||||
|
||||
#endif /* __EMC2305_H_ */
|
||||
|
|
@ -227,8 +227,12 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
|
|||
#ifdef QIXIS_LBMAP_SD
|
||||
QIXIS_WRITE(rst_ctl, 0x30);
|
||||
QIXIS_WRITE(rcfg_ctl, 0);
|
||||
#ifdef NON_EXTENDED_DUTCFG
|
||||
QIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_SD);
|
||||
#else
|
||||
set_lbmap(QIXIS_LBMAP_SD);
|
||||
set_rcw_src(QIXIS_RCW_SRC_SD);
|
||||
#endif
|
||||
QIXIS_WRITE(rcfg_ctl, 0x20);
|
||||
QIXIS_WRITE(rcfg_ctl, 0x21);
|
||||
#else
|
||||
|
|
|
|||
34
board/freescale/lx2160a/Kconfig
Normal file
34
board/freescale/lx2160a/Kconfig
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
if TARGET_LX2160ARDB
|
||||
|
||||
config SYS_BOARD
|
||||
default "lx2160a"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_SOC
|
||||
default "fsl-layerscape"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "lx2160ardb"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
endif
|
||||
|
||||
if TARGET_LX2160AQDS
|
||||
|
||||
config SYS_BOARD
|
||||
default "lx2160a"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_SOC
|
||||
default "fsl-layerscape"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "lx2160aqds"
|
||||
|
||||
source "board/freescale/common/Kconfig"
|
||||
endif
|
||||
|
||||
26
board/freescale/lx2160a/MAINTAINERS
Normal file
26
board/freescale/lx2160a/MAINTAINERS
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
LX2160ARDB BOARD
|
||||
M: Priyanka Jain <priyanka.jain@nxp.com>
|
||||
S: Maintained
|
||||
F: board/freescale/lx2160a/
|
||||
F: include/configs/lx2160a_common.h
|
||||
F: include/configs/lx2160ardb.h
|
||||
F: configs/lx2160ardb_tfa_defconfig
|
||||
F: arch/arm/dts/fsl-lx2160a-rdb.dts
|
||||
|
||||
LX2160ARDB_SECURE_BOOT BOARD
|
||||
M: Udit Agarwal <udit.agarwal@nxp.com>
|
||||
S: Maintained
|
||||
F: configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
|
||||
|
||||
LX2160AQDS BOARD
|
||||
M: Pankaj Bansal <pankaj.bansal@nxp.com>
|
||||
S: Maintained
|
||||
F: board/freescale/lx2160a/eth_lx2160aqds.h
|
||||
F: include/configs/lx2160aqds.h
|
||||
F: configs/lx2160aqds_tfa_defconfig
|
||||
F: arch/arm/dts/fsl-lx2160a-qds.dts
|
||||
|
||||
LX2160AQDS_SECURE_BOOT BOARD
|
||||
M: Udit Agarwal <udit.agarwal@nxp.com>
|
||||
S: Maintained
|
||||
F: configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
|
||||
10
board/freescale/lx2160a/Makefile
Normal file
10
board/freescale/lx2160a/Makefile
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
#
|
||||
# Copyright 2018 Freescale Semiconductor
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += lx2160a.o
|
||||
obj-y += ddr.o
|
||||
obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o
|
||||
obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o
|
||||
197
board/freescale/lx2160a/README
Normal file
197
board/freescale/lx2160a/README
Normal file
|
|
@ -0,0 +1,197 @@
|
|||
Overview
|
||||
--------
|
||||
The LX2160A Reference Design (RDB) is a high-performance computing,
|
||||
evaluation, and development platform that supports the QorIQ LX2160A
|
||||
Layerscape Architecture processor and its personalities.
|
||||
|
||||
LX2160A SoC Overview
|
||||
--------------------------------------
|
||||
For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
|
||||
|
||||
LX2160ARDB board Overview
|
||||
----------------------
|
||||
DDR Memory
|
||||
Two ports of 72-bits (8-bits ECC) DDR4.
|
||||
Each port supports four chip-selects and two DIMM
|
||||
connectors. Data rate upto 3.2 GT/s.
|
||||
|
||||
SERDES ports
|
||||
Thress serdes controllers (24 lanes)
|
||||
Serdes1: Supports two USXGMII connectors, each connected through
|
||||
Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi
|
||||
IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi
|
||||
CS4223 phy.
|
||||
|
||||
Serdes2: Supports one PCIe x4 (Gen1/2/3/4) connector, four SATA 3.0
|
||||
connectors
|
||||
|
||||
Serdes3: Supports one PCIe x8 (Gen1/2/3/4) connector
|
||||
|
||||
eSDHC
|
||||
eSDHC1: Supports a SD connector for connecting SD cards
|
||||
eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC
|
||||
|
||||
Octal SPI (XSPI)
|
||||
Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator
|
||||
for off-board emulation
|
||||
|
||||
I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer
|
||||
Serial Ports
|
||||
|
||||
USB 3.0
|
||||
Two high speed USB 3.0 ports. First USB 3.0 port configured as
|
||||
Host with Type-A connector, second USB 3.0 port configured as OTG
|
||||
with micro-AB connector
|
||||
|
||||
Serial Ports Two UART ports
|
||||
Ethernet Two RGMII interfaces
|
||||
Debug ARM JTAG support
|
||||
|
||||
Booting Options
|
||||
---------------
|
||||
a) Flexspi boot
|
||||
b) SD boot
|
||||
|
||||
Memory map for Flexspi flash
|
||||
----------------------------
|
||||
Image Flash Offset
|
||||
bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000
|
||||
fip.bin (bl31 + bl33(u-boot) +
|
||||
header for Secure-boot(secure-boot only)) 0x00100000
|
||||
Boot firmware Environment 0x00500000
|
||||
DDR PHY Firmware (fip_ddr_all.bin) 0x00800000
|
||||
DPAA2 MC Firmware 0x00A00000
|
||||
DPAA2 DPL 0x00D00000
|
||||
DPAA2 DPC 0x00E00000
|
||||
Kernel.itb 0x01000000
|
||||
|
||||
Memory map for sd card
|
||||
----------------------------
|
||||
Image SD card Offset
|
||||
bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008
|
||||
fip.bin (bl31 + bl33(u-boot) +
|
||||
header for Secure-boot(secure-boot only)) 0x00800
|
||||
Boot firmware Environment 0x02800
|
||||
DDR PHY Firmware (fip_ddr_all.bin) 0x04000
|
||||
DPAA2 MC Firmware 0x05000
|
||||
DPAA2 DPL 0x06800
|
||||
DPAA2 DPC 0x07000
|
||||
Kernel.itb 0x08000
|
||||
|
||||
LX2160AQDS board Overview
|
||||
----------------------
|
||||
Various Mezzanine cards and their connection for different SERDES protocols is
|
||||
as below:
|
||||
|
||||
SERDES1 |CARDS
|
||||
-----------------------------------------------------------------------
|
||||
1 |Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
|
||||
|Connect I/O cable to IO_SLOT1(J110)
|
||||
|Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
|
||||
|Connect I/O cable to IO_SLOT2(J113)
|
||||
------------------------------------------------------------------------
|
||||
3 |Mezzanine:X-M11-USXGMII (29828)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
|
||||
|Connect I/O cable to IO_SLOT1(J110)
|
||||
|Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
|
||||
|Connect I/O cable to IO_SLOT2(J113)
|
||||
------------------------------------------------------------------------
|
||||
7 |Mezzanine:X-M11-USXGMII (29828)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
|
||||
|Connect I/O cable to IO_SLOT1(J110)
|
||||
|Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
|
||||
|Connect I/O cable to IO_SLOT2(J113)
|
||||
------------------------------------------------------------------------
|
||||
8 |Mezzanine:X-M12-XFI (29829)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
|
||||
|Connect I/O cable to IO_SLOT1(J110)
|
||||
|Mezzanine:X-M12-XFI (29829)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
|
||||
|Connect I/O cable to IO_SLOT2(J113)
|
||||
------------------------------------------------------------------------
|
||||
13 |Mezzanine:X-M8-100G (29734)
|
||||
|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
|
||||
|Connect I/O cable to IO_SLOT1(J110)
|
||||
|Mezzanine:X-M8-100G (29734)
|
||||
|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT2(J111)
|
||||
|Connect I/O cable to IO_SLOT2(J113)
|
||||
------------------------------------------------------------------------
|
||||
15 |Mezzanine:X-M8-100G (29734)
|
||||
|Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
|
||||
|Connect I/O cable to IO_SLOT1(J110)
|
||||
|Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
|
||||
|Connect I/O cable to IO_SLOT2(J113)
|
||||
------------------------------------------------------------------------
|
||||
17 |Mezzanine:X-M13-25G (32133)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
|
||||
|Connect I/O cable to IO_SLOT1(J110)
|
||||
|Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
|
||||
|Connect I/O cable to IO_SLOT2(J113)
|
||||
------------------------------------------------------------------------
|
||||
19 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
|
||||
|Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125)
|
||||
|Mezzanine:X-M7-40G (29738)
|
||||
|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111)
|
||||
|Connect I/O cable to IO_SLOT2(J113)
|
||||
------------------------------------------------------------------------
|
||||
20 |Mezzanine:X-M7-40G (29738)
|
||||
|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
|
||||
|Connect I/O cable to IO_SLOT1(J108)
|
||||
|Mezzanine:X-M7-40G (29738)
|
||||
|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111)
|
||||
|Connect I/O cable to IO_SLOT2(J113)
|
||||
------------------------------------------------------------------------
|
||||
|
||||
|
||||
SERDES2 |CARDS
|
||||
-----------------------------------------------------------------------
|
||||
2 |Mezzanine:X-M6-PCIE-X8 (29737) *
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
|
||||
|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117)
|
||||
|Connect I/O cable to IO_SLOT3(J116)
|
||||
------------------------------------------------------------------------
|
||||
3 |Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
|
||||
|Connect I/O cable to IO_SLOT3(J116)
|
||||
|Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
|
||||
|Connect I/O cable to IO_SLOT4(J119)
|
||||
------------------------------------------------------------------------
|
||||
5 |Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
|
||||
|Connect I/O cable to IO_SLOT3(J116)
|
||||
|Mezzanine:X-M5-SATA (29687)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
|
||||
|Connect I/O cable to IO_SLOT4(J119)
|
||||
------------------------------------------------------------------------
|
||||
11 |Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
|
||||
|Connect I/O cable to IO_SLOT7(J127)
|
||||
|Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
|
||||
|Connect I/O cable to IO_SLOT8(J131)
|
||||
------------------------------------------------------------------------
|
||||
|
||||
|
||||
SERDES3 |CARDS
|
||||
-----------------------------------------------------------------------
|
||||
2 |Mezzanine:X-M6-PCIE-X8 (29737) *
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120)
|
||||
|Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT6 (J123)
|
||||
|Connect I/O cable to IO_SLOT5(J122)
|
||||
-------------------------------------------------------------------------
|
||||
3 |Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120)
|
||||
|Connect I/O cable to IO_SLOT5(J122)
|
||||
|Mezzanine:X-M4-PCIE-SGMII (29733)
|
||||
|Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT6 (J123)
|
||||
|Connect I/O cable to IO_SLOT6(J125)
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
20
board/freescale/lx2160a/ddr.c
Normal file
20
board/freescale/lx2160a/ddr.c
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <fsl_ddr_sdram.h>
|
||||
#include <fsl_ddr_dimm_params.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int fsl_initdram(void)
|
||||
{
|
||||
gd->ram_size = tfa_get_dram_size();
|
||||
|
||||
if (!gd->ram_size)
|
||||
gd->ram_size = fsl_ddr_sdram_size();
|
||||
|
||||
return 0;
|
||||
}
|
||||
805
board/freescale/lx2160a/eth_lx2160aqds.c
Normal file
805
board/freescale/lx2160a/eth_lx2160aqds.c
Normal file
|
|
@ -0,0 +1,805 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <hwconfig.h>
|
||||
#include <command.h>
|
||||
#include <netdev.h>
|
||||
#include <malloc.h>
|
||||
#include <fsl_mdio.h>
|
||||
#include <miiphy.h>
|
||||
#include <phy.h>
|
||||
#include <fm_eth.h>
|
||||
#include <asm/io.h>
|
||||
#include <exports.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <fsl-mc/fsl_mc.h>
|
||||
#include <fsl-mc/ldpaa_wriop.h>
|
||||
|
||||
#include "../common/qixis.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define EMI_NONE 0
|
||||
#define EMI1 1 /* Mdio Bus 1 */
|
||||
#define EMI2 2 /* Mdio Bus 2 */
|
||||
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
enum io_slot {
|
||||
IO_SLOT_NONE = 0,
|
||||
IO_SLOT_1,
|
||||
IO_SLOT_2,
|
||||
IO_SLOT_3,
|
||||
IO_SLOT_4,
|
||||
IO_SLOT_5,
|
||||
IO_SLOT_6,
|
||||
IO_SLOT_7,
|
||||
IO_SLOT_8,
|
||||
EMI1_RGMII1,
|
||||
EMI1_RGMII2,
|
||||
IO_SLOT_MAX
|
||||
};
|
||||
|
||||
struct lx2160a_qds_mdio {
|
||||
enum io_slot ioslot : 4;
|
||||
u8 realbusnum : 4;
|
||||
struct mii_dev *realbus;
|
||||
};
|
||||
|
||||
/* structure explaining the phy configuration on 8 lanes of a serdes*/
|
||||
struct serdes_phy_config {
|
||||
u8 serdes; /* serdes protocol */
|
||||
struct phy_config {
|
||||
u8 dpmacid;
|
||||
/* -1 terminated array */
|
||||
int phy_address[WRIOP_MAX_PHY_NUM + 1];
|
||||
u8 mdio_bus;
|
||||
enum io_slot ioslot;
|
||||
} phy_config[SRDS_MAX_LANES];
|
||||
};
|
||||
|
||||
/* Table defining the phy configuration on 8 lanes of a serdes.
|
||||
* Various assumptions have been made while defining this table.
|
||||
* e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
|
||||
* card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
|
||||
* And also that this card is connected to IO Slot 1 (could have been connected
|
||||
* to any of the 8 IO slots (IO slot 1 - IO slot 8)).
|
||||
* similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
|
||||
* used in serdes1 protocol 19 (could have selected MDIO 2)
|
||||
* To override these settings "dpmac" environment variable can be used after
|
||||
* defining "dpmac_override" in hwconfig environment variable.
|
||||
* This table has limited serdes protocol entries. It can be expanded as per
|
||||
* requirement.
|
||||
*/
|
||||
static const struct serdes_phy_config serdes1_phy_config[] = {
|
||||
{3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
|
||||
EMI1, IO_SLOT_1} } },
|
||||
{7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_2},
|
||||
{WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_2},
|
||||
{WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_2},
|
||||
{WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_2} } },
|
||||
{8, {} },
|
||||
{13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_2} } },
|
||||
{15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1} } },
|
||||
{17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1} } },
|
||||
{19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
|
||||
EMI1, IO_SLOT_2},
|
||||
{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_6},
|
||||
{WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
|
||||
EMI1, IO_SLOT_6} } },
|
||||
{20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
|
||||
EMI1, IO_SLOT_1},
|
||||
{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
|
||||
EMI1, IO_SLOT_2} } }
|
||||
};
|
||||
|
||||
static const struct serdes_phy_config serdes2_phy_config[] = {
|
||||
{2, {} },
|
||||
{3, {} },
|
||||
{5, {} },
|
||||
{11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_7},
|
||||
{WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_7},
|
||||
{WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_7},
|
||||
{WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_8},
|
||||
{WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_8},
|
||||
{WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
|
||||
EMI1, IO_SLOT_8} } },
|
||||
};
|
||||
|
||||
static const struct serdes_phy_config serdes3_phy_config[] = {
|
||||
{2, {} },
|
||||
{3, {} }
|
||||
};
|
||||
|
||||
static inline
|
||||
const struct phy_config *get_phy_config(u8 serdes,
|
||||
const struct serdes_phy_config *table,
|
||||
u8 table_size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < table_size; i++) {
|
||||
if (table[i].serdes == serdes)
|
||||
return table[i].phy_config;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* BRDCFG4 controls EMI routing for the board.
|
||||
* Bits Function
|
||||
* 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
|
||||
* EMI1 00= On-board PHY #1
|
||||
* 01= On-board PHY #2
|
||||
* 10= (reserved)
|
||||
* 11= Slots 1..8 multiplexer and translator.
|
||||
* 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
|
||||
* EMI1X 000= Slot #1
|
||||
* 001= Slot #2
|
||||
* 010= Slot #3
|
||||
* 011= Slot #4
|
||||
* 100= Slot #5
|
||||
* 101= Slot #6
|
||||
* 110= Slot #7
|
||||
* 111= Slot #8
|
||||
* 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
|
||||
* EMI2 000= Slot #1 (secondary EMI)
|
||||
* 001= Slot #2 (secondary EMI)
|
||||
* 010= Slot #3 (secondary EMI)
|
||||
* 011= Slot #4 (secondary EMI)
|
||||
* 100= Slot #5 (secondary EMI)
|
||||
* 101= Slot #6 (secondary EMI)
|
||||
* 110= Slot #7 (secondary EMI)
|
||||
* 111= Slot #8 (secondary EMI)
|
||||
*/
|
||||
static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
|
||||
{
|
||||
switch (realbusnum) {
|
||||
case EMI1:
|
||||
switch (ioslot) {
|
||||
case EMI1_RGMII1:
|
||||
return 0;
|
||||
case EMI1_RGMII2:
|
||||
return 0x40;
|
||||
default:
|
||||
return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
|
||||
}
|
||||
break;
|
||||
case EMI2:
|
||||
return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
|
||||
{
|
||||
u8 brdcfg4, mux_val, reg;
|
||||
|
||||
brdcfg4 = QIXIS_READ(brdcfg[4]);
|
||||
reg = brdcfg4;
|
||||
mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
|
||||
|
||||
switch (priv->realbusnum) {
|
||||
case EMI1:
|
||||
brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
|
||||
brdcfg4 |= mux_val;
|
||||
break;
|
||||
case EMI2:
|
||||
brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
|
||||
brdcfg4 |= mux_val;
|
||||
break;
|
||||
}
|
||||
|
||||
if (brdcfg4 ^ reg)
|
||||
QIXIS_WRITE(brdcfg[4], brdcfg4);
|
||||
}
|
||||
|
||||
static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
|
||||
int devad, int regnum)
|
||||
{
|
||||
struct lx2160a_qds_mdio *priv = bus->priv;
|
||||
|
||||
lx2160a_qds_mux_mdio(priv);
|
||||
|
||||
return priv->realbus->read(priv->realbus, addr, devad, regnum);
|
||||
}
|
||||
|
||||
static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
|
||||
int regnum, u16 value)
|
||||
{
|
||||
struct lx2160a_qds_mdio *priv = bus->priv;
|
||||
|
||||
lx2160a_qds_mux_mdio(priv);
|
||||
|
||||
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
|
||||
}
|
||||
|
||||
static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
|
||||
{
|
||||
struct lx2160a_qds_mdio *priv = bus->priv;
|
||||
|
||||
return priv->realbus->reset(priv->realbus);
|
||||
}
|
||||
|
||||
static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
|
||||
{
|
||||
struct lx2160a_qds_mdio *pmdio;
|
||||
struct mii_dev *bus;
|
||||
/*should be within MDIO_NAME_LEN*/
|
||||
char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
|
||||
|
||||
if (realbusnum == EMI2) {
|
||||
if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
|
||||
printf("invalid ioslot %d\n", ioslot);
|
||||
return NULL;
|
||||
}
|
||||
} else if (realbusnum == EMI1) {
|
||||
if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
|
||||
printf("invalid ioslot %d\n", ioslot);
|
||||
return NULL;
|
||||
}
|
||||
} else {
|
||||
printf("not supported real mdio bus %d\n", realbusnum);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (ioslot == EMI1_RGMII1)
|
||||
strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
|
||||
else if (ioslot == EMI1_RGMII2)
|
||||
strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
|
||||
else
|
||||
sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
|
||||
realbusnum, ioslot);
|
||||
bus = miiphy_get_dev_by_name(dummy_mdio_name);
|
||||
|
||||
if (bus)
|
||||
return bus;
|
||||
|
||||
bus = mdio_alloc();
|
||||
if (!bus) {
|
||||
printf("Failed to allocate %s bus\n", dummy_mdio_name);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
pmdio = malloc(sizeof(*pmdio));
|
||||
if (!pmdio) {
|
||||
printf("Failed to allocate %s private data\n", dummy_mdio_name);
|
||||
free(bus);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
switch (realbusnum) {
|
||||
case EMI1:
|
||||
pmdio->realbus =
|
||||
miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
|
||||
break;
|
||||
case EMI2:
|
||||
pmdio->realbus =
|
||||
miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
|
||||
break;
|
||||
}
|
||||
|
||||
if (!pmdio->realbus) {
|
||||
printf("No real mdio bus num %d found\n", realbusnum);
|
||||
free(bus);
|
||||
free(pmdio);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
pmdio->realbusnum = realbusnum;
|
||||
pmdio->ioslot = ioslot;
|
||||
bus->read = lx2160a_qds_mdio_read;
|
||||
bus->write = lx2160a_qds_mdio_write;
|
||||
bus->reset = lx2160a_qds_mdio_reset;
|
||||
strcpy(bus->name, dummy_mdio_name);
|
||||
bus->priv = pmdio;
|
||||
|
||||
if (!mdio_register(bus))
|
||||
return bus;
|
||||
|
||||
printf("No bus with name %s\n", dummy_mdio_name);
|
||||
free(bus);
|
||||
free(pmdio);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void do_phy_config(const struct phy_config *phy_config)
|
||||
{
|
||||
struct mii_dev *bus;
|
||||
int i, phy_num, phy_address;
|
||||
|
||||
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
||||
if (!phy_config[i].dpmacid)
|
||||
continue;
|
||||
|
||||
for (phy_num = 0;
|
||||
phy_num < ARRAY_SIZE(phy_config[i].phy_address);
|
||||
phy_num++) {
|
||||
phy_address = phy_config[i].phy_address[phy_num];
|
||||
if (phy_address == -1)
|
||||
break;
|
||||
wriop_set_phy_address(phy_config[i].dpmacid,
|
||||
phy_num, phy_address);
|
||||
}
|
||||
/*Register the muxing front-ends to the MDIO buses*/
|
||||
bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
|
||||
phy_config[i].ioslot);
|
||||
if (!bus)
|
||||
printf("could not get bus for mdio %d ioslot %d\n",
|
||||
phy_config[i].mdio_bus,
|
||||
phy_config[i].ioslot);
|
||||
else
|
||||
wriop_set_mdio(phy_config[i].dpmacid, bus);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
|
||||
char *env_dpmac)
|
||||
{
|
||||
const char *ret;
|
||||
size_t len;
|
||||
u8 realbusnum, ioslot;
|
||||
struct mii_dev *bus;
|
||||
int phy_num;
|
||||
char *phystr = "phy00";
|
||||
|
||||
/*search phy in dpmac arg*/
|
||||
for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
|
||||
sprintf(phystr, "phy%d", phy_num + 1);
|
||||
ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
|
||||
if (!ret) {
|
||||
/*look for phy instead of phy1*/
|
||||
if (!phy_num)
|
||||
ret = hwconfig_subarg_f(arg_dpmacid, "phy",
|
||||
&len, env_dpmac);
|
||||
if (!ret)
|
||||
continue;
|
||||
}
|
||||
|
||||
if (len != 4 || strncmp(ret, "0x", 2))
|
||||
printf("invalid phy format in %s variable.\n"
|
||||
"specify phy%d for %s in hex format e.g. 0x12\n",
|
||||
env_dpmac, phy_num + 1, arg_dpmacid);
|
||||
else
|
||||
wriop_set_phy_address(dpmac, phy_num,
|
||||
simple_strtoul(ret, NULL, 16));
|
||||
}
|
||||
|
||||
/*search mdio in dpmac arg*/
|
||||
ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
|
||||
if (ret)
|
||||
realbusnum = *ret - '0';
|
||||
else
|
||||
realbusnum = EMI_NONE;
|
||||
|
||||
if (realbusnum) {
|
||||
/*search io in dpmac arg*/
|
||||
ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
|
||||
if (ret)
|
||||
ioslot = *ret - '0';
|
||||
else
|
||||
ioslot = IO_SLOT_NONE;
|
||||
/*Register the muxing front-ends to the MDIO buses*/
|
||||
bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
|
||||
if (!bus)
|
||||
printf("could not get bus for mdio %d ioslot %d\n",
|
||||
realbusnum, ioslot);
|
||||
else
|
||||
wriop_set_mdio(dpmac, bus);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
struct memac_mdio_info mdio_info;
|
||||
struct memac_mdio_controller *regs;
|
||||
int i;
|
||||
const char *ret;
|
||||
char *env_dpmac;
|
||||
char dpmacid[] = "dpmac00", srds[] = "00_00_00";
|
||||
size_t len;
|
||||
struct mii_dev *bus;
|
||||
const struct phy_config *phy_config;
|
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 srds_s1, srds_s2, srds_s3;
|
||||
|
||||
srds_s1 = in_le32(&gur->rcwsr[28]) &
|
||||
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
|
||||
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
|
||||
|
||||
srds_s2 = in_le32(&gur->rcwsr[28]) &
|
||||
FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
|
||||
srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
|
||||
|
||||
srds_s3 = in_le32(&gur->rcwsr[28]) &
|
||||
FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
|
||||
srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
|
||||
|
||||
sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
|
||||
|
||||
regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
|
||||
mdio_info.regs = regs;
|
||||
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
|
||||
|
||||
/*Register the EMI 1*/
|
||||
fm_memac_mdio_init(bis, &mdio_info);
|
||||
|
||||
regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
|
||||
mdio_info.regs = regs;
|
||||
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
|
||||
|
||||
/*Register the EMI 2*/
|
||||
fm_memac_mdio_init(bis, &mdio_info);
|
||||
|
||||
/* "dpmac" environment variable can be used after
|
||||
* defining "dpmac_override" in hwconfig environment variable.
|
||||
*/
|
||||
if (hwconfig("dpmac_override")) {
|
||||
env_dpmac = env_get("dpmac");
|
||||
if (env_dpmac) {
|
||||
ret = hwconfig_arg_f("srds", &len, env_dpmac);
|
||||
if (ret) {
|
||||
if (strncmp(ret, srds, strlen(srds))) {
|
||||
printf("SERDES configuration changed.\n"
|
||||
"previous: %.*s, current: %s.\n"
|
||||
"update dpmac variable.\n",
|
||||
(int)len, ret, srds);
|
||||
}
|
||||
} else {
|
||||
printf("SERDES configuration not found.\n"
|
||||
"Please add srds:%s in dpmac variable\n",
|
||||
srds);
|
||||
}
|
||||
|
||||
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
|
||||
/* Look for dpmac1 to dpmac24(current max) arg
|
||||
* in dpmac environment variable
|
||||
*/
|
||||
sprintf(dpmacid, "dpmac%d", i);
|
||||
ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
|
||||
if (ret)
|
||||
do_dpmac_config(i, dpmacid, env_dpmac);
|
||||
}
|
||||
} else {
|
||||
printf("Warning: environment dpmac not found.\n"
|
||||
"DPAA network interfaces may not work\n");
|
||||
}
|
||||
} else {
|
||||
/*Look for phy config for serdes1 in phy config table*/
|
||||
phy_config = get_phy_config(srds_s1, serdes1_phy_config,
|
||||
ARRAY_SIZE(serdes1_phy_config));
|
||||
if (!phy_config) {
|
||||
printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
|
||||
__func__, srds_s1);
|
||||
} else {
|
||||
do_phy_config(phy_config);
|
||||
}
|
||||
phy_config = get_phy_config(srds_s2, serdes2_phy_config,
|
||||
ARRAY_SIZE(serdes2_phy_config));
|
||||
if (!phy_config) {
|
||||
printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
|
||||
__func__, srds_s2);
|
||||
} else {
|
||||
do_phy_config(phy_config);
|
||||
}
|
||||
phy_config = get_phy_config(srds_s3, serdes3_phy_config,
|
||||
ARRAY_SIZE(serdes3_phy_config));
|
||||
if (!phy_config) {
|
||||
printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
|
||||
__func__, srds_s3);
|
||||
} else {
|
||||
do_phy_config(phy_config);
|
||||
}
|
||||
}
|
||||
|
||||
if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
|
||||
wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
|
||||
bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
|
||||
if (!bus)
|
||||
printf("could not get bus for RGMII1\n");
|
||||
else
|
||||
wriop_set_mdio(WRIOP1_DPMAC17, bus);
|
||||
}
|
||||
|
||||
if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
|
||||
wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
|
||||
bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
|
||||
if (!bus)
|
||||
printf("could not get bus for RGMII2\n");
|
||||
else
|
||||
wriop_set_mdio(WRIOP1_DPMAC18, bus);
|
||||
}
|
||||
|
||||
cpu_eth_init(bis);
|
||||
#endif /* CONFIG_FMAN_ENET */
|
||||
|
||||
#ifdef CONFIG_PHY_AQUANTIA
|
||||
/*
|
||||
* Export functions to be used by AQ firmware
|
||||
* upload application
|
||||
*/
|
||||
gd->jt->strcpy = strcpy;
|
||||
gd->jt->mdelay = mdelay;
|
||||
gd->jt->mdio_get_current_dev = mdio_get_current_dev;
|
||||
gd->jt->phy_find_by_mask = phy_find_by_mask;
|
||||
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
|
||||
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
|
||||
#endif
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_RESET_PHY_R)
|
||||
void reset_phy(void)
|
||||
{
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
mc_env_boot();
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_RESET_PHY_R */
|
||||
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
|
||||
{
|
||||
int offset;
|
||||
int ret;
|
||||
char dpmac_str[] = "dpmacs@00";
|
||||
const char *phy_string;
|
||||
|
||||
offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
|
||||
|
||||
if (offset < 0)
|
||||
offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
|
||||
|
||||
if (offset < 0) {
|
||||
printf("dpmacs node not found in device tree\n");
|
||||
return offset;
|
||||
}
|
||||
|
||||
sprintf(dpmac_str, "dpmac@%x", dpmac_id);
|
||||
debug("dpmac_str = %s\n", dpmac_str);
|
||||
|
||||
offset = fdt_subnode_offset(fdt, offset, dpmac_str);
|
||||
if (offset < 0) {
|
||||
printf("%s node not found in device tree\n", dpmac_str);
|
||||
return offset;
|
||||
}
|
||||
|
||||
ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
|
||||
if (ret)
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
|
||||
phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
|
||||
ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
|
||||
phy_string);
|
||||
if (ret)
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
|
||||
{
|
||||
char mdio_ioslot_str[] = "mdio@00";
|
||||
char mdio_mux_str[] = "mdio-mux-0";
|
||||
struct lx2160a_qds_mdio *priv;
|
||||
int offset, mux_val;
|
||||
|
||||
/*Test if the MDIO bus is real mdio bus or muxing front end ?*/
|
||||
if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
|
||||
strlen("LX2160A_QDS_MDIO")))
|
||||
return -1;
|
||||
|
||||
/*Get the real MDIO bus num and ioslot info from bus's priv data*/
|
||||
priv = mii_dev->priv;
|
||||
|
||||
debug("real_bus_num = %d, ioslot = %d\n",
|
||||
priv->realbusnum, priv->ioslot);
|
||||
|
||||
sprintf(mdio_mux_str, "mdio-mux-%1d", priv->realbusnum);
|
||||
offset = fdt_subnode_offset(fdt, fpga_offset, mdio_mux_str);
|
||||
if (offset < 0) {
|
||||
printf("%s node not found under node %s in device tree\n",
|
||||
mdio_mux_str, fdt_get_name(fdt, fpga_offset, NULL));
|
||||
return offset;
|
||||
}
|
||||
|
||||
mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
|
||||
sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
|
||||
|
||||
offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
|
||||
if (offset < 0) {
|
||||
printf("%s node not found in device tree\n", mdio_ioslot_str);
|
||||
return offset;
|
||||
}
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
|
||||
struct phy_device *phy_dev, int phandle)
|
||||
{
|
||||
char phy_node_name[] = "ethernet-phy@00";
|
||||
char phy_id_compatible_str[] = "ethernet-phy-id0000.0000";
|
||||
int ret;
|
||||
|
||||
sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
|
||||
debug("phy_node_name = %s\n", phy_node_name);
|
||||
|
||||
*subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
|
||||
if (*subnodeoffset <= 0) {
|
||||
printf("Could not add subnode %s\n", phy_node_name);
|
||||
return *subnodeoffset;
|
||||
}
|
||||
|
||||
sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x",
|
||||
phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
|
||||
debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
|
||||
|
||||
ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
|
||||
phy_id_compatible_str);
|
||||
if (ret) {
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (phy_dev->is_c45) {
|
||||
ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
|
||||
"ethernet-phy-ieee802.3-c45");
|
||||
if (ret) {
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
goto out;
|
||||
}
|
||||
} else {
|
||||
ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
|
||||
"ethernet-phy-ieee802.3-c22");
|
||||
if (ret) {
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
|
||||
if (ret) {
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
|
||||
if (ret) {
|
||||
printf("%d@%s %d\n", __LINE__, __func__, ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
if (ret)
|
||||
fdt_del_node(fdt, *subnodeoffset);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int fdt_fixup_board_phy(void *fdt)
|
||||
{
|
||||
int fpga_offset, offset, subnodeoffset;
|
||||
struct mii_dev *mii_dev;
|
||||
struct list_head *mii_devs, *entry;
|
||||
int ret, dpmac_id, phandle, i;
|
||||
struct phy_device *phy_dev;
|
||||
char ethname[ETH_NAME_LEN];
|
||||
phy_interface_t phy_iface;
|
||||
|
||||
ret = 0;
|
||||
/* we know FPGA is connected to i2c0, therefore search path directly,
|
||||
* instead of compatible property, as it saves time
|
||||
*/
|
||||
fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
|
||||
|
||||
if (fpga_offset < 0)
|
||||
fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
|
||||
|
||||
if (fpga_offset < 0) {
|
||||
printf("i2c@2000000/fpga node not found in device tree\n");
|
||||
return fpga_offset;
|
||||
}
|
||||
|
||||
phandle = fdt_alloc_phandle(fdt);
|
||||
mii_devs = mdio_get_list_head();
|
||||
|
||||
list_for_each(entry, mii_devs) {
|
||||
mii_dev = list_entry(entry, struct mii_dev, link);
|
||||
debug("mii_dev name : %s\n", mii_dev->name);
|
||||
offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
|
||||
if (offset < 0)
|
||||
continue;
|
||||
|
||||
// Look for phy devices attached to MDIO bus muxing front end
|
||||
// and create their entries with compatible being the device id
|
||||
for (i = 0; i < PHY_MAX_ADDR; i++) {
|
||||
phy_dev = mii_dev->phymap[i];
|
||||
if (!phy_dev)
|
||||
continue;
|
||||
|
||||
// TODO: use sscanf instead of loop
|
||||
dpmac_id = WRIOP1_DPMAC1;
|
||||
while (dpmac_id < NUM_WRIOP_PORTS) {
|
||||
phy_iface = wriop_get_enet_if(dpmac_id);
|
||||
snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
|
||||
dpmac_id,
|
||||
phy_string_for_interface(phy_iface));
|
||||
if (strcmp(ethname, phy_dev->dev->name) == 0)
|
||||
break;
|
||||
dpmac_id++;
|
||||
}
|
||||
if (dpmac_id == NUM_WRIOP_PORTS)
|
||||
continue;
|
||||
|
||||
ret = fdt_create_phy_node(fdt, offset, i,
|
||||
&subnodeoffset,
|
||||
phy_dev, phandle);
|
||||
if (ret)
|
||||
break;
|
||||
|
||||
ret = fdt_fixup_dpmac_phy_handle(fdt,
|
||||
dpmac_id, phandle);
|
||||
if (ret) {
|
||||
fdt_del_node(fdt, subnodeoffset);
|
||||
break;
|
||||
}
|
||||
phandle++;
|
||||
}
|
||||
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif // CONFIG_FSL_MC_ENET
|
||||
|
||||
210
board/freescale/lx2160a/eth_lx2160ardb.c
Normal file
210
board/freescale/lx2160a/eth_lx2160ardb.c
Normal file
|
|
@ -0,0 +1,210 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <netdev.h>
|
||||
#include <malloc.h>
|
||||
#include <fsl_mdio.h>
|
||||
#include <miiphy.h>
|
||||
#include <phy.h>
|
||||
#include <fm_eth.h>
|
||||
#include <asm/io.h>
|
||||
#include <exports.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <fsl-mc/fsl_mc.h>
|
||||
#include <fsl-mc/ldpaa_wriop.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
|
||||
{
|
||||
int phy_reg;
|
||||
u32 phy_id;
|
||||
|
||||
phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
|
||||
phy_id = (phy_reg & 0xffff) << 16;
|
||||
|
||||
phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
|
||||
phy_id |= (phy_reg & 0xffff);
|
||||
|
||||
if (phy_id == PHY_UID_IN112525_S03)
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
struct memac_mdio_info mdio_info;
|
||||
struct memac_mdio_controller *reg;
|
||||
int i, interface;
|
||||
struct mii_dev *dev;
|
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 srds_s1;
|
||||
|
||||
srds_s1 = in_le32(&gur->rcwsr[28]) &
|
||||
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
|
||||
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
|
||||
|
||||
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
|
||||
mdio_info.regs = reg;
|
||||
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
|
||||
|
||||
/* Register the EMI 1 */
|
||||
fm_memac_mdio_init(bis, &mdio_info);
|
||||
|
||||
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
|
||||
mdio_info.regs = reg;
|
||||
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
|
||||
|
||||
/* Register the EMI 2 */
|
||||
fm_memac_mdio_init(bis, &mdio_info);
|
||||
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
|
||||
switch (srds_s1) {
|
||||
case 19:
|
||||
wriop_set_phy_address(WRIOP1_DPMAC2, 0,
|
||||
CORTINA_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC3, 0,
|
||||
AQR107_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC4, 0,
|
||||
AQR107_PHY_ADDR2);
|
||||
if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
|
||||
wriop_set_phy_address(WRIOP1_DPMAC5, 0,
|
||||
INPHI_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC6, 0,
|
||||
INPHI_PHY_ADDR1);
|
||||
}
|
||||
wriop_set_phy_address(WRIOP1_DPMAC17, 0,
|
||||
RGMII_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC18, 0,
|
||||
RGMII_PHY_ADDR2);
|
||||
break;
|
||||
|
||||
case 18:
|
||||
wriop_set_phy_address(WRIOP1_DPMAC7, 0,
|
||||
CORTINA_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC8, 0,
|
||||
CORTINA_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC9, 0,
|
||||
CORTINA_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC10, 0,
|
||||
CORTINA_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC3, 0,
|
||||
AQR107_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC4, 0,
|
||||
AQR107_PHY_ADDR2);
|
||||
if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
|
||||
wriop_set_phy_address(WRIOP1_DPMAC5, 0,
|
||||
INPHI_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC6, 0,
|
||||
INPHI_PHY_ADDR1);
|
||||
}
|
||||
wriop_set_phy_address(WRIOP1_DPMAC17, 0,
|
||||
RGMII_PHY_ADDR1);
|
||||
wriop_set_phy_address(WRIOP1_DPMAC18, 0,
|
||||
RGMII_PHY_ADDR2);
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
|
||||
srds_s1);
|
||||
goto next;
|
||||
}
|
||||
|
||||
for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
|
||||
interface = wriop_get_enet_if(i);
|
||||
switch (interface) {
|
||||
case PHY_INTERFACE_MODE_XGMII:
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
|
||||
wriop_set_mdio(i, dev);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_25G_AUI:
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
|
||||
wriop_set_mdio(i, dev);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_XLAUI:
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
|
||||
wriop_set_mdio(i, dev);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
|
||||
interface = wriop_get_enet_if(i);
|
||||
switch (interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
|
||||
wriop_set_mdio(i, dev);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
next:
|
||||
cpu_eth_init(bis);
|
||||
#endif /* CONFIG_FSL_MC_ENET */
|
||||
|
||||
#ifdef CONFIG_PHY_AQUANTIA
|
||||
/*
|
||||
* Export functions to be used by AQ firmware
|
||||
* upload application
|
||||
*/
|
||||
gd->jt->strcpy = strcpy;
|
||||
gd->jt->mdelay = mdelay;
|
||||
gd->jt->mdio_get_current_dev = mdio_get_current_dev;
|
||||
gd->jt->phy_find_by_mask = phy_find_by_mask;
|
||||
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
|
||||
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
|
||||
#endif
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_RESET_PHY_R)
|
||||
void reset_phy(void)
|
||||
{
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
mc_env_boot();
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_RESET_PHY_R */
|
||||
|
||||
int fdt_fixup_board_phy(void *fdt)
|
||||
{
|
||||
int mdio_offset;
|
||||
int ret;
|
||||
struct mii_dev *dev;
|
||||
|
||||
ret = 0;
|
||||
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
|
||||
if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
|
||||
mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
|
||||
|
||||
if (mdio_offset < 0)
|
||||
mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
|
||||
|
||||
if (mdio_offset < 0) {
|
||||
printf("mdio@0x8B9700 node not found in dts\n");
|
||||
return mdio_offset;
|
||||
}
|
||||
|
||||
ret = fdt_setprop_string(fdt, mdio_offset, "status",
|
||||
"disabled");
|
||||
if (ret) {
|
||||
printf("Could not set disable mdio@0x8B97000 %s\n",
|
||||
fdt_strerror(ret));
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
574
board/freescale/lx2160a/lx2160a.c
Normal file
574
board/freescale/lx2160a/lx2160a.c
Normal file
|
|
@ -0,0 +1,574 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <dm/platform_data/serial_pl01x.h>
|
||||
#include <i2c.h>
|
||||
#include <malloc.h>
|
||||
#include <errno.h>
|
||||
#include <netdev.h>
|
||||
#include <fsl_ddr.h>
|
||||
#include <fsl_sec.h>
|
||||
#include <asm/io.h>
|
||||
#include <fdt_support.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <fsl-mc/fsl_mc.h>
|
||||
#include <environment.h>
|
||||
#include <efi_loader.h>
|
||||
#include <asm/arch/mmu.h>
|
||||
#include <hwconfig.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include "../common/qixis.h"
|
||||
#include "../common/vid.h"
|
||||
#include <fsl_immap.h>
|
||||
|
||||
#ifdef CONFIG_EMC2305
|
||||
#include "../common/emc2305.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
|
||||
#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
|
||||
#define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
|
||||
#define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
|
||||
#define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
|
||||
#define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
|
||||
#define SDHC1_BASE_PMUX_DSPI 2
|
||||
#define SDHC2_BASE_PMUX_DSPI 2
|
||||
#define IIC5_PMUX_SPI3 3
|
||||
#endif /* CONFIG_TARGET_LX2160AQDS */
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static struct pl01x_serial_platdata serial0 = {
|
||||
#if CONFIG_CONS_INDEX == 0
|
||||
.base = CONFIG_SYS_SERIAL0,
|
||||
#elif CONFIG_CONS_INDEX == 1
|
||||
.base = CONFIG_SYS_SERIAL1,
|
||||
#else
|
||||
#error "Unsupported console index value."
|
||||
#endif
|
||||
.type = TYPE_PL011,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(nxp_serial0) = {
|
||||
.name = "serial_pl01x",
|
||||
.platdata = &serial0,
|
||||
};
|
||||
|
||||
static struct pl01x_serial_platdata serial1 = {
|
||||
.base = CONFIG_SYS_SERIAL1,
|
||||
.type = TYPE_PL011,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(nxp_serial1) = {
|
||||
.name = "serial_pl01x",
|
||||
.platdata = &serial1,
|
||||
};
|
||||
|
||||
int select_i2c_ch_pca9547(u8 ch)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
|
||||
if (ret) {
|
||||
puts("PCA: failed to select proper channel\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void uart_get_clock(void)
|
||||
{
|
||||
serial0.clock = get_serial_clock();
|
||||
serial1.clock = get_serial_clock();
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_I2C_EARLY_INIT
|
||||
i2c_early_init_f();
|
||||
#endif
|
||||
/* get required clock for UART IP */
|
||||
uart_get_clock();
|
||||
|
||||
#ifdef CONFIG_EMC2305
|
||||
select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
|
||||
emc2305_init();
|
||||
set_fan_speed(I2C_EMC2305_PWM);
|
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
|
||||
#endif
|
||||
|
||||
fsl_lsch3_early_init_f();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_TARGET_LX2160AQDS)
|
||||
void esdhc_dspi_status_fixup(void *blob)
|
||||
{
|
||||
const char esdhc0_path[] = "/soc/esdhc@2140000";
|
||||
const char esdhc1_path[] = "/soc/esdhc@2150000";
|
||||
const char dspi0_path[] = "/soc/dspi@2100000";
|
||||
const char dspi1_path[] = "/soc/dspi@2110000";
|
||||
const char dspi2_path[] = "/soc/dspi@2120000";
|
||||
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 sdhc1_base_pmux;
|
||||
u32 sdhc2_base_pmux;
|
||||
u32 iic5_pmux;
|
||||
|
||||
/* Check RCW field sdhc1_base_pmux to enable/disable
|
||||
* esdhc0/dspi0 DT node
|
||||
*/
|
||||
sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
|
||||
& FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
|
||||
sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
|
||||
|
||||
if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
|
||||
do_fixup_by_path(blob, dspi0_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
|
||||
sizeof("disabled"), 1);
|
||||
} else {
|
||||
do_fixup_by_path(blob, esdhc0_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
do_fixup_by_path(blob, dspi0_path, "status", "disabled",
|
||||
sizeof("disabled"), 1);
|
||||
}
|
||||
|
||||
/* Check RCW field sdhc2_base_pmux to enable/disable
|
||||
* esdhc1/dspi1 DT node
|
||||
*/
|
||||
sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
|
||||
& FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
|
||||
sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
|
||||
|
||||
if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
|
||||
do_fixup_by_path(blob, dspi1_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
|
||||
sizeof("disabled"), 1);
|
||||
} else {
|
||||
do_fixup_by_path(blob, esdhc1_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
do_fixup_by_path(blob, dspi1_path, "status", "disabled",
|
||||
sizeof("disabled"), 1);
|
||||
}
|
||||
|
||||
/* Check RCW field IIC5 to enable dspi2 DT node */
|
||||
iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
|
||||
& FSL_CHASSIS3_IIC5_PMUX_MASK;
|
||||
iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
|
||||
|
||||
if (iic5_pmux == IIC5_PMUX_SPI3) {
|
||||
do_fixup_by_path(blob, dspi2_path, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
int esdhc_status_fixup(void *blob, const char *compat)
|
||||
{
|
||||
#if defined(CONFIG_TARGET_LX2160AQDS)
|
||||
/* Enable esdhc and dspi DT nodes based on RCW fields */
|
||||
esdhc_dspi_status_fixup(blob);
|
||||
#else
|
||||
/* Enable both esdhc DT nodes for LX2160ARDB */
|
||||
do_fixup_by_compat(blob, compat, "status", "okay",
|
||||
sizeof("okay"), 1);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_VID)
|
||||
int i2c_multiplexer_select_vid_channel(u8 channel)
|
||||
{
|
||||
return select_i2c_ch_pca9547(channel);
|
||||
}
|
||||
|
||||
int init_func_vid(void)
|
||||
{
|
||||
if (adjust_vdd(0) < 0)
|
||||
printf("core voltage not adjusted\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
enum boot_src src = get_boot_src();
|
||||
char buf[64];
|
||||
u8 sw;
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
int clock;
|
||||
static const char *const freq[] = {"100", "125", "156.25",
|
||||
"161.13", "322.26", "", "", "",
|
||||
"", "", "", "", "", "", "",
|
||||
"100 separate SSCG"};
|
||||
#endif
|
||||
|
||||
cpu_name(buf);
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
printf("Board: %s-QDS, ", buf);
|
||||
#else
|
||||
printf("Board: %s-RDB, ", buf);
|
||||
#endif
|
||||
|
||||
sw = QIXIS_READ(arch);
|
||||
printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
|
||||
|
||||
if (src == BOOT_SOURCE_SD_MMC) {
|
||||
puts("SD\n");
|
||||
} else {
|
||||
sw = QIXIS_READ(brdcfg[0]);
|
||||
sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
|
||||
switch (sw) {
|
||||
case 0:
|
||||
case 4:
|
||||
puts("FlexSPI DEV#0\n");
|
||||
break;
|
||||
case 1:
|
||||
puts("FlexSPI DEV#1\n");
|
||||
break;
|
||||
case 2:
|
||||
case 3:
|
||||
puts("FlexSPI EMU\n");
|
||||
break;
|
||||
default:
|
||||
printf("invalid setting, xmap: %d\n", sw);
|
||||
break;
|
||||
}
|
||||
}
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
printf("FPGA: v%d (%s), build %d",
|
||||
(int)QIXIS_READ(scver), qixis_read_tag(buf),
|
||||
(int)qixis_read_minor());
|
||||
/* the timestamp string contains "\n" at the end */
|
||||
printf(" on %s", qixis_read_time(buf));
|
||||
|
||||
puts("SERDES1 Reference : ");
|
||||
sw = QIXIS_READ(brdcfg[2]);
|
||||
clock = sw >> 4;
|
||||
printf("Clock1 = %sMHz ", freq[clock]);
|
||||
clock = sw & 0x0f;
|
||||
printf("Clock2 = %sMHz", freq[clock]);
|
||||
|
||||
sw = QIXIS_READ(brdcfg[3]);
|
||||
puts("\nSERDES2 Reference : ");
|
||||
clock = sw >> 4;
|
||||
printf("Clock1 = %sMHz ", freq[clock]);
|
||||
clock = sw & 0x0f;
|
||||
printf("Clock2 = %sMHz", freq[clock]);
|
||||
|
||||
sw = QIXIS_READ(brdcfg[12]);
|
||||
puts("\nSERDES3 Reference : ");
|
||||
clock = sw >> 4;
|
||||
printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
|
||||
#else
|
||||
printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
|
||||
|
||||
puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
|
||||
puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
|
||||
puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
/*
|
||||
* implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
|
||||
*/
|
||||
u8 qixis_esdhc_detect_quirk(void)
|
||||
{
|
||||
/* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
|
||||
* SDHC1 Card ID:
|
||||
* Specifies the type of card installed in the SDHC1 adapter slot.
|
||||
* 000= (reserved)
|
||||
* 001= eMMC V4.5 adapter is installed.
|
||||
* 010= SD/MMC 3.3V adapter is installed.
|
||||
* 011= eMMC V4.4 adapter is installed.
|
||||
* 100= eMMC V5.0 adapter is installed.
|
||||
* 101= MMC card/Legacy (3.3V) adapter is installed.
|
||||
* 110= SDCard V2/V3 adapter installed.
|
||||
* 111= no adapter is installed.
|
||||
*/
|
||||
return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
|
||||
QIXIS_ESDHC_NO_ADAPTER);
|
||||
}
|
||||
|
||||
int config_board_mux(void)
|
||||
{
|
||||
u8 reg11, reg5, reg13;
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u32 sdhc1_base_pmux;
|
||||
u32 sdhc2_base_pmux;
|
||||
u32 iic5_pmux;
|
||||
|
||||
/* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
|
||||
* Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
|
||||
* Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
|
||||
* Qixis and remote systems are isolated from the I2C1 bus.
|
||||
* Processor connections are still available.
|
||||
* SPI2 CS2_B controls EN25S64 SPI memory device.
|
||||
* SPI3 CS2_B controls EN25S64 SPI memory device.
|
||||
* EC2 connects to PHY #2 using RGMII protocol.
|
||||
* CLK_OUT connects to FPGA for clock measurement.
|
||||
*/
|
||||
|
||||
reg5 = QIXIS_READ(brdcfg[5]);
|
||||
reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
|
||||
QIXIS_WRITE(brdcfg[5], reg5);
|
||||
|
||||
/* Check RCW field sdhc1_base_pmux
|
||||
* esdhc0 : sdhc1_base_pmux = 0
|
||||
* dspi0 : sdhc1_base_pmux = 2
|
||||
*/
|
||||
sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
|
||||
& FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
|
||||
sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
|
||||
|
||||
if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
|
||||
reg11 = QIXIS_READ(brdcfg[11]);
|
||||
reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
|
||||
QIXIS_WRITE(brdcfg[11], reg11);
|
||||
} else {
|
||||
/* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
|
||||
* {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
|
||||
* {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
|
||||
*/
|
||||
reg11 = QIXIS_READ(brdcfg[11]);
|
||||
reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
|
||||
QIXIS_WRITE(brdcfg[11], reg11);
|
||||
}
|
||||
|
||||
/* Check RCW field sdhc2_base_pmux
|
||||
* esdhc1 : sdhc2_base_pmux = 0 (default)
|
||||
* dspi1 : sdhc2_base_pmux = 2
|
||||
*/
|
||||
sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
|
||||
& FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
|
||||
sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
|
||||
|
||||
if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
|
||||
reg13 = QIXIS_READ(brdcfg[13]);
|
||||
reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
|
||||
QIXIS_WRITE(brdcfg[13], reg13);
|
||||
} else {
|
||||
reg13 = QIXIS_READ(brdcfg[13]);
|
||||
reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
|
||||
QIXIS_WRITE(brdcfg[13], reg13);
|
||||
}
|
||||
|
||||
/* Check RCW field IIC5 to enable dspi2 DT nodei
|
||||
* dspi2: IIC5 = 3
|
||||
*/
|
||||
iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
|
||||
& FSL_CHASSIS3_IIC5_PMUX_MASK;
|
||||
iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
|
||||
|
||||
if (iic5_pmux == IIC5_PMUX_SPI3) {
|
||||
/* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
|
||||
reg11 = QIXIS_READ(brdcfg[11]);
|
||||
reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
|
||||
QIXIS_WRITE(brdcfg[11], reg11);
|
||||
|
||||
/* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
|
||||
* {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
|
||||
* {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
|
||||
*/
|
||||
reg11 = QIXIS_READ(brdcfg[11]);
|
||||
reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
|
||||
QIXIS_WRITE(brdcfg[11], reg11);
|
||||
} else {
|
||||
/* Routes {SDHC1_DAT4} to SDHC1 adapter slot */
|
||||
reg11 = QIXIS_READ(brdcfg[11]);
|
||||
reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
|
||||
QIXIS_WRITE(brdcfg[11], reg11);
|
||||
|
||||
/* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
|
||||
* {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
|
||||
* {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
|
||||
*/
|
||||
reg11 = QIXIS_READ(brdcfg[11]);
|
||||
reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
|
||||
QIXIS_WRITE(brdcfg[11], reg11);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
int config_board_mux(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
unsigned long get_board_sys_clk(void)
|
||||
{
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
|
||||
|
||||
switch (sysclk_conf & 0x03) {
|
||||
case QIXIS_SYSCLK_100:
|
||||
return 100000000;
|
||||
case QIXIS_SYSCLK_125:
|
||||
return 125000000;
|
||||
case QIXIS_SYSCLK_133:
|
||||
return 133333333;
|
||||
}
|
||||
return 100000000;
|
||||
#else
|
||||
return 100000000;
|
||||
#endif
|
||||
}
|
||||
|
||||
unsigned long get_board_ddr_clk(void)
|
||||
{
|
||||
#ifdef CONFIG_TARGET_LX2160AQDS
|
||||
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
|
||||
|
||||
switch ((ddrclk_conf & 0x30) >> 4) {
|
||||
case QIXIS_DDRCLK_100:
|
||||
return 100000000;
|
||||
case QIXIS_DDRCLK_125:
|
||||
return 125000000;
|
||||
case QIXIS_DDRCLK_133:
|
||||
return 133333333;
|
||||
}
|
||||
return 100000000;
|
||||
#else
|
||||
return 100000000;
|
||||
#endif
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_IS_NOWHERE
|
||||
gd->env_addr = (ulong)&default_environment[0];
|
||||
#endif
|
||||
|
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
|
||||
|
||||
#ifdef CONFIG_FSL_CAAM
|
||||
sec_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void detail_board_ddr_info(void)
|
||||
{
|
||||
int i;
|
||||
u64 ddr_size = 0;
|
||||
|
||||
puts("\nDDR ");
|
||||
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
|
||||
ddr_size += gd->bd->bi_dram[i].size;
|
||||
print_size(ddr_size, "");
|
||||
print_ddr_info(0);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARCH_MISC_INIT)
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
config_board_mux();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_MC_ENET
|
||||
extern int fdt_fixup_board_phy(void *fdt);
|
||||
|
||||
void fdt_fixup_board_enet(void *fdt)
|
||||
{
|
||||
int offset;
|
||||
|
||||
offset = fdt_path_offset(fdt, "/soc/fsl-mc");
|
||||
|
||||
if (offset < 0)
|
||||
offset = fdt_path_offset(fdt, "/fsl-mc");
|
||||
|
||||
if (offset < 0) {
|
||||
printf("%s: fsl-mc node not found in device tree (error %d)\n",
|
||||
__func__, offset);
|
||||
return;
|
||||
}
|
||||
|
||||
if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) {
|
||||
fdt_status_okay(fdt, offset);
|
||||
fdt_fixup_board_phy(fdt);
|
||||
} else {
|
||||
fdt_status_fail(fdt, offset);
|
||||
}
|
||||
}
|
||||
|
||||
void board_quiesce_devices(void)
|
||||
{
|
||||
fsl_mc_ldpaa_exit(gd->bd);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int i;
|
||||
u64 base[CONFIG_NR_DRAM_BANKS];
|
||||
u64 size[CONFIG_NR_DRAM_BANKS];
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
/* fixup DT for the three GPP DDR banks */
|
||||
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
||||
base[i] = gd->bd->bi_dram[i].start;
|
||||
size[i] = gd->bd->bi_dram[i].size;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RESV_RAM
|
||||
/* reduce size if reserved memory is within this bank */
|
||||
if (gd->arch.resv_ram >= base[0] &&
|
||||
gd->arch.resv_ram < base[0] + size[0])
|
||||
size[0] = gd->arch.resv_ram - base[0];
|
||||
else if (gd->arch.resv_ram >= base[1] &&
|
||||
gd->arch.resv_ram < base[1] + size[1])
|
||||
size[1] = gd->arch.resv_ram - base[1];
|
||||
else if (gd->arch.resv_ram >= base[2] &&
|
||||
gd->arch.resv_ram < base[2] + size[2])
|
||||
size[2] = gd->arch.resv_ram - base[2];
|
||||
#endif
|
||||
|
||||
fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
|
||||
|
||||
#ifdef CONFIG_USB
|
||||
fsl_fdt_fixup_dr_usb(blob, bd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_MC_ENET
|
||||
fdt_fsl_mc_fixup_iommu_map_entry(blob);
|
||||
fdt_fixup_board_enet(blob);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void qixis_dump_switch(void)
|
||||
{
|
||||
int i, nr_of_cfgsw;
|
||||
|
||||
QIXIS_WRITE(cms[0], 0x00);
|
||||
nr_of_cfgsw = QIXIS_READ(cms[1]);
|
||||
|
||||
puts("DIP switch settings dump:\n");
|
||||
for (i = 1; i <= nr_of_cfgsw; i++) {
|
||||
QIXIS_WRITE(cms[0], i);
|
||||
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
|
||||
}
|
||||
}
|
||||
|
|
@ -3,6 +3,7 @@ CONFIG_TARGET_LS1012AFRWY=y
|
|||
CONFIG_SYS_TEXT_BASE=0x40100000
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -28,7 +29,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_BLK is not set
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
|
|
@ -40,6 +41,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1012AFRWY=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40100000
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -29,7 +30,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
|
|||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_BLK is not set
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
|
|
@ -41,6 +42,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ CONFIG_SECURE_BOOT=y
|
|||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -28,7 +29,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_BLK is not set
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
|
|
@ -40,6 +41,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x82000000
|
|||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -29,7 +30,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
|
|||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
# CONFIG_BLK is not set
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
|
|
@ -41,6 +42,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AIOT=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40010000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
|
||||
CONFIG_MISC_INIT_R=y
|
||||
|
|
@ -15,7 +16,9 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
|
|
@ -28,6 +31,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
@ -36,4 +40,3 @@ CONFIG_FSL_QSPI=y
|
|||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ CONFIG_TARGET_LS1021AIOT=y
|
|||
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
|
||||
CONFIG_MISC_INIT_R=y
|
||||
|
|
@ -20,7 +21,9 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
|
|
@ -33,6 +36,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
@ -41,4 +45,3 @@ CONFIG_FSL_QSPI=y
|
|||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -33,7 +34,9 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
|
|
@ -47,6 +50,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SPECIFY_CONSOLE_INDEX=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -34,7 +35,9 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
|
|
@ -48,6 +51,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_USB=y
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -48,8 +49,10 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
|
|
@ -63,6 +66,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -34,7 +35,9 @@ CONFIG_CMD_FAT=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
|
|
@ -48,6 +51,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -33,8 +34,10 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
|
|
@ -48,6 +51,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SPECIFY_CONSOLE_INDEX=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -34,8 +35,10 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
|
|
@ -49,6 +52,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_USB=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40100000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -34,8 +35,10 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
@ -47,6 +50,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ CONFIG_SPL_MMC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -46,8 +47,10 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
|
|
@ -61,6 +64,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ CONFIG_SPL_MMC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -45,8 +46,10 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
@ -58,6 +61,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1021ATWR=y
|
||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -29,6 +30,7 @@ CONFIG_CMD_BMP=y
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -43,6 +45,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021ATWR=y
|
||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -30,6 +31,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -45,6 +47,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_USB=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1021ATWR=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40100000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -31,6 +32,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -45,6 +47,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -41,6 +42,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -56,6 +58,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -41,6 +42,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -55,6 +57,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1043AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -30,6 +31,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -44,6 +46,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_SPI=y
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ CONFIG_FSL_LS_PPA=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -44,6 +45,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -58,6 +60,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1043AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -29,6 +30,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_DM_MMC=y
|
||||
|
|
@ -44,6 +46,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1043AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40100000
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -29,6 +30,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -39,6 +41,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -44,6 +45,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -58,6 +60,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -42,6 +43,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -52,6 +54,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ CONFIG_SECURE_BOOT=y
|
|||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -31,6 +32,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x82000000
|
|||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -34,6 +35,7 @@ CONFIG_ENV_IS_IN_MMC=y
|
|||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1046AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT=y
|
||||
|
|
@ -30,6 +31,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:2m@0x100000(nor_bank0_uboot),40m@
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -43,6 +45,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1046AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x60100000
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -31,6 +32,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart"
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -45,6 +47,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_SPI=y
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x82000000
|
|||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -37,6 +38,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -51,6 +53,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ CONFIG_ARM=y
|
|||
CONFIG_TARGET_LS1046AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40100000
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -29,6 +30,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -40,6 +42,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -46,6 +47,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -60,6 +62,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -44,6 +45,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -55,6 +57,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -41,6 +42,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -52,6 +54,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x40100000
|
|||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_QSPI_AHB_INIT=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -26,6 +27,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
|
|
@ -37,6 +39,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ CONFIG_QSPI_AHB_INIT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -44,7 +45,9 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
|
|||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SPL_ENV_IS_NOWHERE=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
@ -54,6 +57,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -40,6 +41,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -51,6 +53,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ CONFIG_QSPI_AHB_INIT=y
|
|||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -27,6 +28,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:1m(rcw),15m(u-boot),48m(kernel
|
|||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
|
|
@ -38,6 +40,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x20100000
|
|||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_QSPI_AHB_INIT=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -29,6 +30,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds"
|
|||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
|
|
@ -41,6 +43,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ CONFIG_TARGET_LS1088AQDS=y
|
|||
CONFIG_SYS_TEXT_BASE=0x20100000
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_QSPI_AHB_INIT=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -29,6 +30,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
|
|
@ -41,6 +43,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
|
|
@ -38,6 +39,7 @@ CONFIG_ENV_IS_IN_MMC=y
|
|||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -50,6 +52,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -39,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y
|
|||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
|
|
@ -51,6 +53,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ CONFIG_QSPI_AHB_INIT=y
|
|||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -34,6 +35,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -50,6 +52,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x20100000
|
|||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_QSPI_AHB_INIT=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -30,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
|
|||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
|
|
@ -42,6 +44,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -40,6 +41,7 @@ CONFIG_ENV_IS_IN_MMC=y
|
|||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
|
|
@ -52,6 +54,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ CONFIG_QSPI_AHB_INIT=y
|
|||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -32,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb"
|
|||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
|
|
@ -44,6 +46,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ CONFIG_QSPI_AHB_INIT=y
|
|||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
|
|
@ -33,6 +34,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
|
|
@ -45,6 +47,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ CONFIG_TARGET_LS2080AQDS=y
|
|||
CONFIG_SYS_TEXT_BASE=0x30100000
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -31,6 +32,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -47,6 +49,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -41,6 +42,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
|
|||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -54,6 +56,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS2080AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x20100000
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -32,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
|
|||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -45,6 +47,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
|
|
@ -40,6 +41,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
|
|||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
|
|
@ -52,6 +54,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ CONFIG_TARGET_LS2080ARDB=y
|
|||
CONFIG_SYS_TEXT_BASE=0x30100000
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -31,6 +32,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -46,6 +48,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_CONS_INDEX=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -39,6 +40,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
|
|||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -54,6 +56,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_CONS_INDEX=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ CONFIG_TARGET_LS2081ARDB=y
|
|||
CONFIG_SYS_TEXT_BASE=0x20100000
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_QSPI_AHB_INIT=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -30,7 +31,9 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SCSI_AHCI=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
@ -42,6 +45,7 @@ CONFIG_DM_PCI=y
|
|||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_CONS_INDEX=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x82000000
|
|||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -35,6 +36,7 @@ CONFIG_ENV_IS_IN_MMC=y
|
|||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -51,6 +53,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x20100000
|
|||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_QSPI_AHB_INIT=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -26,6 +27,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
|
|
@ -40,6 +42,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_CONS_INDEX=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ CONFIG_TARGET_LS2080ARDB=y
|
|||
CONFIG_SYS_TEXT_BASE=0x20100000
|
||||
CONFIG_FSL_LS_PPA=y
|
||||
CONFIG_QSPI_AHB_INIT=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -29,6 +30,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
|
|||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -44,6 +46,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_CONS_INDEX=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ CONFIG_QSPI_AHB_INIT=y
|
|||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -34,6 +35,7 @@ CONFIG_OF_CONTROL=y
|
|||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
|
|
@ -51,6 +53,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_CONS_INDEX=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ CONFIG_QSPI_AHB_INIT=y
|
|||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -36,6 +37,7 @@ CONFIG_ENV_IS_IN_MMC=y
|
|||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
|
|
@ -55,6 +57,7 @@ CONFIG_PCI=y
|
|||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_CONS_INDEX=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
|
|
|
|||
58
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
Normal file
58
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LX2160AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_AQUANTIA=y
|
||||
CONFIG_PHY_CORTINA=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_DSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_RSA_SOFTWARE_EXP=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
53
configs/lx2160aqds_tfa_defconfig
Normal file
53
configs/lx2160aqds_tfa_defconfig
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LX2160AQDS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_AQUANTIA=y
|
||||
CONFIG_PHY_CORTINA=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
55
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
Normal file
55
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LX2160ARDB=y
|
||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||
CONFIG_SECURE_BOOT=y
|
||||
CONFIG_EMC2305=y
|
||||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_AQUANTIA=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_CORTINA=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_RSA_SOFTWARE_EXP=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
53
configs/lx2160ardb_tfa_defconfig
Normal file
53
configs/lx2160ardb_tfa_defconfig
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LX2160ARDB=y
|
||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x6000
|
||||
CONFIG_EMC2305=y
|
||||
CONFIG_TFABOOT=y
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
|
||||
# CONFIG_USE_BOOTCOMMAND is not set
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_AQUANTIA=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_CORTINA=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
|
||||
|
|
@ -22,9 +22,12 @@
|
|||
*/
|
||||
|
||||
/* Board-specific functions defined in each board's ddr.c */
|
||||
extern void fsl_ddr_board_options(memctl_options_t *popts,
|
||||
void __weak fsl_ddr_board_options(memctl_options_t *popts,
|
||||
dimm_params_t *pdimm,
|
||||
unsigned int ctrl_num);
|
||||
unsigned int ctrl_num)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
struct dynamic_odt {
|
||||
unsigned int odt_rd_cfg;
|
||||
|
|
|
|||
|
|
@ -6,7 +6,6 @@
|
|||
#ifndef __LS1012A_COMMON_H
|
||||
#define __LS1012A_COMMON_H
|
||||
|
||||
#define CONFIG_FSL_LAYERSCAPE
|
||||
#define CONFIG_GICV2
|
||||
|
||||
#include <asm/arch/config.h>
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@
|
|||
#endif
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
#define CONFIG_FSL_LAYERSCAPE
|
||||
#define CONFIG_GICV2
|
||||
|
||||
#include <asm/arch/stream_id_lsch2.h>
|
||||
|
|
@ -209,7 +208,7 @@
|
|||
*/
|
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
|
||||
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
|
||||
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00)
|
||||
#elif defined(CONFIG_QSPI_BOOT)
|
||||
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
|
||||
|
|
@ -255,6 +254,8 @@
|
|||
"fdtheader_addr_r=0x80100000\0" \
|
||||
"kernelheader_addr_r=0x80200000\0" \
|
||||
"kernel_addr_r=0x81000000\0" \
|
||||
"kernel_start=0x1000000\0" \
|
||||
"kernelheader_start=0x800000\0" \
|
||||
"fdt_addr_r=0x90000000\0" \
|
||||
"load_addr=0xa0000000\0" \
|
||||
"kernelheader_addr=0x60800000\0" \
|
||||
|
|
@ -306,6 +307,12 @@
|
|||
"&& cp.b $kernelheader_addr $kernelheader_addr_r " \
|
||||
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
|
||||
"bootm $load_addr#$board\0" \
|
||||
"nand_bootcmd=echo Trying load from NAND..;" \
|
||||
"nand info; nand read $load_addr " \
|
||||
"$kernel_start $kernel_size; env exists secureboot " \
|
||||
"&& nand read $kernelheader_addr_r $kernelheader_start " \
|
||||
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
|
||||
"bootm $load_addr#$board\0" \
|
||||
"sd_bootcmd=echo Trying load from SD ..;" \
|
||||
"mmcinfo; mmc read $load_addr " \
|
||||
"$kernel_addr_sd $kernel_size_sd && " \
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@
|
|||
#endif
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
#define CONFIG_FSL_LAYERSCAPE
|
||||
#define CONFIG_GICV2
|
||||
|
||||
#include <asm/arch/config.h>
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@
|
|||
#endif
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
#define CONFIG_FSL_LAYERSCAPE
|
||||
|
||||
#include <asm/arch/stream_id_lsch3.h>
|
||||
#include <asm/arch/config.h>
|
||||
|
|
|
|||
|
|
@ -8,9 +8,7 @@
|
|||
#define __LS2_COMMON_H
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
#define CONFIG_FSL_LAYERSCAPE
|
||||
#define CONFIG_GICV3
|
||||
#define CONFIG_FSL_TZPC_BP147
|
||||
|
||||
#include <asm/arch/stream_id_lsch3.h>
|
||||
#include <asm/arch/config.h>
|
||||
|
|
|
|||
289
include/configs/lx2160a_common.h
Normal file
289
include/configs/lx2160a_common.h
Normal file
|
|
@ -0,0 +1,289 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __LX2_COMMON_H
|
||||
#define __LX2_COMMON_H
|
||||
|
||||
#include <asm/arch/stream_id_lsch3.h>
|
||||
#include <asm/arch/config.h>
|
||||
#include <asm/arch/soc.h>
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
#define CONFIG_FSL_LAYERSCAPE
|
||||
#define CONFIG_GICV3
|
||||
#define CONFIG_FSL_TZPC_BP147
|
||||
#define CONFIG_FSL_MEMAC
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_FLASH_BASE 0x20000000
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1
|
||||
|
||||
/* DDR */
|
||||
#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
|
||||
#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
|
||||
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
|
||||
#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
|
||||
#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
|
||||
#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_DDR_ECC
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#define SPD_EEPROM_ADDRESS1 0x51
|
||||
#define SPD_EEPROM_ADDRESS2 0x52
|
||||
#define SPD_EEPROM_ADDRESS3 0x53
|
||||
#define SPD_EEPROM_ADDRESS4 0x54
|
||||
#define SPD_EEPROM_ADDRESS5 0x55
|
||||
#define SPD_EEPROM_ADDRESS6 0x56
|
||||
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
|
||||
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
|
||||
#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
|
||||
|
||||
/* SMP Definitinos */
|
||||
#define CPU_RELEASE_ADDR secondary_boot_func
|
||||
|
||||
/* Generic Timer Definitions */
|
||||
/*
|
||||
* This is not an accurate number. It is used in start.S. The frequency
|
||||
* will be udpated later when get_bus_freq(0) is available.
|
||||
*/
|
||||
|
||||
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_PL01X_SERIAL
|
||||
#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
|
||||
#define CONFIG_SYS_SERIAL0 0x21c0000
|
||||
#define CONFIG_SYS_SERIAL1 0x21d0000
|
||||
#define CONFIG_SYS_SERIAL2 0x21e0000
|
||||
#define CONFIG_SYS_SERIAL3 0x21f0000
|
||||
/*below might needs to be removed*/
|
||||
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
|
||||
(void *)CONFIG_SYS_SERIAL1, \
|
||||
(void *)CONFIG_SYS_SERIAL2, \
|
||||
(void *)CONFIG_SYS_SERIAL3 }
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/* MC firmware */
|
||||
#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
|
||||
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
|
||||
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
|
||||
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
|
||||
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
|
||||
|
||||
/* Define phy_reset function to boot the MC based on mcinitcmd.
|
||||
* This happens late enough to properly fixup u-boot env MAC addresses.
|
||||
*/
|
||||
#define CONFIG_RESET_PHY_R
|
||||
|
||||
/*
|
||||
* Carve out a DDR region which will not be used by u-boot/Linux
|
||||
*
|
||||
* It will be used by MC and Debug Server. The MC region must be
|
||||
* 512MB aligned, so the min size to hide is 512MB.
|
||||
*/
|
||||
#ifdef CONFIG_FSL_MC_ENET
|
||||
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
|
||||
#endif
|
||||
|
||||
/* I2C bus multiplexer */
|
||||
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
|
||||
#define I2C_MUX_CH_DEFAULT 0x8
|
||||
|
||||
/* RTC */
|
||||
#define RTC
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/* Qixis */
|
||||
#define CONFIG_FSL_QIXIS
|
||||
#define CONFIG_QIXIS_I2C_ACCESS
|
||||
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
|
||||
|
||||
/* PCI */
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_SYS_PCI_64BIT
|
||||
#define CONFIG_PCI_SCAN_SHOW
|
||||
#endif
|
||||
|
||||
/* MMC */
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
||||
#endif
|
||||
|
||||
/* SATA */
|
||||
|
||||
#ifdef CONFIG_SCSI
|
||||
#define CONFIG_SCSI_AHCI_PLAT
|
||||
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
|
||||
#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
|
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
|
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1
|
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
|
||||
CONFIG_SYS_SCSI_MAX_LUN)
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#ifdef CONFIG_USB
|
||||
#define CONFIG_HAS_FSL_XHCI_USB
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#endif
|
||||
|
||||
/* FlexSPI */
|
||||
#ifdef CONFIG_NXP_FSPI
|
||||
#define NXP_FSPI_FLASH_SIZE SZ_64M
|
||||
#define NXP_FSPI_FLASH_NUM 1
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
unsigned long get_board_sys_clk(void);
|
||||
unsigned long get_board_ddr_clk(void);
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
|
||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
|
||||
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
#define HWCONFIG_BUFFER_SIZE 128
|
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_OFFSET 0x500000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
|
||||
CONFIG_ENV_OFFSET)
|
||||
|
||||
/* Allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
#define CONFIG_SYS_MAXARGS 64 /* max command args */
|
||||
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
/* Initial environment variables */
|
||||
#define XSPI_MC_INIT_CMD \
|
||||
"env exists secureboot && " \
|
||||
"esbc_validate 0x20700000 && " \
|
||||
"esbc_validate 0x20740000 ;" \
|
||||
"fsl_mc start mc 0x20a00000 0x20e00000\0"
|
||||
|
||||
#define SD_MC_INIT_CMD \
|
||||
"mmc read 0x80000000 0x5000 0x800;" \
|
||||
"mmc read 0x80100000 0x7000 0x800;" \
|
||||
"env exists secureboot && " \
|
||||
"mmc read 0x80700000 0x3800 0x10 && " \
|
||||
"mmc read 0x80740000 0x3A00 0x10 && " \
|
||||
"esbc_validate 0x80700000 && " \
|
||||
"esbc_validate 0x80740000 ;" \
|
||||
"fsl_mc start mc 0x80000000 0x80100000\0"
|
||||
|
||||
#define EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
||||
"ramdisk_addr=0x800000\0" \
|
||||
"ramdisk_size=0x2000000\0" \
|
||||
"fdt_high=0xa0000000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"fdt_addr=0x64f00000\0" \
|
||||
"kernel_start=0x1000000\0" \
|
||||
"kernelheader_start=0x7C0000\0" \
|
||||
"scriptaddr=0x80000000\0" \
|
||||
"scripthdraddr=0x80080000\0" \
|
||||
"fdtheader_addr_r=0x80100000\0" \
|
||||
"kernelheader_addr_r=0x80200000\0" \
|
||||
"kernel_addr_r=0x81000000\0" \
|
||||
"kernelheader_size=0x40000\0" \
|
||||
"fdt_addr_r=0x90000000\0" \
|
||||
"load_addr=0xa0000000\0" \
|
||||
"kernel_size=0x2800000\0" \
|
||||
"kernel_addr_sd=0x8000\0" \
|
||||
"kernelhdr_addr_sd=0x3E00\0" \
|
||||
"kernel_size_sd=0x1d000\0" \
|
||||
"kernelhdr_size_sd=0x10\0" \
|
||||
"console=ttyAMA0,38400n8\0" \
|
||||
BOOTENV \
|
||||
"mcmemsize=0x70000000\0" \
|
||||
XSPI_MC_INIT_CMD \
|
||||
"boot_scripts=lx2160ardb_boot.scr\0" \
|
||||
"boot_script_hdr=hdr_lx2160ardb_bs.out\0" \
|
||||
"scan_dev_for_boot_part=" \
|
||||
"part list ${devtype} ${devnum} devplist; " \
|
||||
"env exists devplist || setenv devplist 1; " \
|
||||
"for distro_bootpart in ${devplist}; do " \
|
||||
"if fstype ${devtype} " \
|
||||
"${devnum}:${distro_bootpart} " \
|
||||
"bootfstype; then " \
|
||||
"run scan_dev_for_boot; " \
|
||||
"fi; " \
|
||||
"done\0" \
|
||||
"scan_dev_for_boot=" \
|
||||
"echo Scanning ${devtype} " \
|
||||
"${devnum}:${distro_bootpart}...; " \
|
||||
"for prefix in ${boot_prefixes}; do " \
|
||||
"run scan_dev_for_scripts; " \
|
||||
"done;\0" \
|
||||
"boot_a_script=" \
|
||||
"load ${devtype} ${devnum}:${distro_bootpart} " \
|
||||
"${scriptaddr} ${prefix}${script}; " \
|
||||
"env exists secureboot && load ${devtype} " \
|
||||
"${devnum}:${distro_bootpart} " \
|
||||
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
|
||||
"&& esbc_validate ${scripthdraddr};" \
|
||||
"source ${scriptaddr}\0"
|
||||
|
||||
#define XSPI_NOR_BOOTCOMMAND \
|
||||
"env exists mcinitcmd && env exists secureboot "\
|
||||
"&& esbc_validate 0x20780000; " \
|
||||
"env exists mcinitcmd && " \
|
||||
"fsl_mc lazyapply dpl 0x20d00000; " \
|
||||
"run distro_bootcmd;run xspi_bootcmd; " \
|
||||
"env exists secureboot && esbc_halt;"
|
||||
|
||||
#define SD_BOOTCOMMAND \
|
||||
"env exists mcinitcmd && mmcinfo; " \
|
||||
"mmc read 0x80001000 0x6800 0x800; " \
|
||||
"env exists mcinitcmd && env exists secureboot " \
|
||||
" && mmc read 0x80780000 0x3C00 0x10 " \
|
||||
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
|
||||
"&& fsl_mc lazyapply dpl 0x80001000;" \
|
||||
"run distro_bootcmd;run sd_bootcmd;" \
|
||||
"env exists secureboot && esbc_halt;"
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(USB, usb, 0) \
|
||||
func(MMC, mmc, 0) \
|
||||
func(SCSI, scsi, 0)
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
#endif /* __LX2_COMMON_H */
|
||||
140
include/configs/lx2160aqds.h
Normal file
140
include/configs/lx2160aqds.h
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018-2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __LX2_QDS_H
|
||||
#define __LX2_QDS_H
|
||||
|
||||
#include "lx2160a_common.h"
|
||||
|
||||
/* Qixis */
|
||||
#define QIXIS_XMAP_MASK 0x07
|
||||
#define QIXIS_XMAP_SHIFT 5
|
||||
#define QIXIS_RST_CTL_RESET_EN 0x30
|
||||
#define QIXIS_LBMAP_DFLTBANK 0x00
|
||||
#define QIXIS_LBMAP_ALTBANK 0x20
|
||||
#define QIXIS_LBMAP_QSPI 0x00
|
||||
#define QIXIS_RCW_SRC_QSPI 0xff
|
||||
#define QIXIS_RST_CTL_RESET 0x31
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
|
||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
|
||||
#define QIXIS_LBMAP_MASK 0x0f
|
||||
#define QIXIS_LBMAP_SD
|
||||
#define QIXIS_RCW_SRC_SD 0x08
|
||||
#define NON_EXTENDED_DUTCFG
|
||||
#define QIXIS_SDID_MASK 0x07
|
||||
#define QIXIS_ESDHC_NO_ADAPTER 0x7
|
||||
|
||||
/* SYSCLK */
|
||||
#define QIXIS_SYSCLK_100 0x0
|
||||
#define QIXIS_SYSCLK_125 0x1
|
||||
#define QIXIS_SYSCLK_133 0x2
|
||||
|
||||
/* DDRCLK */
|
||||
#define QIXIS_DDRCLK_100 0x0
|
||||
#define QIXIS_DDRCLK_125 0x1
|
||||
#define QIXIS_DDRCLK_133 0x2
|
||||
|
||||
#define BRDCFG4_EMI1SEL_MASK 0xF8
|
||||
#define BRDCFG4_EMI1SEL_SHIFT 3
|
||||
#define BRDCFG4_EMI2SEL_MASK 0x07
|
||||
#define BRDCFG4_EMI2SEL_SHIFT 0
|
||||
|
||||
/* VID */
|
||||
|
||||
#define I2C_MUX_CH_VOL_MONITOR 0xA
|
||||
/* Voltage monitor on channel 2*/
|
||||
#define I2C_VOL_MONITOR_ADDR 0x63
|
||||
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
|
||||
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
|
||||
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
|
||||
#define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv"
|
||||
#define CONFIG_VID
|
||||
|
||||
/* The lowest and highest voltage allowed*/
|
||||
#define VDD_MV_MIN 775
|
||||
#define VDD_MV_MAX 925
|
||||
|
||||
/* PM Bus commands code for LTC3882*/
|
||||
#define PMBUS_CMD_PAGE 0x0
|
||||
#define PMBUS_CMD_READ_VOUT 0x8B
|
||||
#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
|
||||
#define PMBUS_CMD_VOUT_COMMAND 0x21
|
||||
#define PWM_CHANNEL0 0x0
|
||||
|
||||
#define CONFIG_VOL_MONITOR_LTC3882_SET
|
||||
#define CONFIG_VOL_MONITOR_LTC3882_READ
|
||||
|
||||
/* RTC */
|
||||
#define CONFIG_SYS_RTC_BUS_NUM 0
|
||||
#define I2C_MUX_CH_RTC 0xB
|
||||
|
||||
/*
|
||||
* MMC
|
||||
*/
|
||||
#ifdef CONFIG_MMC
|
||||
#ifndef __ASSEMBLY__
|
||||
u8 qixis_esdhc_detect_quirk(void);
|
||||
#endif
|
||||
#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()
|
||||
#endif
|
||||
|
||||
/* MAC/PHY configuration */
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
|
||||
|
||||
#define AQ_PHY_ADDR1 0x00
|
||||
#define AQ_PHY_ADDR2 0x01
|
||||
#define AQ_PHY_ADDR3 0x02
|
||||
#define AQ_PHY_ADDR4 0x03
|
||||
|
||||
#define CORTINA_NO_FW_UPLOAD
|
||||
#define CORTINA_PHY_ADDR1 0x0
|
||||
|
||||
#define INPHI_PHY_ADDR1 0x0
|
||||
#define INPHI_PHY_ADDR2 0x1
|
||||
|
||||
#define RGMII_PHY_ADDR1 0x01
|
||||
#define RGMII_PHY_ADDR2 0x02
|
||||
|
||||
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
|
||||
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
|
||||
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
|
||||
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
|
||||
|
||||
#endif
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
EXTRA_ENV_SETTINGS \
|
||||
"lx2160aqds_vdd_mv=800\0" \
|
||||
"BOARD=lx2160aqds\0" \
|
||||
"xspi_bootcmd=echo Trying load from flexspi..;" \
|
||||
"sf probe 0:0 && sf read $load_addr " \
|
||||
"$kernel_start $kernel_size ; env exists secureboot &&" \
|
||||
"sf read $kernelheader_addr_r $kernelheader_start " \
|
||||
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
|
||||
" bootm $load_addr#$BOARD\0" \
|
||||
"sd_bootcmd=echo Trying load from sd card..;" \
|
||||
"mmcinfo; mmc read $load_addr " \
|
||||
"$kernel_addr_sd $kernel_size_sd ;" \
|
||||
"env exists secureboot && mmc read $kernelheader_addr_r "\
|
||||
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
|
||||
" && esbc_validate ${kernelheader_addr_r};" \
|
||||
"bootm $load_addr#$BOARD\0"
|
||||
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
|
||||
#endif /* __LX2_QDS_H */
|
||||
109
include/configs/lx2160ardb.h
Normal file
109
include/configs/lx2160ardb.h
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __LX2_RDB_H
|
||||
#define __LX2_RDB_H
|
||||
|
||||
#include "lx2160a_common.h"
|
||||
|
||||
/* Qixis */
|
||||
#define QIXIS_XMAP_MASK 0x07
|
||||
#define QIXIS_XMAP_SHIFT 5
|
||||
#define QIXIS_RST_CTL_RESET_EN 0x30
|
||||
#define QIXIS_LBMAP_DFLTBANK 0x00
|
||||
#define QIXIS_LBMAP_ALTBANK 0x20
|
||||
#define QIXIS_LBMAP_QSPI 0x00
|
||||
#define QIXIS_RCW_SRC_QSPI 0xff
|
||||
#define QIXIS_RST_CTL_RESET 0x31
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
|
||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
|
||||
#define QIXIS_LBMAP_MASK 0x0f
|
||||
#define QIXIS_LBMAP_SD
|
||||
#define QIXIS_RCW_SRC_SD 0x08
|
||||
#define NON_EXTENDED_DUTCFG
|
||||
|
||||
/* VID */
|
||||
|
||||
#define I2C_MUX_CH_VOL_MONITOR 0xA
|
||||
/* Voltage monitor on channel 2*/
|
||||
#define I2C_VOL_MONITOR_ADDR 0x63
|
||||
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
|
||||
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
|
||||
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
|
||||
#define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv"
|
||||
#define CONFIG_VID
|
||||
|
||||
/* The lowest and highest voltage allowed*/
|
||||
#define VDD_MV_MIN 775
|
||||
#define VDD_MV_MAX 855
|
||||
|
||||
/* PM Bus commands code for LTC3882*/
|
||||
#define PMBUS_CMD_PAGE 0x0
|
||||
#define PMBUS_CMD_READ_VOUT 0x8B
|
||||
#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
|
||||
#define PMBUS_CMD_VOUT_COMMAND 0x21
|
||||
#define PWM_CHANNEL0 0x0
|
||||
|
||||
#define CONFIG_VOL_MONITOR_LTC3882_SET
|
||||
#define CONFIG_VOL_MONITOR_LTC3882_READ
|
||||
|
||||
/* RTC */
|
||||
#define CONFIG_SYS_RTC_BUS_NUM 4
|
||||
|
||||
/* MAC/PHY configuration */
|
||||
#if defined(CONFIG_FSL_MC_ENET)
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
|
||||
|
||||
#define AQR107_PHY_ADDR1 0x04
|
||||
#define AQR107_PHY_ADDR2 0x05
|
||||
|
||||
#define CORTINA_NO_FW_UPLOAD
|
||||
#define CORTINA_PHY_ADDR1 0x0
|
||||
#define INPHI_PHY_ADDR1 0x0
|
||||
|
||||
#define RGMII_PHY_ADDR1 0x01
|
||||
#define RGMII_PHY_ADDR2 0x02
|
||||
|
||||
#endif
|
||||
|
||||
/* EMC2305 */
|
||||
#define I2C_MUX_CH_EMC2305 0x09
|
||||
#define I2C_EMC2305_ADDR 0x4D
|
||||
#define I2C_EMC2305_CMD 0x40
|
||||
#define I2C_EMC2305_PWM 0x80
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
EXTRA_ENV_SETTINGS \
|
||||
"lx2160ardb_vdd_mv=800\0" \
|
||||
"BOARD=lx2160ardb\0" \
|
||||
"xspi_bootcmd=echo Trying load from flexspi..;" \
|
||||
"sf probe 0:0 && sf read $load_addr " \
|
||||
"$kernel_start $kernel_size ; env exists secureboot &&" \
|
||||
"sf read $kernelheader_addr_r $kernelheader_start " \
|
||||
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
|
||||
" bootm $load_addr#$BOARD\0" \
|
||||
"sd_bootcmd=echo Trying load from sd card..;" \
|
||||
"mmcinfo; mmc read $load_addr " \
|
||||
"$kernel_addr_sd $kernel_size_sd ;" \
|
||||
"env exists secureboot && mmc read $kernelheader_addr_r "\
|
||||
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
|
||||
" && esbc_validate ${kernelheader_addr_r};" \
|
||||
"bootm $load_addr#$BOARD\0"
|
||||
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
|
||||
#endif /* __LX2_RDB_H */
|
||||
|
|
@ -643,7 +643,6 @@ CONFIG_FSL_I2C_CUSTOM_DFSR
|
|||
CONFIG_FSL_I2C_CUSTOM_FDR
|
||||
CONFIG_FSL_IIM
|
||||
CONFIG_FSL_ISBC_KEY_EXT
|
||||
CONFIG_FSL_LAYERSCAPE
|
||||
CONFIG_FSL_LBC
|
||||
CONFIG_FSL_MC9SDZ60
|
||||
CONFIG_FSL_MEMAC
|
||||
|
|
@ -670,8 +669,6 @@ CONFIG_FSL_SGMII_RISER
|
|||
CONFIG_FSL_SPI_INTERFACE
|
||||
CONFIG_FSL_TBCLK_EXTRA_DIV
|
||||
CONFIG_FSL_TRUST_ARCH_v1
|
||||
CONFIG_FSL_TZASC_400
|
||||
CONFIG_FSL_TZPC_BP147
|
||||
CONFIG_FSL_USDHC
|
||||
CONFIG_FSL_VIA
|
||||
CONFIG_FSMC_NAND_BASE
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue