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[MIPS] Replace memory clearance code with f_fill64

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This routine fills memory with zero by 64 bytes, and is 64-bit capable.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This commit is contained in:
Shinya Kuribayashi 2008-03-25 21:30:06 +09:00
parent 2f5d414ccb
commit 1898840797
1 changed files with 28 additions and 15 deletions
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43
cpu/mips/cache.S
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@ -104,6 +104,27 @@
#define icacheop(kva, n, cacheSize, cacheLineSize, op) \ #define icacheop(kva, n, cacheSize, cacheLineSize, op) \
icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
.macro f_fill64 dst, offset, val
LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
#if LONGSIZE == 4
LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
#endif
.endm
/******************************************************************************* /*******************************************************************************
* *
* mips_cache_reset - low level initialisation of the primary caches * mips_cache_reset - low level initialisation of the primary caches
@ -128,22 +149,14 @@ NESTED(mips_cache_reset, 0, ra)
li v0, MIPS_MAX_CACHE_SIZE li v0, MIPS_MAX_CACHE_SIZE
/* Now clear that much memory starting from zero. /*
* Now clear that much memory starting from zero.
*/ */
PTR_LI a0, KSEG1
li a0, KSEG1 PTR_ADDU a1, a0, v0
addu a1, a0, v0 2: PTR_ADDIU a0, 64
2: f_fill64 a0, -64, zero
sw zero, 0(a0) bne a0, a1, 2b
sw zero, 4(a0)
sw zero, 8(a0)
sw zero, 12(a0)
sw zero, 16(a0)
sw zero, 20(a0)
sw zero, 24(a0)
sw zero, 28(a0)
addu a0, 32
bltu a0, a1, 2b
/* Set invalid tag. /* Set invalid tag.
*/ */