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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

Browse source 
- Add DM model for P1010RDB
- Add I2C DM Model support for P1010RDB, T1042RDB, T2080, T4240RDB,
  MPC8548CDS, T1024RDB, P4080, P3041DS, P2041RDB, P2020RDB, P1020RDB,
  P5040DS
- Fix reference to READM.qe_firmware
This commit is contained in:
Tom Rini 2020-05-05 09:08:53 -04:00
commit 191ee8aac6
128 changed files with 1580 additions and 83 deletions
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2
arch/powerpc/dts/Makefile
View file

@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb

17
arch/powerpc/dts/p1010rdb-pa.dts Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 RDB Device Tree Source
*
* Copyright 2020 NXP
*/
/include/ "p1010si-pre.dtsi"
/ {
model = "fsl,P1010RDB";
compatible = "fsl,P1010RDB";
/include/ "p1010rdb_32b.dtsi"
};
/include/ "p1010si-post.dtsi"

17
arch/powerpc/dts/p1010rdb-pa_36b.dts Normal file
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@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 RDB Device Tree Source (36-bit address map)
*
* Copyright 2020 NXP
*/
/include/ "p1010si-pre.dtsi"
/ {
model = "fsl,P1010RDB";
compatible = "fsl,P1010RDB";
/include/ "p1010rdb_36b.dtsi"
};
/include/ "p1010si-post.dtsi"

18
arch/powerpc/dts/p1010rdb-pb.dts Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010RDB Device Tree Source
*
* Copyright 2020 NXP
*/
/include/ "p1010si-pre.dtsi"
/ {
model = "fsl,P1010RDB-PB";
compatible = "fsl,P1010RDB-PB";
/include/ "p1010rdb_32b.dtsi"
};
/include/ "p1010si-post.dtsi"
/include/ "p1010rdb.dtsi"

18
arch/powerpc/dts/p1010rdb-pb_36b.dts Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 RDB Device Tree Source (36-bit address map)
*
* Copyright 2020 NXP
*/
/include/ "p1010si-pre.dtsi"
/ {
model = "fsl,P1010RDB-PB";
compatible = "fsl,P1010RDB-PB";
/include/ "p1010rdb_36b.dtsi"
};
/include/ "p1010si-post.dtsi"
/include/ "p1010rdb.dtsi"

14
arch/powerpc/dts/p1010rdb.dtsi Normal file
View file

@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010RDB Device Tree Source
*
* Copyright 2020 NXP
*/
&soc {
i2c@3000 {
rtc@68 {
compatible = "pericom,pt7c4338";
reg = <0x68>;
};
};
};

22
arch/powerpc/dts/p1010rdb_32b.dtsi Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010RDB Device Tree Source
*
* Copyright 2020 NXP
*/
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci1: pcie@ffe09000 {
reg = <0 0xffe09000 0 0x1000>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
};
pci0: pcie@ffe0a000 {
reg = <0 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
};

22
arch/powerpc/dts/p1010rdb_36b.dtsi Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010RDB Device Tree Source (36-bit address map)
*
* Copyright 2020 NXP
*/
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
pci1: pcie@fffe09000 {
reg = <0xf 0xffe09000 0 0x1000>;
ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
};
pci0: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
};

48
arch/powerpc/dts/p1010si-post.dtsi Normal file
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@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2020 NXP
*/
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p1010-immr", "simple-bus";
bus-frequency = <0>;
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic";
device_type = "open-pic";
big-endian;
single-cpu-affinity;
last-interrupt-source = <255>;
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
};
/* controller at 0x9000 */
&pci1 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};
/* controller at 0xa000 */
&pci0 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};

27
arch/powerpc/dts/p1010si-pre.dtsi Normal file
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@ -0,0 +1,27 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1010 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2020 NXP
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
compatible = "fsl,P1010";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,P1010@0 {
device_type = "cpu";
reg = <0x0>;
};
};
};

2
arch/powerpc/dts/p1020-post.dtsi
View file

@ -44,6 +44,8 @@
clock-frequency = <0>;
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
};
/* PCIe controller base address 0x9000 */

3
arch/powerpc/dts/p2020-post.dtsi
View file

@ -37,6 +37,9 @@
/* Filled in by U-Boot */
clock-frequency = <0>;
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
};
/* PCIe controller base address 0x8000 */

5
arch/powerpc/dts/p2041.dtsi
View file

@ -3,7 +3,7 @@
* P2041 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -86,6 +86,9 @@
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe200000 {

4
arch/powerpc/dts/p3041.dtsi
View file

@ -3,7 +3,7 @@
* P3041 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2010 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -86,6 +86,8 @@
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe200000 {

4
arch/powerpc/dts/p4080.dtsi
View file

@ -3,7 +3,7 @@
* P4080/P4040 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -97,6 +97,8 @@
reg = <0x211000 0x1000>;
phy_type = "ulpi";
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe200000 {

5
arch/powerpc/dts/p5040.dtsi
View file

@ -3,7 +3,7 @@
* P5040 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -85,6 +85,9 @@
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe200000 {

15
arch/powerpc/dts/pq3-i2c-0.dtsi Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 I2C Device Tree stub
*
* Copyright 2020 NXP
*/
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
u-boot,dm-pre-reloc;
reg = <0x3000 0x100>;
interrupts = <43 2 0 0>;
};

15
arch/powerpc/dts/pq3-i2c-1.dtsi Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 I2C Device Tree stub
*
* Copyright 2020 NXP
*/
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
u-boot,dm-pre-reloc;
reg = <0x3100 0x100>;
interrupts = <43 2 0 0>;
};

25
arch/powerpc/dts/qoriq-i2c-0.dtsi Normal file
View file

@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* QorIQ I2C Device Tree stub
*
* Copyright 2020 NXP
*/
i2c0: i2c@118000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
u-boot,dm-pre-reloc;
reg = <0x118000 0x100>;
interrupts = <38 2 0 0>;
};
i2c1: i2c@118100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
u-boot,dm-pre-reloc;
reg = <0x118100 0x100>;
interrupts = <38 2 0 0>;
};

25
arch/powerpc/dts/qoriq-i2c-1.dtsi Normal file
View file

@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* QorIQ I2C Device Tree stub
*
* Copyright 2020 NXP
*/
i2c2: i2c@119000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <2>;
compatible = "fsl-i2c";
u-boot,dm-pre-reloc;
reg = <0x119000 0x100>;
interrupts = <39 2 0 0>;
};
i2c3: i2c@119100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <3>;
compatible = "fsl-i2c";
u-boot,dm-pre-reloc;
reg = <0x119100 0x100>;
interrupts = <39 2 0 0>;
};

4
arch/powerpc/dts/t102x.dtsi
View file

@ -3,7 +3,7 @@
* T102X Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -75,6 +75,8 @@
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe240000 {

4
arch/powerpc/dts/t104x.dtsi
View file

@ -3,7 +3,7 @@
* T104X Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -85,6 +85,8 @@
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe240000 {

4
arch/powerpc/dts/t2080.dtsi
View file

@ -3,7 +3,7 @@
* T2080/T2081 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2018 NXP
* Copyright 2018,2020 NXP
*/
/dts-v1/;
@ -96,6 +96,8 @@
sata-number = <2>;
sata-fpdma = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe240000 {

5
arch/powerpc/dts/t4240.dtsi
View file

@ -3,7 +3,7 @@
* T4240 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/dts-v1/;
@ -125,6 +125,9 @@
reg = <0x114000 0x1000>;
clock-frequency = <0>;
};
/include/ "qoriq-i2c-0.dtsi"
/include/ "qoriq-i2c-1.dtsi"
};
pcie@ffe240000 {

3
board/freescale/common/sys_eeprom.c
View file

@ -595,6 +595,7 @@ unsigned int get_cpu_board_revision(void)
(void *)&be, sizeof(be));
#else
struct udevice *dev;
int ret;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
CONFIG_SYS_I2C_EEPROM_ADDR,
@ -603,7 +604,7 @@ unsigned int get_cpu_board_revision(void)
#else
ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
&dev)
&dev);
#endif
if (!ret)
dm_i2c_read(dev, 0, (void *)&be, sizeof(be));

258
board/freescale/common/vsc3316_3308.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#include "vsc3316_3308.h"
@ -32,7 +33,22 @@ int vsc_if_enable(unsigned int vsc_addr)
/* enable 2-wire Serial InterFace (I2C) */
data = 0x02;
#ifdef CONFIG_DM_I2C
int ret, bus_num = 0;
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
return dm_i2c_write(dev, INTERFACE_MODE_REG, &data, 1);
#else
return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1);
#endif
}
int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
@ -45,6 +61,66 @@ int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
debug("VSC:Initializing VSC3316 at I2C address 0x%2x"
" for Tx\n", vsc_addr);
#ifdef CONFIG_DM_I2C
int bus_num = 0;
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1);
if (ret < 0) {
printf("VSC:0x%x could not read REV_ID from device.\n",
vsc_addr);
return ret;
}
if (rev_id != 0xab) {
printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
vsc_addr);
return -ENODEV;
}
ret = vsc_if_enable(vsc_addr);
if (ret) {
printf("VSC:0x%x could not configured for 2-wire I/F.\n",
vsc_addr);
return ret;
}
/* config connections - page 0x00 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
/* Making crosspoint connections, by connecting required
* input to output
*/
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]);
/* input state - page 0x13 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
/* Configuring the required input of the switch */
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][0], 0x80);
/* Setting Global Input LOS threshold value */
dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60);
/* config output mode - page 0x23 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
/* Turn ON the Output driver correspond to required output*/
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][1], 0);
/* configure global core control register, Turn on Global core power */
dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0);
#else
ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
if (ret < 0) {
printf("VSC:0x%x could not read REV_ID from device.\n",
@ -90,6 +166,7 @@ int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
/* configure global core control register, Turn on Global core power */
i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
#endif
vsc_wp_config(vsc_addr);
@ -107,6 +184,105 @@ int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n",
vsc_addr);
#ifdef CONFIG_DM_I2C
int bus_num = 0;
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1);
if (ret < 0) {
printf("VSC:0x%x could not read REV_ID from device.\n",
vsc_addr);
return ret;
}
if (rev_id != 0xab) {
printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
vsc_addr);
return -ENODEV;
}
ret = vsc_if_enable(vsc_addr);
if (ret) {
printf("VSC:0x%x could not configured for 2-wire I/F.\n",
vsc_addr);
return ret;
}
/* config connections - page 0x00 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
/* Configure Global Input ISE */
dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0);
dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0);
/* Configure Tx/Rx Global Output PE1 */
dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE1, 0);
/* Configure Tx/Rx Global Output PE2 */
dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE2, 0);
/* Configure Tx/Rx Global Input GAIN */
dm_i2c_reg_write(dev, GLOBAL_INPUT_GAIN, 0x3F);
/* Setting Global Input LOS threshold value */
dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0xE0);
/* Setting Global output termination */
dm_i2c_reg_write(dev, GLOBAL_OUTPUT_TERMINATION, 0);
/* Configure Tx/Rx Global Output level */
if (vsc_addr == VSC3308_TX_ADDRESS)
dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 4);
else
dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 2);
/* Making crosspoint connections, by connecting required
* input to output
*/
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]);
/* input state - page 0x13 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
/* Turning off all the required input of the switch */
for (i = 0; i < num_con; i++)
dm_i2c_reg_write(dev, con_arr[i][0], 1);
/* only turn on specific Tx/Rx requested by the XFI erratum */
if (vsc_addr == VSC3308_TX_ADDRESS) {
dm_i2c_reg_write(dev, 2, 0);
dm_i2c_reg_write(dev, 3, 0);
} else {
dm_i2c_reg_write(dev, 0, 0);
dm_i2c_reg_write(dev, 1, 0);
}
/* config output mode - page 0x23 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
/* Turn off the Output driver correspond to required output*/
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][1], 1);
/* only turn on specific Tx/Rx requested by the XFI erratum */
if (vsc_addr == VSC3308_TX_ADDRESS) {
dm_i2c_reg_write(dev, 0, 0);
dm_i2c_reg_write(dev, 1, 0);
} else {
dm_i2c_reg_write(dev, 3, 0);
dm_i2c_reg_write(dev, 4, 0);
}
/* configure global core control register, Turn on Global core power */
dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0);
#else
ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
if (ret < 0) {
printf("VSC:0x%x could not read REV_ID from device.\n",
@ -192,7 +368,7 @@ int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
/* configure global core control register, Turn on Global core power */
i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
#endif
vsc_wp_config(vsc_addr);
return 0;
@ -208,7 +384,69 @@ int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
debug("VSC:Initializing VSC3308 at I2C address 0x%x"
" for Tx\n", vsc_addr);
#ifdef CONFIG_DM_I2C
int bus_num = 0;
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1);
if (ret < 0) {
printf("VSC:0x%x could not read REV_ID from device.\n",
vsc_addr);
return ret;
}
if (rev_id != 0xab) {
printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
vsc_addr);
return -ENODEV;
}
ret = vsc_if_enable(vsc_addr);
if (ret) {
printf("VSC:0x%x could not configured for 2-wire I/F.\n",
vsc_addr);
return ret;
}
/* config connections - page 0x00 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
/* Making crosspoint connections, by connecting required
* input to output
*/
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]);
/*Configure Global Input ISE and gain */
dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0x12);
dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0x12);
/* input state - page 0x13 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
/* Turning ON the required input of the switch */
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][0], 0);
/* Setting Global Input LOS threshold value */
dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60);
/* config output mode - page 0x23 */
dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
/* Turn ON the Output driver correspond to required output*/
for (i = 0; i < num_con ; i++)
dm_i2c_reg_write(dev, con_arr[i][1], 0);
/* configure global core control register, Turn on Global core power */
dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0);
#else
ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
if (ret < 0) {
printf("VSC:0x%x could not read REV_ID from device.\n",
@ -258,7 +496,7 @@ int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
/* configure global core control register, Turn on Global core power */
i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
#endif
vsc_wp_config(vsc_addr);
return 0;
@ -270,6 +508,22 @@ void vsc_wp_config(unsigned int vsc_addr)
/* For new crosspoint configuration to occur, WP bit of
* CORE_CONFIG_REG should be set 1 and then reset to 0 */
#ifdef CONFIG_DM_I2C
int ret, bus_num = 0;
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, vsc_addr,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return;
}
dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x01);
dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x0);
#else
i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01);
i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0);
#endif
}

160
board/freescale/p1010rdb/p1010rdb.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#include <common.h>
@ -124,7 +125,7 @@ int board_early_init_r(void)
return 0;
}
#ifdef CONFIG_PCI
#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
void pci_init_board(void)
{
fsl_pcie_init_board(0);
@ -136,6 +137,125 @@ int config_board_mux(int ctrl_type)
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u8 tmp;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
int ret;
#if defined(CONFIG_TARGET_P1010RDB_PA)
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
I2C_PCA9557_ADDR1, 1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n",
__func__, I2C_PCA9557_BUS_NUM);
return ret;
}
switch (ctrl_type) {
case MUX_TYPE_IFC:
tmp = 0xf0;
dm_i2c_write(dev, 3, &tmp, 1);
tmp = 0x01;
dm_i2c_write(dev, 1, &tmp, 1);
sd_ifc_mux = MUX_TYPE_IFC;
clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
break;
case MUX_TYPE_SDHC:
tmp = 0xf0;
dm_i2c_write(dev, 3, &tmp, 1);
tmp = 0x05;
dm_i2c_write(dev, 1, &tmp, 1);
sd_ifc_mux = MUX_TYPE_SDHC;
clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
PMUXCR1_SDHC_ENABLE);
break;
case MUX_TYPE_SPIFLASH:
out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
break;
case MUX_TYPE_TDM:
out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
break;
case MUX_TYPE_CAN:
out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
break;
default:
break;
}
#elif defined(CONFIG_TARGET_P1010RDB_PB)
ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM,
I2C_PCA9557_ADDR2, 1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n",
__func__, I2C_PCA9557_BUS_NUM);
return ret;
}
switch (ctrl_type) {
case MUX_TYPE_IFC:
dm_i2c_read(dev, 0, &tmp, 1);
clrbits_8(&tmp, 0x04);
dm_i2c_write(dev, 1, &tmp, 1);
dm_i2c_read(dev, 3, &tmp, 1);
clrbits_8(&tmp, 0x04);
dm_i2c_write(dev, 3, &tmp, 1);
sd_ifc_mux = MUX_TYPE_IFC;
clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
break;
case MUX_TYPE_SDHC:
dm_i2c_read(dev, 0, &tmp, 1);
setbits_8(&tmp, 0x04);
dm_i2c_write(dev, 1, &tmp, 1);
dm_i2c_read(dev, 3, &tmp, 1);
clrbits_8(&tmp, 0x04);
dm_i2c_write(dev, 3, &tmp, 1);
sd_ifc_mux = MUX_TYPE_SDHC;
clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
PMUXCR1_SDHC_ENABLE);
break;
case MUX_TYPE_SPIFLASH:
dm_i2c_read(dev, 0, &tmp, 1);
clrbits_8(&tmp, 0x80);
dm_i2c_write(dev, 1, &tmp, 1);
dm_i2c_read(dev, 3, &tmp, 1);
clrbits_8(&tmp, 0x80);
dm_i2c_write(dev, 3, &tmp, 1);
break;
case MUX_TYPE_TDM:
dm_i2c_read(dev, 0, &tmp, 1);
setbits_8(&tmp, 0x82);
dm_i2c_write(dev, 1, &tmp, 1);
dm_i2c_read(dev, 3, &tmp, 1);
clrbits_8(&tmp, 0x82);
dm_i2c_write(dev, 3, &tmp, 1);
break;
case MUX_TYPE_CAN:
dm_i2c_read(dev, 0, &tmp, 1);
clrbits_8(&tmp, 0x02);
dm_i2c_write(dev, 1, &tmp, 1);
dm_i2c_read(dev, 3, &tmp, 1);
clrbits_8(&tmp, 0x02);
dm_i2c_write(dev, 3, &tmp, 1);
break;
case MUX_TYPE_CS0_NOR:
dm_i2c_read(dev, 0, &tmp, 1);
clrbits_8(&tmp, 0x08);
dm_i2c_write(dev, 1, &tmp, 1);
dm_i2c_read(dev, 3, &tmp, 1);
clrbits_8(&tmp, 0x08);
dm_i2c_write(dev, 3, &tmp, 1);
break;
case MUX_TYPE_CS0_NAND:
dm_i2c_read(dev, 0, &tmp, 1);
setbits_8(&tmp, 0x08);
dm_i2c_write(dev, 1, &tmp, 1);
dm_i2c_read(dev, 3, &tmp, 1);
clrbits_8(&tmp, 0x08);
dm_i2c_write(dev, 3, &tmp, 1);
break;
default:
break;
}
#endif
#else
#if defined(CONFIG_TARGET_P1010RDB_PA)
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
@ -242,6 +362,7 @@ int config_board_mux(int ctrl_type)
break;
}
i2c_set_bus_num(orig_bus);
#endif
#endif
return 0;
}
@ -250,9 +371,23 @@ int config_board_mux(int ctrl_type)
int i2c_pca9557_read(int type)
{
u8 val;
int bus_num = I2C_PCA9557_BUS_NUM;
i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
#ifdef CONFIG_DM_I2C
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA9557_ADDR2, 1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n",
__func__, bus_num);
return ret;
}
dm_i2c_read(dev, 0, &val, 1);
#else
i2c_set_bus_num(bus_num);
i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
#endif
switch (type) {
case I2C_READ_BANK:
@ -280,11 +415,26 @@ int checkboard(void)
printf("Board: %sRDB-PA, ", cpu->name);
#elif defined(CONFIG_TARGET_P1010RDB_PB)
printf("Board: %sRDB-PB, ", cpu->name);
#ifdef CONFIG_DM_I2C
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR2,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
I2C_PCA9557_BUS_NUM);
return ret;
}
val = 0x0; /* no polarity inversion */
dm_i2c_write(dev, 2, &val, 1);
#else
i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
val = 0x0; /* no polarity inversion */
i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
#endif
#endif
#ifdef CONFIG_SDCARD
/* switch to IFC to read info from CPLD */
@ -308,7 +458,11 @@ int checkboard(void)
case 0xe:
puts("SDHC\n");
val = 0x60; /* set pca9557 pin input/output */
#ifdef CONFIG_DM_I2C
dm_i2c_write(dev, 3, &val, 1);
#else
i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
#endif
break;
case 0x5:
config_board_mux(MUX_TYPE_IFC);
@ -457,7 +611,7 @@ int ft_board_setup(void *blob, bd_t *bd)
base = env_get_bootm_low();
size = env_get_bootm_size();
#if defined(CONFIG_PCI)
#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
FT_FSL_PCI_SETUP;
#endif

24
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#include <common.h>
@ -227,6 +228,7 @@ int checkboard(void)
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u8 in, out, io_config, val;
int bus_num = CONFIG_SYS_SPD_BUS_NUM;
printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
in_8(&cpld_data->cpld_rev_major) & 0x0F,
@ -234,7 +236,26 @@ int checkboard(void)
in_8(&cpld_data->pcba_rev) & 0x0F);
/* Initialize i2c early for rom_loc and flash bank information */
i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
#if defined(CONFIG_DM_I2C)
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return -ENXIO;
}
if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
dm_i2c_read(dev, 1, &out, 1) < 0 ||
dm_i2c_read(dev, 3, &io_config, 1) < 0) {
printf("Error reading i2c boot information!\n");
return 0; /* Don't want to hang() on this error */
}
#else /* Non DM I2C support - will be removed */
i2c_set_bus_num(bus_num);
if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
@ -242,6 +263,7 @@ int checkboard(void)
printf("Error reading i2c boot information!\n");
return 0; /* Don't want to hang() on this error */
}
#endif
val = (in & io_config) | (out & (~io_config));

95
board/freescale/t102xqds/t102xqds.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#include <common.h>
@ -75,11 +76,24 @@ int checkboard(void)
return 0;
}
int select_i2c_ch_pca9547(u8 ch)
int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_write(dev, 0, &ch, 1);
#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@ -191,6 +205,82 @@ void board_retimer_ds125df111_init(void)
{
u8 reg;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
int ret, bus_num = 0;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
1, &dev);
if (ret)
goto failed;
/* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
reg = I2C_MUX_CH7;
dm_i2c_write(dev, 0, &reg, 1);
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
1, &dev);
if (ret)
goto failed;
reg = I2C_MUX_CH5;
dm_i2c_write(dev, 0, &reg, 1);
/* Access to Control/Shared register */
ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
1, &dev);
if (ret)
goto failed;
reg = 0x0;
dm_i2c_write(dev, 0xff, &reg, 1);
/* Read device revision and ID */
dm_i2c_read(dev, 1, &reg, 1);
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast */
reg = 0x0c;
dm_i2c_write(dev, 0xff, &reg, 1);
/* Reset Channel Registers */
dm_i2c_read(dev, 0, &reg, 1);
reg |= 0x4;
dm_i2c_write(dev, 0, &reg, 1);
/* Enable override divider select and Enable Override Output Mux */
dm_i2c_read(dev, 9, &reg, 1);
reg |= 0x24;
dm_i2c_write(dev, 9, &reg, 1);
/* Select VCO Divider to full rate (000) */
dm_i2c_read(dev, 0x18, &reg, 1);
reg &= 0x8f;
dm_i2c_write(dev, 0x18, &reg, 1);
/* Select active PFD MUX input as re-timed data (001) */
dm_i2c_read(dev, 0x1e, &reg, 1);
reg &= 0x3f;
reg |= 0x20;
dm_i2c_write(dev, 0x1e, &reg, 1);
/* Set data rate as 10.3125 Gbps */
reg = 0x0;
dm_i2c_write(dev, 0x60, &reg, 1);
reg = 0xb2;
dm_i2c_write(dev, 0x61, &reg, 1);
reg = 0x90;
dm_i2c_write(dev, 0x62, &reg, 1);
reg = 0xb3;
dm_i2c_write(dev, 0x63, &reg, 1);
reg = 0xcd;
dm_i2c_write(dev, 0x64, &reg, 1);
return;
failed:
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return;
#else
/* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
reg = I2C_MUX_CH7;
i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
@ -241,6 +331,7 @@ void board_retimer_ds125df111_init(void)
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
#endif
}
int board_early_init_f(void)
@ -281,7 +372,7 @@ int board_early_init_r(void)
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
board_mux_lane_to_slot();
board_retimer_ds125df111_init();

3
board/freescale/t102xqds/t102xqds.h
View file

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#ifndef __T102x_QDS_H__
@ -8,6 +9,6 @@
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
int select_i2c_ch_pca9547(u8 ch);
int select_i2c_ch_pca9547(u8 ch, int bus_num);
#endif

71
board/freescale/t102xrdb/t102xrdb.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#include <common.h>
@ -250,8 +251,69 @@ static u32 t1023rdb_ctrl(u32 ctrl_type)
{
ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 val, orig_bus = i2c_get_bus_num();
u32 val;
u8 tmp;
int bus_num = I2C_PCA6408_BUS_NUM;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(bus_num, I2C_PCA6408_ADDR,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
switch (ctrl_type) {
case GPIO1_SD_SEL:
val = in_be32(&pgpio->gpdat);
val |= GPIO1_SD_SEL;
out_be32(&pgpio->gpdat, val);
setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
break;
case GPIO1_EMMC_SEL:
val = in_be32(&pgpio->gpdat);
val &= ~GPIO1_SD_SEL;
out_be32(&pgpio->gpdat, val);
setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
break;
case GPIO3_GET_VERSION:
pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
+ GPIO3_OFFSET);
val = in_be32(&pgpio->gpdat);
val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
if (val == 0x3) /* GPIO3_4/5 not used on RevB */
val = 0;
return val;
case I2C_GET_BANK:
dm_i2c_read(dev, 0, &tmp, 1);
tmp &= 0x7;
tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
return tmp;
case I2C_SET_BANK0:
tmp = 0x0;
dm_i2c_write(dev, 1, &tmp, 1);
tmp = 0xf8;
dm_i2c_write(dev, 3, &tmp, 1);
/* asserting HRESET_REQ */
out_be32(&gur->rstcr, 0x2);
break;
case I2C_SET_BANK4:
tmp = 0x1;
dm_i2c_write(dev, 1, &tmp, 1);
tmp = 0xf8;
dm_i2c_write(dev, 3, &tmp, 1);
out_be32(&gur->rstcr, 0x2);
break;
default:
break;
}
#else
u32 orig_bus;
orig_bus = i2c_get_bus_num();
switch (ctrl_type) {
case GPIO1_SD_SEL:
@ -275,14 +337,14 @@ static u32 t1023rdb_ctrl(u32 ctrl_type)
val = 0;
return val;
case I2C_GET_BANK:
i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
i2c_set_bus_num(bus_num);
i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
tmp &= 0x7;
tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
i2c_set_bus_num(orig_bus);
return tmp;
case I2C_SET_BANK0:
i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
i2c_set_bus_num(bus_num);
tmp = 0x0;
i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
tmp = 0xf8;
@ -291,7 +353,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type)
out_be32(&gur->rstcr, 0x2);
break;
case I2C_SET_BANK4:
i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
i2c_set_bus_num(bus_num);
tmp = 0x1;
i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
tmp = 0xf8;
@ -301,6 +363,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type)
default:
break;
}
#endif
return 0;
}

5
board/freescale/t1040qds/diu.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
* Author: Priyanka Jain <Priyanka.Jain@freescale.com>
*/
@ -48,7 +49,7 @@ void diu_set_pixel_clock(unsigned int pixclock)
/* Program HDMI encoder */
/* Switch channel to DIU */
select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
select_i2c_ch_pca9547(I2C_MUX_CH_DIU, 0);
/* Set dispaly encoder */
ret = diu_set_dvi_encoder(temp);
@ -58,7 +59,7 @@ void diu_set_pixel_clock(unsigned int pixclock)
}
/* Switch channel to default */
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
/* Program pixel clock */
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,

18
board/freescale/t1040qds/t1040qds.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#include <common.h>
@ -79,11 +80,24 @@ int checkboard(void)
return 0;
}
int select_i2c_ch_pca9547(u8 ch)
int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_write(dev, 0, &ch, 1);
#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@ -154,7 +168,7 @@ int board_early_init_r(void)
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
return 0;
}

3
board/freescale/t1040qds/t1040qds.h
View file

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#ifndef __T1040_QDS_H__
@ -8,6 +9,6 @@
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
int select_i2c_ch_pca9547(u8 ch);
int select_i2c_ch_pca9547(u8 ch, int bus_bum);
#endif

19
board/freescale/t208xqds/t208xqds.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2013 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#include <common.h>
@ -75,11 +76,23 @@ int checkboard(void)
return 0;
}
int select_i2c_ch_pca9547(u8 ch)
int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_write(dev, 0, &ch, 1);
#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@ -90,7 +103,7 @@ int select_i2c_ch_pca9547(u8 ch)
int i2c_multiplexer_select_vid_channel(u8 channel)
{
return select_i2c_ch_pca9547(channel);
return select_i2c_ch_pca9547(channel, 0);
}
int brd_mux_lane_to_slot(void)
@ -368,7 +381,7 @@ int board_early_init_r(void)
printf("Warning: Adjusting core voltage failed.\n");
brd_mux_lane_to_slot();
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
return 0;
}

45
board/freescale/t4qds/t4240qds.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2012 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#include <common.h>
@ -91,11 +92,25 @@ int checkboard(void)
return 0;
}
int select_i2c_ch_pca9547(u8 ch)
int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_write(dev, 0, &ch, 1);
#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@ -115,10 +130,28 @@ static inline int read_voltage(void)
{
int i, ret, voltage_read = 0;
u16 vol_mon;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
int bus_num = 0;
#endif
for (i = 0; i < NUM_READINGS; i++) {
#ifdef CONFIG_DM_I2C
ret = i2c_get_chip_for_busnum(bus_num, I2C_VOL_MONITOR_ADDR,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_read(dev,
I2C_VOL_MONITOR_BUS_V_OFFSET,
(void *)&vol_mon, 2);
#else
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
#endif
if (ret) {
printf("VID: failed to read core voltage\n");
return ret;
@ -250,7 +283,7 @@ static int adjust_vdd(ulong vdd_override)
unsigned voltage;
};
ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0);
if (ret) {
debug("VID: I2c failed to switch channel\n");
ret = -1;
@ -348,7 +381,7 @@ int config_frontside_crossbar_vsc3316(void)
u32 srds_prtcl_s1, srds_prtcl_s2;
int ret;
ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS, 0);
if (ret)
return ret;
@ -567,7 +600,7 @@ int board_early_init_r(void)
/* Configure board SERDES ports crossbar */
config_frontside_crossbar_vsc3316();
config_backside_crossbar_mux();
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
return 0;
}
@ -732,11 +765,11 @@ void board_detail(void)
}
/* Voltage secion */
if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0)) {
vdd = read_voltage();
if (vdd > 0)
printf("Core voltage= %d mV\n", vdd);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
}
printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);

1
configs/MPC8548CDS_36BIT_defconfig
View file

@ -45,3 +45,4 @@ CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_DM_I2C=y

1
configs/MPC8548CDS_defconfig
View file

@ -44,3 +44,4 @@ CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_DM_I2C=y

1
configs/MPC8548CDS_legacy_defconfig
View file

@ -44,3 +44,4 @@ CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_DM_I2C=y

9
configs/P1010RDB-PA_36BIT_NAND_defconfig
View file

@ -10,6 +10,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@ -69,6 +71,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -76,4 +82,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

10
configs/P1010RDB-PA_36BIT_NOR_defconfig
View file

@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -50,6 +53,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -57,4 +64,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

9
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
View file

@ -11,6 +11,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -63,6 +65,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -70,4 +76,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

9
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
View file

@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -65,6 +67,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -72,4 +78,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

9
configs/P1010RDB-PA_NAND_defconfig
View file

@ -10,6 +10,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_OF_CONTROL=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@ -68,6 +70,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -75,4 +81,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

10
configs/P1010RDB-PA_NOR_defconfig
View file

@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -49,6 +52,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -56,4 +63,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

9
configs/P1010RDB-PA_SDCARD_defconfig
View file

@ -11,6 +11,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -62,6 +64,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -69,4 +75,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

9
configs/P1010RDB-PA_SPIFLASH_defconfig
View file

@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -64,6 +66,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -71,4 +77,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

9
configs/P1010RDB-PB_36BIT_NAND_defconfig
View file

@ -10,6 +10,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
@ -69,6 +71,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -76,4 +82,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

10
configs/P1010RDB-PB_36BIT_NOR_defconfig
View file

@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -50,6 +53,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -57,4 +64,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

9
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
View file

@ -11,6 +11,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -63,6 +65,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -70,4 +76,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

9
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
View file

@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_OF_CONTROL=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@ -65,6 +67,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -72,4 +78,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

9
configs/P1010RDB-PB_NAND_defconfig
View file

@ -10,6 +10,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xFF800000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_OF_CONTROL=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
CONFIG_FIT=y
@ -67,6 +69,10 @@ CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
@ -75,4 +81,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

10
configs/P1010RDB-PB_NOR_defconfig
View file

@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -48,6 +51,10 @@ CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
@ -56,4 +63,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

9
configs/P1010RDB-PB_SDCARD_defconfig
View file

@ -11,6 +11,8 @@ CONFIG_SPL=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -62,6 +64,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -69,4 +75,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

9
configs/P1010RDB-PB_SPIFLASH_defconfig
View file

@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_TEXT_BASE=0xD0001000
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -64,6 +66,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
@ -71,4 +77,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P1020RDB-PC_36BIT_NAND_defconfig
View file

@ -82,3 +82,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
View file

@ -77,3 +77,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
View file

@ -79,3 +79,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P1020RDB-PC_36BIT_defconfig
View file

@ -66,3 +66,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P1020RDB-PC_NAND_defconfig
View file

@ -81,3 +81,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P1020RDB-PC_SDCARD_defconfig
View file

@ -76,3 +76,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P1020RDB-PC_SPIFLASH_defconfig
View file

@ -78,3 +78,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P1020RDB-PC_defconfig
View file

@ -65,3 +65,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P1020RDB-PD_NAND_defconfig
View file

@ -85,3 +85,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P1020RDB-PD_SDCARD_defconfig
View file

@ -80,3 +80,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P1020RDB-PD_SPIFLASH_defconfig
View file

@ -82,3 +82,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P1020RDB-PD_defconfig
View file

@ -69,3 +69,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P2020RDB-PC_36BIT_NAND_defconfig
View file

@ -87,3 +87,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P2020RDB-PC_36BIT_SDCARD_defconfig
View file

@ -82,3 +82,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
View file

@ -84,3 +84,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P2020RDB-PC_36BIT_defconfig
View file

@ -71,3 +71,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P2020RDB-PC_NAND_defconfig
View file

@ -86,3 +86,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P2020RDB-PC_SDCARD_defconfig
View file

@ -81,3 +81,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P2020RDB-PC_SPIFLASH_defconfig
View file

@ -83,3 +83,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/P2020RDB-PC_defconfig
View file

@ -70,3 +70,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

1
configs/P2041RDB_NAND_defconfig
View file

@ -61,3 +61,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P2041RDB_SDCARD_defconfig
View file

@ -60,3 +60,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P2041RDB_SPIFLASH_defconfig
View file

@ -61,3 +61,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P2041RDB_defconfig
View file

@ -59,3 +59,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P3041DS_NAND_defconfig
View file

@ -61,3 +61,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P3041DS_SDCARD_defconfig
View file

@ -60,3 +60,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P3041DS_SPIFLASH_defconfig
View file

@ -61,3 +61,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P3041DS_defconfig
View file

@ -59,3 +59,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P4080DS_SDCARD_defconfig
View file

@ -59,3 +59,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P4080DS_SPIFLASH_defconfig
View file

@ -60,3 +60,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P4080DS_defconfig
View file

@ -58,3 +58,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P5040DS_NAND_defconfig
View file

@ -62,3 +62,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P5040DS_SDCARD_defconfig
View file

@ -60,3 +60,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P5040DS_SPIFLASH_defconfig
View file

@ -61,3 +61,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

1
configs/P5040DS_defconfig
View file

@ -59,3 +59,4 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y

2
configs/T1024RDB_NAND_defconfig
View file

@ -81,3 +81,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/T1024RDB_SDCARD_defconfig
View file

@ -78,3 +78,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/T1024RDB_SPIFLASH_defconfig
View file

@ -81,3 +81,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/T1024RDB_defconfig
View file

@ -66,3 +66,5 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/T1042D4RDB_NAND_defconfig
View file

@ -82,3 +82,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/T1042D4RDB_SDCARD_defconfig
View file

@ -79,3 +79,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/T1042D4RDB_SPIFLASH_defconfig
View file

@ -82,3 +82,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

2
configs/T1042D4RDB_defconfig
View file

@ -67,3 +67,5 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO=y
CONFIG_CFB_CONSOLE_ANSI=y
CONFIG_DM_I2C=y
CONFIG_DM_RTC=y

1
configs/T2080QDS_NAND_defconfig
View file

@ -80,3 +80,4 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_I2C=y

1
configs/T2080QDS_SDCARD_defconfig
View file

@ -77,3 +77,4 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_I2C=y

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