GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-21 14:41:31 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

DRA7: add ABB setup for MPU voltage domain

Browse source 
Patch adds modification to shared omap5 abb_setup() function, and
proper registers definitions needed for ABB setup sequence. ABB is
initialized for MPU voltage domain at OPP_NOM.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
This commit is contained in:
Nishanth Menon 2014-01-14 12:27:29 -06:00 • committed by Tom Rini
parent 3ac8c0bf65
commit 194dd74ad9
3 changed files with 20 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
arch/arm/cpu/armv7/omap5/abb.c
View file

@ -28,18 +28,25 @@
s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb)
{ {
u32 vset; u32 vset;
u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK;
u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK;
if (!is_omap54xx()) {
/* DRA7 */
fuse_enable_mask = DRA7_ABB_FUSE_ENABLE_MASK;
fuse_vset_mask = DRA7_ABB_FUSE_VSET_MASK;
}
/* /*
* ABB parameters must be properly fused * ABB parameters must be properly fused
* otherwise ABB should be disabled * otherwise ABB should be disabled
*/ */
vset = readl(fuse); vset = readl(fuse);
if (!(vset & OMAP5_ABB_FUSE_ENABLE_MASK)) if (!(vset & fuse_enable_mask))
return -1; return -1;
/* prepare VSET value for LDOVBB mux register */ /* prepare VSET value for LDOVBB mux register */
vset &= OMAP5_ABB_FUSE_VSET_MASK; vset &= fuse_vset_mask;
vset >>= ffs(OMAP5_ABB_FUSE_VSET_MASK) - 1; vset >>= ffs(fuse_vset_mask) - 1;
vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1; vset <<= ffs(OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK) - 1;
vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK; vset |= OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK;

8
arch/arm/cpu/armv7/omap5/prcm-regs.c
View file

@ -432,11 +432,13 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_srcomp_code_latch = 0x4A002E84, .control_srcomp_code_latch = 0x4A002E84,
.control_ddr_control_ext_0 = 0x4A002E88, .control_ddr_control_ext_0 = 0x4A002E88,
.control_padconf_core_base = 0x4A003400, .control_padconf_core_base = 0x4A003400,
.control_std_fuse_opp_vdd_mpu_2 = 0x4A003B24,
.control_port_emif1_sdram_config = 0x4AE0C110, .control_port_emif1_sdram_config = 0x4AE0C110,
.control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
.control_port_emif2_sdram_config = 0x4AE0C118, .control_port_emif2_sdram_config = 0x4AE0C118,
.control_emif1_sdram_config_ext = 0x4AE0C144, .control_emif1_sdram_config_ext = 0x4AE0C144,
.control_emif2_sdram_config_ext = 0x4AE0C148, .control_emif2_sdram_config_ext = 0x4AE0C148,
.control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C158,
.control_padconf_mode = 0x4AE0C5A0, .control_padconf_mode = 0x4AE0C5A0,
.control_xtal_oscillator = 0x4AE0C5A4, .control_xtal_oscillator = 0x4AE0C5A4,
.control_i2c_2 = 0x4AE0C5A8, .control_i2c_2 = 0x4AE0C5A8,
@ -807,6 +809,9 @@ struct prcm_regs const dra7xx_prcm = {
.cm_dsp_clkstctrl = 0x4a005400, .cm_dsp_clkstctrl = 0x4a005400,
.cm_dsp_dsp_clkctrl = 0x4a005420, .cm_dsp_dsp_clkctrl = 0x4a005420,
/* prm irqstatus regs */
.prm_irqstatus_mpu_2 = 0x4ae06014,
/* cm2.ckgen */ /* cm2.ckgen */
.cm_clksel_usb_60mhz = 0x4a008104, .cm_clksel_usb_60mhz = 0x4a008104,
.cm_clkmode_dpll_per = 0x4a008140, .cm_clkmode_dpll_per = 0x4a008140,
@ -967,4 +972,7 @@ struct prcm_regs const dra7xx_prcm = {
.prm_vc_val_bypass = 0x4ae07da0, .prm_vc_val_bypass = 0x4ae07da0,
.prm_vc_cfg_i2c_mode = 0x4ae07db4, .prm_vc_cfg_i2c_mode = 0x4ae07db4,
.prm_vc_cfg_i2c_clk = 0x4ae07db8, .prm_vc_cfg_i2c_clk = 0x4ae07db8,
.prm_abbldo_mpu_setup = 0x4AE07DDC,
.prm_abbldo_mpu_ctrl = 0x4AE07DE0,
}; };

2
arch/arm/include/asm/arch-omap5/omap.h
View file

@ -205,6 +205,8 @@ struct s32ktimer {
/* ABB efuse masks */ /* ABB efuse masks */
#define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24)
#define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) #define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29)
#define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20)
#define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25)
#define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10)
#define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0) #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0)