GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-03-27 17:41:34 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

ARC: Cache: Fix style violations reported by checkpatch

Browse source 
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Eugeniy Paltsev 2018-01-16 19:20:29 +03:00 • committed by Alexey Brodkin
parent b0146f9e29
commit 19b10a42f6
1 changed files with 8 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
arch/arc/lib/cache.c
View file

@ -13,12 +13,12 @@
#include <asm/cache.h> #include <asm/cache.h>
/* Bit values in IC_CTRL */ /* Bit values in IC_CTRL */
#define IC_CTRL_CACHE_DISABLE (1 << 0) #define IC_CTRL_CACHE_DISABLE BIT(0)
/* Bit values in DC_CTRL */ /* Bit values in DC_CTRL */
#define DC_CTRL_CACHE_DISABLE (1 << 0) #define DC_CTRL_CACHE_DISABLE BIT(0)
#define DC_CTRL_INV_MODE_FLUSH (1 << 6) #define DC_CTRL_INV_MODE_FLUSH BIT(6)
#define DC_CTRL_FLUSH_STATUS (1 << 8) #define DC_CTRL_FLUSH_STATUS BIT(8)
#define CACHE_VER_NUM_MASK 0xF #define CACHE_VER_NUM_MASK 0xF
#define OP_INV 0x1 #define OP_INV 0x1
@ -269,7 +269,6 @@ void cache_init(void)
write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
order_base_2(ap_size / 1024) - 2); order_base_2(ap_size / 1024) - 2);
/* IOC Aperture start must be aligned to the size of the aperture */ /* IOC Aperture start must be aligned to the size of the aperture */
if (ap_base % ap_size != 0) if (ap_base % ap_size != 0)
panic("IOC Aperture start must be aligned to the size of the aperture"); panic("IOC Aperture start must be aligned to the size of the aperture");
@ -277,7 +276,6 @@ void cache_init(void)
write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12); write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1); write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1); write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
} }
read_decode_mmu_bcr(); read_decode_mmu_bcr();
@ -426,8 +424,7 @@ static unsigned int __before_dc_op(const int op)
static void __after_dc_op(const int op, unsigned int reg) static void __after_dc_op(const int op, unsigned int reg)
{ {
if (op & OP_FLUSH) /* flush / flush-n-inv both wait */ if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS) while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
;
/* Switch back to default Invalidate mode */ /* Switch back to default Invalidate mode */
if (op == OP_INV) if (op == OP_INV)
@ -453,6 +450,7 @@ static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
const int cacheop) const int cacheop)
{ {
unsigned int ctrl_reg = __before_dc_op(cacheop); unsigned int ctrl_reg = __before_dc_op(cacheop);
__cache_line_loop(paddr, sz, cacheop); __cache_line_loop(paddr, sz, cacheop);
__after_dc_op(cacheop, ctrl_reg); __after_dc_op(cacheop, ctrl_reg);
} }