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Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Arria10 DRAM fixes and Gen5 cache fixes
This commit is contained in:
Tom Rini
commit
19c8c9c103
6 changed files with 48 additions and 76 deletions
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@ -62,8 +62,8 @@ void v7_outer_cache_enable(void)
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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writel(0x111, &pl310->pl310_tag_latency_ctrl);
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writel(0x121, &pl310->pl310_data_latency_ctrl);
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writel(0x0, &pl310->pl310_tag_latency_ctrl);
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writel(0x10, &pl310->pl310_data_latency_ctrl);
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/* enable BRESP, instruction and data prefetch, full line of zeroes */
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setbits_le32(&pl310->pl310_aux_ctrl,
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@ -77,6 +77,8 @@ void spl_board_init(void)
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void board_init_f(ulong dummy)
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{
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dcache_disable();
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socfpga_init_security_policies();
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socfpga_sdram_remap_zero();
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@ -1,4 +1,4 @@
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if TARGET_SOCFPGA_ARRIA10
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if TARGET_SOCFPGA_ARRIA10_SOCDK
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config SYS_CPU
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default "armv7"
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@ -31,7 +31,6 @@ static u64 sdram_size_calc(void);
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#define DDR_REG_CORE2SEQ 0xFFD05078
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#define DDR_READ_LATENCY_DELAY 40
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#define DDR_SIZE_2GB_HEX 0x80000000
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#define DDR_MAX_TRIES 0x00100000
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#define IO48_MMR_DRAMSTS 0xFFCFA0EC
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#define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
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@ -103,52 +102,18 @@ static int match_ddr_conf(u32 ddr_conf)
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return 0;
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}
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/* Check whether SDRAM is successfully Calibrated */
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static int is_sdram_cal_success(void)
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{
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return readl(&socfpga_ecc_hmc_base->ddrcalstat);
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}
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static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
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{
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u32 reg = readl(ereg);
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return (reg & BIT(bit)) ? 1 : 0;
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}
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static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
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u32 expected, u32 timeout_usec)
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{
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u32 tmr;
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for (tmr = 0; tmr < timeout_usec; tmr += 100) {
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udelay(100);
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WATCHDOG_RESET();
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if (ddr_get_bit(ereg, bit) == expected)
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return 0;
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}
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return 1;
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}
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static int emif_clear(void)
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{
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u32 i = DDR_MAX_TRIES;
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u8 ret = 0;
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writel(0, DDR_REG_CORE2SEQ);
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do {
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ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
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SEQ2CORE_MASK, 1, 50, 0);
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} while (ret && (--i > 0));
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return !i;
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return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
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SEQ2CORE_MASK, 0, 1000, 0);
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}
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static int emif_reset(void)
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{
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u32 c2s, s2c;
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int ret;
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c2s = readl(DDR_REG_CORE2SEQ);
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s2c = readl(DDR_REG_SEQ2CORE);
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@ -159,21 +124,28 @@ static int emif_reset(void)
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readl(IO48_MMR_NIOS2_RESERVE2),
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readl(IO48_MMR_DRAMSTS));
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if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
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debug("failed emif_clear()\n");
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return -EPERM;
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if (s2c & SEQ2CORE_MASK) {
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ret = emif_clear();
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if (ret) {
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debug("failed emif_clear()\n");
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return -EPERM;
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}
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}
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writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
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if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
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ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
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SEQ2CORE_INT_RESP_BIT, false, 1000, false);
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if (ret) {
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debug("emif_reset failed to see interrupt acknowledge\n");
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return -EPERM;
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} else {
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debug("emif_reset interrupt acknowledged\n");
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emif_clear();
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return ret;
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}
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if (emif_clear()) {
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mdelay(1);
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ret = emif_clear();
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if (ret) {
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debug("emif_clear() failed\n");
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return -EPERM;
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}
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@ -189,30 +161,23 @@ static int emif_reset(void)
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static int ddr_setup(void)
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{
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int i, j, ddr_setup_complete = 0;
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int i, ret;
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/* Try 3 times to do a calibration */
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for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
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WATCHDOG_RESET();
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/* Try 32 times to do a calibration */
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for (i = 0; i < 32; i++) {
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mdelay(500);
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ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat,
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BIT(0), true, 500, false);
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if (!ret)
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return 0;
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/* A delay to wait for calibration bit to set */
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for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
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mdelay(500);
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ddr_setup_complete = is_sdram_cal_success();
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}
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if (!ddr_setup_complete)
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if (emif_reset())
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puts("Error: Failed to reset EMIF\n");
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ret = emif_reset();
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if (ret)
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puts("Error: Failed to reset EMIF\n");
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}
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/* After 3 times trying calibration */
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if (!ddr_setup_complete) {
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puts("Error: Could Not Calibrate SDRAM\n");
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return -EPERM;
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}
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return 0;
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puts("Error: Could Not Calibrate SDRAM\n");
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return -EPERM;
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}
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static int sdram_is_ecc_enabled(void)
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@ -270,7 +235,7 @@ static u64 sdram_size_calc(void)
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size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
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ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
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debug("SDRAM size=%llu", size);
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debug("SDRAM size=%llu\n", size);
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return size;
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}
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@ -304,7 +269,7 @@ static void sdram_mmr_init(void)
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* bit[9:6] = Minor Release #
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* bit[14:10] = Major Release #
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*/
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if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
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if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
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update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
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writel(((update_value & 0xFF) >> 5),
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&socfpga_ecc_hmc_base->ddrioctrl);
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@ -394,7 +359,7 @@ static void sdram_mmr_init(void)
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caltim0_cfg_act_to_rdwr -
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(ctrlcfg0_cfg_ctrl_burst_len >> 2));
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io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
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io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
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ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
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(ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
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/* Up to here was in memory cycles so divide by 2 */
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@ -424,7 +389,7 @@ static void sdram_mmr_init(void)
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&socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
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/* Configure the read latency [0xFFD12414] */
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writel(((socfpga_io48_mmr_base->dramtiming0 &
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writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
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ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
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DDR_READ_LATENCY_DELAY,
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&socfpga_noc_ddr_scheduler_base->
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@ -15,8 +15,6 @@
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/*
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* U-Boot general configurations
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*/
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/* Cache options */
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#define CONFIG_SYS_DCACHE_OFF
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/* Memory configurations */
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#define PHYS_SDRAM_1_SIZE 0x40000000
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@ -275,13 +275,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
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/* SPL QSPI boot support */
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#ifdef CONFIG_SPL_SPI_SUPPORT
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000
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#endif
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#endif
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/* SPL NAND boot support */
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#ifdef CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
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#endif
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#endif
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/*
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