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pcm051: Add support for Phytec phyCORE-AM335x
The board is named pcm051 and has this hardware: SOC: TI AM3359 DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB ETH 1: LAN8710AI SPI-Flash: W25Q64BVSSIG RTC: RV-4162-C7 I2C-EEPROM: CAT32WC32 NAND: MT29F4G08_VFPGA63 PMIC: TPS65910A3 LCD Supported: UART 1 MMC/SD ETH 1 USB I2C SPI Not yet supported: NAND RTC LCD Signed-off-by: Lars Poeschel <poeschel@lemonage.de> [trini: Add #define CONFIG_PHY_ADDR 0 to config] Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Lars Poeschel
Tom Rini
parent
aca0b8b4f7
commit
1c1b7c3739
8 changed files with 801 additions and 0 deletions
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@ -815,6 +815,9 @@ Dave Peverley <dpeverley@mpc-data.co.uk>
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omap730p2 ARM926EJS
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Lars Poeschel <poeschel@lemonage.de>
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pcm051 ARM ARMV7 (AM33xx Soc)
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Mathieu Poirier <mathieu.poirier@linaro.org>
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snowball ARM ARMV7 (u8500 SoC)
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@ -65,6 +65,24 @@
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#define MT41J128MJT125_PHY_FIFO_WE 0x100
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#define MT41J128MJT125_IOCTRL_VALUE 0x18B
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/* Micron MT41J256M8HX-15E */
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#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
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#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
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#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
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#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
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#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
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#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
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#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
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#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1
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#define MT41J256M8HX15E_RATIO 0x40
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#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
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#define MT41J256M8HX15E_RD_DQS 0x3B
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#define MT41J256M8HX15E_WR_DQS 0x85
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#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
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#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
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#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
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/**
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* Configure SDRAM
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*/
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46
board/phytec/pcm051/Makefile
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46
board/phytec/pcm051/Makefile
Normal file
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@ -0,0 +1,46 @@
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#
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# Makefile
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#
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# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed "as is" WITHOUT ANY WARRANTY of any
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# kind, whether express or implied; without even the implied warranty
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# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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ifdef CONFIG_SPL_BUILD
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COBJS := mux.o
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endif
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COBJS += board.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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266
board/phytec/pcm051/board.c
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266
board/phytec/pcm051/board.c
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@ -0,0 +1,266 @@
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/*
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* board.c
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*
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* Board functions for Phytec phyCORE-AM335x (pcm051) based boards
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*
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* Copyright (C) 2013 Lemonage Software GmbH
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* Author Lars Poeschel <poeschel@lemonage.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
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#ifdef CONFIG_SPL_BUILD
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static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
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#endif
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/* MII mode defines */
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#define MII_MODE_ENABLE 0x0
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#define RGMII_MODE_ENABLE 0xA
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#define RMII_RGMII2_MODE_ENABLE 0x49
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/* UART defines */
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#ifdef CONFIG_SPL_BUILD
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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/* DDR RAM defines */
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#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
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static void rtc32k_enable(void)
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{
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struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
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/*
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* Unlock the RTC's registers. For more details please see the
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* RTC_SS section of the TRM. In order to unlock we need to
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* write these specific values (keys) in this order.
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*/
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writel(0x83e70b13, &rtc->kick0r);
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writel(0x95a4f1e0, &rtc->kick1r);
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/* Enable the RTC 32K OSC by setting bits 3 and 6. */
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writel((1 << 3) | (1 << 6), &rtc->osc);
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}
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41J256M8HX15E_RD_DQS,
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.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
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.datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
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.datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
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.datadldiff0 = PHY_DLL_LOCK_DIFF,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41J256M8HX15E_RATIO,
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.cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
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.cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
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.cmd1csratio = MT41J256M8HX15E_RATIO,
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.cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
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.cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
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.cmd2csratio = MT41J256M8HX15E_RATIO,
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.cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
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.cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
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.ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
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.sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
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.sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
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.sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
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.zq_config = MT41J256M8HX15E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY,
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};
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#endif
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/*
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* early system init of muxing and clocks.
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*/
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void s_init(void)
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{
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/*
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* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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writel(0xAAAA, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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writel(0x5555, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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#ifdef CONFIG_SPL_BUILD
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/* Setup the PLLs and the clocks for the peripherals */
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pll_init();
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/* Enable RTC32K clock */
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rtc32k_enable();
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/* UART softreset */
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u32 regval;
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enable_uart0_pin_mux();
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regval = readl(&uart_base->uartsyscfg);
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regval |= UART_RESET;
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writel(regval, &uart_base->uartsyscfg);
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while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
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!= UART_CLK_RUNNING_MASK)
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;
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/* Disable smart idle */
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regval = readl(&uart_base->uartsyscfg);
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regval |= UART_SMART_IDLE_EN;
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writel(regval, &uart_base->uartsyscfg);
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gd = &gdata;
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preloader_console_init();
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/* Initalize the board header */
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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enable_board_pin_mux();
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config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
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#endif
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}
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
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return 0;
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}
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#ifdef CONFIG_DRIVER_TI_CPSW
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_id = 0,
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.phy_if = PHY_INTERFACE_MODE_RGMII,
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},
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{
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.slave_reg_ofs = 0x308,
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.sliver_reg_ofs = 0xdc0,
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.phy_id = 1,
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.phy_if = PHY_INTERFACE_MODE_RGMII,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = AM335X_CPSW_MDIO_BASE,
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.cpsw_base = AM335X_CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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#endif
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#if defined(CONFIG_DRIVER_TI_CPSW) || \
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(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
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int board_eth_init(bd_t *bis)
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{
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int rv, n = 0;
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#ifdef CONFIG_DRIVER_TI_CPSW
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
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printf("<ethaddr> not set. Reading from E-fuse\n");
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (is_valid_ether_addr(mac_addr))
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eth_setenv_enetaddr("ethaddr", mac_addr);
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else
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goto try_usbether;
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}
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writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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n += rv;
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try_usbether:
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#endif
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#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
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rv = usb_eth_initialize(bis);
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if (rv < 0)
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printf("Error %d registering USB_ETHER\n", rv);
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else
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n += rv;
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#endif
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return n;
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}
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#endif
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33
board/phytec/pcm051/board.h
Normal file
33
board/phytec/pcm051/board.h
Normal file
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@ -0,0 +1,33 @@
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/*
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* board.h
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*
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* Phytec phyCORE-AM335x (pcm051) boards information header
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*
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* Copyright (C) 2013, Lemonage Software GmbH
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* Author Lars Poeschel <poeschel@lemonage.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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/*
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* We have three pin mux functions that must exist. We must be able to enable
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* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
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* main pinmux function that can be overridden to enable all other pinmux that
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* is required on the board.
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*/
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void enable_uart0_pin_mux(void);
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void enable_i2c0_pin_mux(void);
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void enable_board_pin_mux(void);
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void enable_cbmux_pin_mux(void);
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#endif
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133
board/phytec/pcm051/mux.c
Normal file
133
board/phytec/pcm051/mux.c
Normal file
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@ -0,0 +1,133 @@
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/*
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* mux.c
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*
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* Copyright (C) 2013 Lemonage Software GmbH
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* Author Lars Poeschel <poeschel@lemonage.de>
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include "board.h"
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
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{-1},
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};
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#ifdef CONFIG_MMC
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static struct module_pin_mux mmc0_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
||||
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
||||
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
||||
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
||||
{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
|
||||
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
|
||||
{-1},
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_I2C
|
||||
static struct module_pin_mux i2c0_pin_mux[] = {
|
||||
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
|
||||
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
|
||||
{-1},
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPI
|
||||
static struct module_pin_mux spi0_pin_mux[] = {
|
||||
{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
|
||||
{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
|
||||
{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
|
||||
{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
|
||||
{-1},
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct module_pin_mux gpio0_7_pin_mux[] = {
|
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux rmii1_pin_mux[] = {
|
||||
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
|
||||
{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
|
||||
{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
|
||||
{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
|
||||
{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
|
||||
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
|
||||
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
static struct module_pin_mux cbmux_pin_mux[] = {
|
||||
{OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
|
||||
{OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN}, /* JP4 */
|
||||
{-1},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_NAND
|
||||
static struct module_pin_mux nand_pin_mux[] = {
|
||||
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
|
||||
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
|
||||
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
|
||||
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
|
||||
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
|
||||
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
|
||||
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
|
||||
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
|
||||
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
|
||||
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
|
||||
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
|
||||
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
|
||||
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
|
||||
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
|
||||
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
|
||||
{-1},
|
||||
};
|
||||
#endif
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_i2c0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_board_pin_mux()
|
||||
{
|
||||
configure_module_pin_mux(rmii1_pin_mux);
|
||||
configure_module_pin_mux(mmc0_pin_mux);
|
||||
configure_module_pin_mux(cbmux_pin_mux);
|
||||
#ifdef CONFIG_NAND
|
||||
configure_module_pin_mux(nand_pin_mux);
|
||||
#endif
|
||||
#ifdef CONFIG_SPI
|
||||
configure_module_pin_mux(spi0_pin_mux);
|
||||
#endif
|
||||
}
|
||||
|
|
@ -238,6 +238,7 @@ am335x_evm_uart2 arm armv7 am335x ti
|
|||
am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4
|
||||
am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5
|
||||
am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6
|
||||
pcm051 arm armv7 pcm051 phytec am33xx pcm051
|
||||
highbank arm armv7 highbank - highbank
|
||||
mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
|
||||
mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
|
||||
|
|
|
|||
301
include/configs/pcm051.h
Normal file
301
include/configs/pcm051.h
Normal file
|
|
@ -0,0 +1,301 @@
|
|||
/*
|
||||
* pcm051.h
|
||||
*
|
||||
* Phytec phyCORE-AM335x (pcm051) boards information header
|
||||
*
|
||||
* Copyright (C) 2013 Lemonage Software GmbH
|
||||
* Author Lars Poeschel <poeschel@lemonage.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_PCM051_H
|
||||
#define __CONFIG_PCM051_H
|
||||
|
||||
#define CONFIG_AM33XX
|
||||
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#define CONFIG_DMA_COHERENT
|
||||
#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
|
||||
|
||||
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT "U-Boot# "
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#define MACH_TYPE_PCM051 4144 /* Until the next sync */
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_PCM051
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
|
||||
/* commands to include */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
|
||||
/* set to negative value for no autoboot */
|
||||
#define CONFIG_BOOTDELAY 1
|
||||
#define CONFIG_ENV_VARS_UBOOT_CONFIG
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr=0x80007fc0\0" \
|
||||
"fdtaddr=0x80000000\0" \
|
||||
"rdaddr=0x81000000\0" \
|
||||
"bootfile=uImage\0" \
|
||||
"fdtfile=pcm051.dtb\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"optargs=\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 ro\0" \
|
||||
"mmcrootfstype=ext4 rootwait\0" \
|
||||
"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
|
||||
"ramrootfstype=ext2\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||
"importbootenv=echo Importing environment from mmc ...; " \
|
||||
"env import -t $loadaddr $filesize\0" \
|
||||
"ramargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${ramroot} " \
|
||||
"rootfstype=${ramrootfstype}\0" \
|
||||
"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
|
||||
"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
|
||||
"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"ramboot=echo Booting from ramdisk ...; " \
|
||||
"run ramargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"echo SD/MMC found on device ${mmcdev};" \
|
||||
"if run loadbootenv; then " \
|
||||
"echo Loaded environment from ${bootenv};" \
|
||||
"run importbootenv;" \
|
||||
"fi;" \
|
||||
"if test -n $uenvcmd; then " \
|
||||
"echo Running uenvcmd ...;" \
|
||||
"run uenvcmd;" \
|
||||
"fi;" \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot;" \
|
||||
"fi;" \
|
||||
"fi;" \
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 25000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK)
|
||||
|
||||
#define CONFIG_CMD_ECHO
|
||||
|
||||
/* max number of command args */
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
|
||||
/* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_CBSIZE 512
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
|
||||
+ sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
/*
|
||||
* memtest works on 8 MB in DRAM after skipping 32MB from
|
||||
* start addr of ram disk
|
||||
*/
|
||||
#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024))
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
|
||||
+ (8 * 1024 * 1024))
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x80007fc0 /* Default load address */
|
||||
#define CONFIG_SYS_HZ 1000 /* 1ms clock */
|
||||
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_OMAP_HSMMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_EXT2
|
||||
|
||||
#define CONFIG_SPI
|
||||
#define CONFIG_OMAP3_SPI
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_WINBOND
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SF_DEFAULT_SPEED 24000000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
|
||||
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
|
||||
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 19) /* 512MiB */
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
/* Platform/Board specific defs */
|
||||
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
|
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
/* NS16550 Configuration */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK (48000000)
|
||||
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
|
||||
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
|
||||
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
|
||||
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
|
||||
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
|
||||
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
|
||||
|
||||
/* I2C Configuration */
|
||||
#define CONFIG_I2C
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 1
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_DRIVER_OMAP24XX_I2C
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_ENV_EEPROM_IS_ON_I2C
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||
|
||||
#define CONFIG_OMAP_GPIO
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
|
||||
4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_TEXT_BASE 0x402F0400
|
||||
#define CONFIG_SPL_MAX_SIZE (101 * 1024)
|
||||
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
|
||||
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
|
||||
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
|
||||
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
|
||||
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
|
||||
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#define CONFIG_SPL_FAT_SUPPORT
|
||||
#define CONFIG_SPL_I2C_SUPPORT
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBDISK_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
#define CONFIG_SPL_YMODEM_SUPPORT
|
||||
#define CONFIG_SPL_NET_SUPPORT
|
||||
#define CONFIG_SPL_NET_VCI_STRING "pcm051 U-Boot SPL"
|
||||
#define CONFIG_SPL_ETH_SUPPORT
|
||||
#define CONFIG_SPL_SPI_SUPPORT
|
||||
#define CONFIG_SPL_SPI_FLASH_SUPPORT
|
||||
#define CONFIG_SPL_SPI_LOAD
|
||||
#define CONFIG_SPL_SPI_BUS 0
|
||||
#define CONFIG_SPL_SPI_CS 0
|
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
||||
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
|
||||
|
||||
/*
|
||||
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
|
||||
* 64 bytes before this address should be set aside for u-boot.img's
|
||||
* header. That is 0x800FFFC0--0x80100000 should not be used for any
|
||||
* other needs.
|
||||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80800000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
|
||||
|
||||
/* Since SPL did pll and ddr initialization for us,
|
||||
* we don't need to do it twice.
|
||||
*/
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB configuration
|
||||
*/
|
||||
#define CONFIG_USB_MUSB_DSPS
|
||||
#define CONFIG_ARCH_MISC_INIT
|
||||
#define CONFIG_MUSB_GADGET
|
||||
#define CONFIG_MUSB_PIO_ONLY
|
||||
#define CONFIG_USB_GADGET_DUALSPEED
|
||||
#define CONFIG_MUSB_HOST
|
||||
#define CONFIG_AM335X_USB0
|
||||
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
|
||||
#define CONFIG_AM335X_USB1
|
||||
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
|
||||
|
||||
#ifdef CONFIG_MUSB_HOST
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MUSB_GADGET
|
||||
#define CONFIG_USB_ETHER
|
||||
#define CONFIG_USB_ETH_RNDIS
|
||||
#endif /* CONFIG_MUSB_GADGET */
|
||||
|
||||
/* Unsupported features */
|
||||
#undef CONFIG_USE_IRQ
|
||||
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_DRIVER_TI_CPSW
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_BOOTP_DEFAULT
|
||||
#define CONFIG_BOOTP_DNS
|
||||
#define CONFIG_BOOTP_DNS2
|
||||
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_NET_RETRY_COUNT 10
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PHY_GIGE
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ADDR 0
|
||||
#define CONFIG_PHY_SMSC
|
||||
|
||||
#endif /* ! __CONFIG_PCM051_H */
|
||||
Loading…
Add table
Reference in a new issue