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rockchip: rk3288: move SOC setting into arch_cpu_init()

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Qos setting and emmc relate SoC setting should go to arch_cpu_init().

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang 2019-07-22 20:02:10 +08:00
parent a97b65a7a0
commit 1e7d2be011
2 changed files with 28 additions and 30 deletions
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30
arch/arm/mach-rockchip/rk3288-board.c
View file

@ -13,7 +13,6 @@
#include <asm/arch-rockchip/cru_rk3288.h>
#include <asm/arch-rockchip/periph.h>
#include <asm/arch-rockchip/pmu_rk3288.h>
#include <asm/arch-rockchip/qos_rk3288.h>
#include <asm/arch-rockchip/boot_mode.h>
#include <asm/gpio.h>
#include <dt-bindings/clock/rk3288-cru.h>
@ -26,24 +25,6 @@ __weak int rk_board_late_init(void)
return 0;
}
int rk3288_qos_init(void)
{
int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
/* set vop qos to higher priority */
writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
if (!fdt_node_check_compatible(gd->fdt_blob, 0,
"rockchip,rk3288-tinker"))
{
/* set isp qos to higher priority */
writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
}
return 0;
}
static void rk3288_detect_reset_reason(void)
{
struct rk3288_cru *cru = rockchip_get_cru();
@ -84,7 +65,6 @@ static void rk3288_detect_reset_reason(void)
int board_late_init(void)
{
setup_boot_mode();
rk3288_qos_init();
rk3288_detect_reset_reason();
return rk_board_late_init();
@ -266,8 +246,6 @@ U_BOOT_CMD(
int board_early_init_f(void)
{
const uintptr_t GRF_SOC_CON0 = 0xff770244;
const uintptr_t GRF_SOC_CON2 = 0xff77024c;
struct udevice *dev;
int ret;
@ -282,13 +260,5 @@ int board_early_init_f(void)
return ret;
}
rk_setreg(GRF_SOC_CON2, 1 << 0);
/*
* Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
* cleared
*/
rk_clrreg(GRF_SOC_CON0, 1 << 12);
return 0;
}

28
arch/arm/mach-rockchip/rk3288/rk3288.c
View file

@ -2,12 +2,14 @@
/*
* Copyright (c) 2016 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <asm/armv7.h>
#include <asm/io.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/pmu_rk3288.h>
#include <asm/arch-rockchip/qos_rk3288.h>
#include <asm/arch-rockchip/sdram_common.h>
DECLARE_GLOBAL_DATA_PTR;
@ -40,6 +42,24 @@ static void configure_l2ctlr(void)
}
#endif
int rk3288_qos_init(void)
{
int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
/* set vop qos to higher priority */
writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
if (!fdt_node_check_compatible(gd->fdt_blob, 0,
"rockchip,rk3288-tinker")) {
/* set isp qos to higher priority */
writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
}
return 0;
}
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
@ -50,6 +70,14 @@ int arch_cpu_init(void)
/* Use rkpwm by default */
rk_setreg(&grf->soc_con2, 1 << 0);
/*
* Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
* cleared
*/
rk_clrreg(&grf->soc_con0, 1 << 12);
rk3288_qos_init();
#endif
return 0;