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am33xx:ddr:Fix config_sdram to work for all DDR
The original write to sdram_config is correct for DDR3 but incorrect for DDR2 so SPL was hanging. For DDR2, the write to sdram_config should be after the writes to ref_ctrl. This was working for DDR3 because there was a write of 0x2800 to ref_ctrl before a write to sdram_config. Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3), Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3) Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
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1e7e374b35
1 changed files with 4 additions and 1 deletions
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@ -54,10 +54,13 @@ void config_sdram(const struct emif_regs *regs)
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writel(0x2800, &emif_reg->emif_sdram_ref_ctrl);
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writel(regs->zq_config, &emif_reg->emif_zq_config);
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writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
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writel(regs->sdram_config, &emif_reg->emif_sdram_config);
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writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
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writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
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}
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writel(regs->sdram_config, &emif_reg->emif_sdram_config);
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writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
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writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
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writel(regs->sdram_config, &emif_reg->emif_sdram_config);
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}
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/**
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