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powerpc/P4080: Check SVR for CPU22 workaround
Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only. Signed-off-by: York Sun <yorksun@freescale.com>
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parent
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commit
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3 changed files with 15 additions and 4 deletions
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@ -51,7 +51,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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puts("Work-around for Erratum SERDES-A005 enabled\n");
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
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puts("Work-around for Erratum CPU22 enabled\n");
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if (SVR_MAJ(svr) < 3)
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puts("Work-around for Erratum CPU22 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
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puts("Work-around for Erratum CPU-A003999 enabled\n");
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@ -309,9 +309,11 @@ int cpu_init_r(void)
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
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flush_dcache();
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mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
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sync();
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if (SVR_MAJ(svr) < 3) {
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flush_dcache();
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mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
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sync();
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}
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#endif
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puts ("L2: ");
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@ -144,9 +144,17 @@ __secondary_start_page:
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
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/* apply to P4080 rev 1 and rev 2 */
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mfspr r3,SPRN_SVR
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rlwinm r3,r3,0,0xf0
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li r4,0x30
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cmpw r3,r4
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bge 2f
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mfspr r8,L1CSR2
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oris r8,r8,(L1CSR2_DCWS)@h
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mtspr L1CSR2,r8
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2:
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#endif
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#ifdef CONFIG_BACKSIDE_L2_CACHE
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