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mt7629: use linux kernel compatible SMP initialization
This patch changes mt7629 to use the compatible platform SMP initialization method of linux kernel. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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1 changed files with 44 additions and 8 deletions
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@ -5,6 +5,14 @@
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#include <linux/linkage.h>
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#define WAIT_CODE_SRAM_BASE 0x0010ff00
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#define SLAVE_JUMP_REG 0x10202034
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#define SLAVE1_MAGIC_REG 0x10202038
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#define SLAVE1_MAGIC_NUM 0x534c4131
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#define GIC_CPU_BASE 0x10320000
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ENTRY(lowlevel_init)
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#ifndef CONFIG_SPL_BUILD
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@ -28,6 +36,7 @@ ENTRY(lowlevel_init)
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mrc p15, 0, r0, c0, c0, 5
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ands r1, r0, #0x40000000
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bne go @ Go if UP
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/* read slave CPU number */
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ands r0, r0, #0x0f
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beq go @ Go if core0 on primary core tile
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b secondary
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@ -37,14 +46,41 @@ go:
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mov pc, lr
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secondary:
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/* read slave CPU number into r0 firstly */
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #0x0f
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/* enable GIC as cores will be waken up by IPI */
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ldr r2, =GIC_CPU_BASE
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mov r1, #0xf0
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str r1, [r2, #4]
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mov r1, #1
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str r1, [r2, #0]
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ldr r1, [r2]
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orr r1, #1
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str r1, [r2]
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/* copy wait code into SRAM */
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ldr r0, =slave_cpu_wait
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ldm r0, {r1 - r8} @ slave_cpu_wait has eight insns
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ldr r0, =WAIT_CODE_SRAM_BASE
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stm r0, {r1 - r8}
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/* pass args to slave_cpu_wait */
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ldr r0, =SLAVE1_MAGIC_REG
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ldr r1, =SLAVE1_MAGIC_NUM
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/* jump to wait code in SRAM */
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ldr pc, =WAIT_CODE_SRAM_BASE
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loop:
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dsb
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isb
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wfi @Zzz...
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b loop
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#endif
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ENDPROC(lowlevel_init)
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/* This function will be copied into SRAM */
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ENTRY(slave_cpu_wait)
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wfi
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ldr r2, [r0]
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cmp r2, r1
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bne slave_cpu_wait
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movw r0, #:lower16:SLAVE_JUMP_REG
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movt r0, #:upper16:SLAVE_JUMP_REG
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ldr r1, [r0]
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mov pc, r1
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ENDPROC(slave_cpu_wait)
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