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ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery
MSMC segment Privilege ID is not consistent accross the keystone2 SoCs. As the first step to ensure complete SoC wide coherency setup, lets refactor the macros to remove the #if-deffery around the code which obfuscates which IDs are actually enabled for which SoC. As a result of this change the PCIe configuration is moved after the msmc configuration is complete, but that should ideally have no functional impact. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
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4 changed files with 53 additions and 23 deletions
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@ -34,9 +34,6 @@
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#define KS2_LPSC_PCIE_1 27
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#define KS2_LPSC_PCIE_1 27
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#define KS2_LPSC_XGE 50
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#define KS2_LPSC_XGE 50
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/* MSMC */
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#define KS2_MSMC_SEGMENT_PCIE1 13
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/* Chip Interrupt Controller */
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/* Chip Interrupt Controller */
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#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
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#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
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#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
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#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
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@ -53,9 +53,6 @@
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#define KS2_LPSC_FFTC_B 49
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#define KS2_LPSC_FFTC_B 49
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#define KS2_LPSC_IQN_AIL 50
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#define KS2_LPSC_IQN_AIL 50
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/* MSMC */
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#define KS2_MSMC_SEGMENT_PCIE1 14
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/* Chip Interrupt Controller */
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/* Chip Interrupt Controller */
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#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
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#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
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#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
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#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
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@ -215,16 +215,23 @@ typedef volatile unsigned int *dv_reg_p;
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/* MSMC control */
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/* MSMC control */
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#define KS2_MSMC_CTRL_BASE 0x0bc00000
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#define KS2_MSMC_CTRL_BASE 0x0bc00000
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#define KS2_MSMC_DATA_BASE 0x0c000000
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#define KS2_MSMC_DATA_BASE 0x0c000000
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#ifndef CONFIG_SOC_K2G
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#define KS2_MSMC_SEGMENT_TETRIS 8
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/* KS2 HK/L/E MSMC PRIVIDs for MSMC2 */
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#define KS2_MSMC_SEGMENT_NETCP 9
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#define K2HKLE_MSMC_SEGMENT_ARM 8
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#define KS2_MSMC_SEGMENT_QM_PDSP 10
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#define K2HKLE_MSMC_SEGMENT_NETCP 9
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#define KS2_MSMC_SEGMENT_PCIE0 11
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#define K2HKLE_MSMC_SEGMENT_QM_PDSP 10
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#else
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#define K2HKLE_MSMC_SEGMENT_PCIE0 11
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#define KS2_MSMC_SEGMENT_TETRIS 1
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#define KS2_MSMC_SEGMENT_NETCP 4
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/* K2L specific Privilege ID Settings */
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#define KS2_MSMC_SEGMENT_PCIE0 5
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#define K2L_MSMC_SEGMENT_PCIE1 14
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#endif
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/* K2E specific Privilege ID Settings */
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#define K2E_MSMC_SEGMENT_PCIE1 13
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/* K2G specific Privilege ID Settings */
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#define K2G_MSMC_SEGMENT_ARM 1
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#define K2G_MSMC_SEGMENT_NSS 4
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#define K2G_MSMC_SEGMENT_PCIE 5
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/* MSMC segment size shift bits */
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/* MSMC segment size shift bits */
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#define KS2_MSMC_SEG_SIZE_SHIFT 12
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#define KS2_MSMC_SEG_SIZE_SHIFT 12
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@ -96,22 +96,51 @@ static void config_pcie_mode(int pcie_port, enum pci_mode mode)
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__raw_writel(val, KS2_DEVCFG);
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__raw_writel(val, KS2_DEVCFG);
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}
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}
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static void msmc_k2hkle_common_setup(void)
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{
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msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
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msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
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#ifdef KS2_MSMC_SEGMENT_QM_PDSP
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msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
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#endif
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msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
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}
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static inline void msmc_k2l_setup(void)
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{
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msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
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}
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static inline void msmc_k2e_setup(void)
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{
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msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
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}
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static inline void msmc_k2g_setup(void)
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{
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msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
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msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
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msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
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}
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int arch_cpu_init(void)
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int arch_cpu_init(void)
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{
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{
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chip_configuration_unlock();
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chip_configuration_unlock();
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icache_enable();
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icache_enable();
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msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
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if (cpu_is_k2g()) {
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msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
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msmc_k2g_setup();
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#ifdef KS2_MSMC_SEGMENT_QM_PDSP
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} else {
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msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
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msmc_k2hkle_common_setup();
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#endif
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if (cpu_is_k2e())
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msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
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msmc_k2e_setup();
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else if (cpu_is_k2l())
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msmc_k2l_setup();
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}
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/* Initialize the PCIe-0 to work as Root Complex */
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/* Initialize the PCIe-0 to work as Root Complex */
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config_pcie_mode(0, ROOTCOMPLEX);
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config_pcie_mode(0, ROOTCOMPLEX);
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#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
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#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
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msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
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/* Initialize the PCIe-1 to work as Root Complex */
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/* Initialize the PCIe-1 to work as Root Complex */
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config_pcie_mode(1, ROOTCOMPLEX);
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config_pcie_mode(1, ROOTCOMPLEX);
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#endif
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#endif
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