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imx: apbh_dma: Update APBH-DMA for MX7D

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Update APBH-DMA driver and head files to support i.MX7D

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan 2015-12-22 17:04:22 +08:00 • committed by Stefano Babic
parent c6d3d812fe
commit 1fc4f80495
3 changed files with 5 additions and 5 deletions
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2
arch/arm/include/asm/imx-common/dma.h
View file

@ -59,7 +59,7 @@ enum {
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1, MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS, MXS_MAX_DMA_CHANNELS,
}; };
#elif defined(CONFIG_MX6) #elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
enum { enum {
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0, MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1, MXS_DMA_CHANNEL_AHB_APBH_GPMI1,

6
arch/arm/include/asm/imx-common/regs-apbh.h
View file

@ -96,7 +96,7 @@ struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_version) mxs_reg_32(hw_apbh_version)
}; };
#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6)) #elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
struct mxs_apbh_regs { struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0) mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1) mxs_reg_32(hw_apbh_ctrl1)
@ -275,7 +275,7 @@ struct mxs_apbh_regs {
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 #define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 #define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
#elif defined(CONFIG_MX6) #elif (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
@ -391,7 +391,7 @@ struct mxs_apbh_regs {
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif #endif
#if defined(CONFIG_MX6) #if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#endif #endif

2
drivers/dma/apbh_dma.c
View file

@ -215,7 +215,7 @@ static int mxs_dma_reset(int channel)
#if defined(CONFIG_MX23) #if defined(CONFIG_MX23)
uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set); uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET; uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6)) #elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set); uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET; uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
#endif #endif