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board: phytec: phycore_imx8mp: Change debug UART
With the first redesign the debug UART had changed from UART2 to UART1. As the first hardware revision is considered as alpha and will not be supported in future. The old setup will not be preserved. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
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parent
3240d9c63a
commit
1feac813fe
4 changed files with 13 additions and 13 deletions
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@ -18,7 +18,7 @@
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u-boot,dm-spl;
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};
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&pinctrl_uart2 {
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&pinctrl_uart1 {
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u-boot,dm-spl;
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};
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@ -54,7 +54,7 @@
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u-boot,dm-spl;
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};
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&uart2 {
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&uart1 {
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u-boot,dm-spl;
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};
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@ -16,7 +16,7 @@
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"phytec,imx8mp-phycore-som", "fsl,imx8mp";
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chosen {
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stdout-path = &uart2;
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stdout-path = &uart1;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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@ -95,9 +95,9 @@
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};
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/* debug console */
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&uart2 {
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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@ -154,10 +154,10 @@
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>;
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};
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pinctrl_uart2: uart2grp {
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
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MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
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MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49
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MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49
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>;
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};
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@ -80,8 +80,8 @@ int board_fit_config_name_match(const char *name)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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static iomux_v3_cfg_t const uart_pads[] = {
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MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const wdog_pads[] = {
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@ -107,7 +107,7 @@ void board_init_f(ulong dummy)
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arch_cpu_init();
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init_uart_clk(1);
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init_uart_clk(0);
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board_early_init_f();
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@ -39,7 +39,7 @@
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"image=Image\0" \
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"console=ttymxc1,115200\0" \
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"console=ttymxc0,115200\0" \
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"fdt_addr=0x48000000\0" \
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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@ -87,7 +87,7 @@
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#define PHYS_SDRAM_SIZE 0x80000000
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/* UART */
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#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
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#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE SZ_2K
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