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PMC405 and CPCI405: Moved configuration of pci resources into config file.

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PMC405 and CPCI2DP: Added firmware download and booting via pci.

Patch by Matthias Fuchs, 20 Dec 2005
This commit is contained in:
Stefan Roese 2006-01-18 20:03:15 +01:00
parent c4b465f63e
commit 2076d0a15f
13 changed files with 249 additions and 73 deletions
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5
CHANGELOG
View file

@ -2,6 +2,11 @@
Changes since U-Boot 1.1.4:
======================================================================
* PMC405 and CPCI405: Moved configuration of pci resources
into config file.
PMC405 and CPCI2DP: Added firmware download and booting via pci.
Patch by Matthias Fuchs, 20 Dec 2005
* Fix 28F256J3A support on PM520 board
(without bank-switching only 32 MB can be accessed)

123
board/esd/common/cmd_loadpci.c Normal file
View file

@ -0,0 +1,123 @@
/*
* (C) Copyright 2005
* Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#if (CONFIG_COMMANDS & CFG_CMD_BSP)
extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
extern int do_autoscript (cmd_tbl_t *, int, int, char *[]);
#define ADDRMASK 0xfffff000
/*
* Command loadpci: wait for signal from host and boot image.
*/
int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned int *ptr = 0;
int count = 0;
int count2 = 0;
char addr[16];
char str[] = "\\|/-";
char *local_args[2];
while(1) {
/*
* Mark sync address
*/
ptr = 0;
memset(ptr, 0, 0x20);
*ptr = 0xffffffff;
puts("\nWaiting for action from pci host -");
/*
* Wait for host to write the start address
*/
while (*ptr == 0xffffffff) {
count++;
if (!(count % 100)) {
count2++;
putc(0x08); /* backspace */
putc(str[count2 % 4]);
}
/* Abort if ctrl-c was pressed */
if (ctrlc()) {
puts("\nAbort\n");
return 0;
}
udelay(1000);
}
printf("\nGot bootcode %08x: ", *ptr);
sprintf(addr, "%08x", *ptr & ADDRMASK);
switch (*ptr & ~ADDRMASK) {
case 0:
/*
* Boot image via bootm
*/
printf("booting image at addr 0x%s ...\n", addr);
setenv("loadaddr", addr);
do_bootm (cmdtp, 0, 0, NULL);
break;
case 1:
/*
* Boot image via autoscr
*/
printf("executing script at addr 0x%s ...\n", addr);
local_args[0] = addr;
local_args[1] = NULL;
do_autoscript(cmdtp, 0, 1, local_args);
break;
case 2:
/*
* Call run_cmd
*/
printf("running command at addr 0x%s ...\n", addr);
run_command ((char*)(*ptr & ADDRMASK), 0);
break;
default:
printf("unhandled boot method\n");
break;
}
}
}
U_BOOT_CMD(
loadpci, 1, 1, do_loadpci,
"loadpci - Wait for pci bootcmd and boot it\n",
NULL
);
#endif

2
board/esd/cpci2dp/Makefile
View file

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o ../common/misc.o
OBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)

32
board/esd/cpci2dp/cpci2dp.c
View file

@ -31,17 +31,15 @@ int board_early_init_f (void)
unsigned long cntrl0Reg;
/*
* Setup GPIO pins (CS4+CS7 as GPIO)
* Setup GPIO pins
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00900000);
mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5));
/* set output pins to high */
out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED);
/* INTA# is open drain */
out32(GPIO0_ODR, CFG_INTA_FAKE);
/* setup for output */
out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP);
/* set output pins to high */
out32(GPIO0_OR, CFG_EEPROM_WP);
/* setup for output (LED=off) */
out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED);
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
@ -130,16 +128,6 @@ long int initdram (int board_type)
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 64 MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
@ -207,8 +195,8 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
eepwren, 2, 0, do_eep_wren,
"eepwren - Enable / disable / query EEPROM write access\n",
NULL
);
eepwren, 2, 0, do_eep_wren,
"eepwren - Enable / disable / query EEPROM write access\n",
NULL
);
#endif /* #if defined(CFG_EEPROM_WREN) */

2
board/esd/pmc405/Makefile
View file

@ -30,7 +30,7 @@ CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
../common/xilinx_jtag/ports.o
OBJS = $(BOARD).o ../common/misc.o $(CPLD)
OBJS = $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)

81
board/esd/pmc405/pmc405.c
View file

@ -1,6 +1,9 @@
/*
* (C) Copyright 2001-2003
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2005
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
@ -66,16 +69,27 @@ int board_early_init_f (void)
mtebc (epcr, 0xa8400000);
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
* Setup GPIO pins
*/
mtdcr(cntrl0, mfdcr(cntrl0) | 0x00300000);
/*
* Configure GPIO pins
mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \
CFG_FPGA_DONE | \
CFG_XEREADY | \
CFG_NONMONARCH | \
CFG_REV1_2) << 5));
if (!(in32(GPIO0_IR) & CFG_REV1_2)) {
/* rev 1.2 boards */
mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \
CFG_SELF_RST) << 5));
}
out32(GPIO0_OR, 0);
out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */
/* - check if rev1_2 is low, then:
* - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST#
*/
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA); /* setup for output */
out32(GPIO0_OR, 0); /* outputs -> low */
return 0;
}
@ -83,11 +97,6 @@ int board_early_init_f (void)
/* ------------------------------------------------------------------------- */
int misc_init_f (void)
{
return 0; /* dummy implementation */
}
int misc_init_r (void)
{
@ -97,16 +106,30 @@ int misc_init_r (void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */
return (0);
}
ushort pmc405_pci_subsys_deviceid(void)
{
ulong val;
val = in32(GPIO0_IR);
if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
if (val & CFG_NONMONARCH) { /* monarch# signal */
return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
}
return CFG_PCI_SUBSYS_DEVICEID_MONARCH;
}
return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
}
/*
* Check Board Identity:
*/
int checkboard (void)
{
ulong val;
char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
@ -118,12 +141,18 @@ int checkboard (void)
puts(str);
}
putc ('\n');
val = in32(GPIO0_IR);
if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
puts(" rev1.2 (");
if (val & CFG_NONMONARCH) { /* monarch# signal */
puts("non-");
}
puts("monarch)");
} else {
puts(" <=rev1.1");
}
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
putc ('\n');
return 0;
}
@ -145,17 +174,19 @@ long int initdram (int board_type)
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
/* ------------------------------------------------------------------------- */
int testdram (void)
void reset_phy(void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
#ifdef CONFIG_LXT971_NO_SLEEP
return (0);
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
#endif
}
/* ------------------------------------------------------------------------- */
int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{

9
cpu/ppc4xx/405gp_pci.c
View file

@ -81,6 +81,10 @@
#ifdef CONFIG_PCI
#if defined(CONFIG_PMC405)
ushort pmc405_pci_subsys_deviceid(void);
#endif
/*#define DEBUG*/
/*-----------------------------------------------------------------------------+
@ -96,13 +100,10 @@ void pci_405gp_init(struct pci_controller *hose)
unsigned short temp_short;
unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart};
unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1};
char *ptmla_str, *ptmms_str;
#else
#endif
unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
#endif
#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};

10
include/configs/CPCI2DP.h
View file

@ -143,8 +143,9 @@
#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CFG_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */
#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */
#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */
@ -250,14 +251,15 @@
#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* GPIO definitions
*/
#define CFG_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */
#define CFG_SELF_RST (0x80000000 >> 14) /* GPIO14 */
#define CFG_PB_LED (0x80000000 >> 16) /* GPIO16 */
#define CFG_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */

4
include/configs/CPCI405.h
View file

@ -151,8 +151,8 @@
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */

4
include/configs/CPCI4052.h
View file

@ -178,8 +178,8 @@
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */

4
include/configs/CPCI405AB.h
View file

@ -161,8 +161,8 @@
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */

4
include/configs/CPCI405DT.h
View file

@ -183,8 +183,8 @@
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */

42
include/configs/PMC405.h
View file

@ -53,9 +53,15 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_BSP | \
@ -154,15 +160,24 @@
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
#define CFG_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID: Non-Monarch */
#define CFG_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID: Monarch */
#define CFG_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#if 1
#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs */
#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */
#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
#else /* old mapping */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
#endif
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
@ -259,7 +274,7 @@
#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
#define CAN_BA 0xF0000000 /* CAN Base Address */
#define RTC_BA 0xF0000500 /* RTC Base Address */
#define CF_BA 0xF0100000 /* CompactFlash Base Address */
#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
/* Memory Bank 0 (Flash Bank 0) initialization */
#define CFG_EBC_PB0AP 0x92015480
@ -273,9 +288,11 @@
#define CFG_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */
#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
/* Memory Bank 3 -> unused */
/* Memory Bank 4 (NVRAM) initialization */
#define CFG_EBC_PB4AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
#define CFG_EBC_PB4CR NVRAM_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/*-----------------------------------------------------------------------
* FPGA stuff
@ -292,6 +309,15 @@
#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
/*-----------------------------------------------------------------------
* GPIOs
*/
#define CFG_NONMONARCH (0x80000000 >> 14) /* GPIO24 */
#define CFG_XEREADY (0x80000000 >> 15) /* GPIO15 */
#define CFG_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
#define CFG_SELF_RST (0x80000000 >> 21) /* GPIO21 */
#define CFG_REV1_2 (0x80000000 >> 23) /* GPIO23 */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/