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omap3_spi: introduce CONFIG_OMAP3_SPI_D0_D1_SWAPPED

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D0/D1 Swapped or not is a board property, not anything specific to
the am33xx SoC, so add a custom define for it.

At the same time correct the bit handling for the swapped mode
(DPE0 should be cleared and SI/DPE1 set).

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
This commit is contained in:
Peter Korsgaard 2012-10-17 09:20:46 +00:00 • committed by Tom Rini
parent 8f1fae26a7
commit 22cbeed454
1 changed files with 5 additions and 6 deletions
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11
drivers/spi/omap3_spi.c
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@ -173,14 +173,13 @@ int spi_claim_bus(struct spi_slave *slave)
/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
* REVISIT: this controller could support SPI_3WIRE mode. * REVISIT: this controller could support SPI_3WIRE mode.
*/ */
#ifdef CONFIG_AM33XX #ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED
/* /*
* The reference design on AM33xx has D0 and D1 wired up opposite * Some boards have D0 wired as MOSI / D1 as MISO instead of
* of how it has been done on previous platforms. We assume that * The normal D0 as MISO / D1 as MOSI.
* custom hardware will also follow this convention.
*/ */
conf &= OMAP3_MCSPI_CHCONF_DPE0; conf &= ~OMAP3_MCSPI_CHCONF_DPE0;
conf |= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1); conf |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
#else #else
conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1); conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
conf |= OMAP3_MCSPI_CHCONF_DPE0; conf |= OMAP3_MCSPI_CHCONF_DPE0;