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board: sama5d2_xplained: Make SPL work on spiflash
Because before switching to a lower clock source, we must switch the clock source first instead of last. So before configuring the PMC_MCKR register, invoke at91_mck_init_down() first. As said in datasheet, the the size of SPL must not exceed the maximum size allowed(64Kbytes). Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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2 changed files with 11 additions and 1 deletions
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@ -247,6 +247,16 @@ void at91_pmc_init(void)
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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u32 tmp;
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/*
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* while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
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* so we need to slow down and configure MCKR accordingly.
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* This is why we have a special flavor of the switching function.
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*/
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tmp = AT91_PMC_MCKR_PLLADIV_2 |
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AT91_PMC_MCKR_MDIV_3 |
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AT91_PMC_MCKR_CSS_MAIN;
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at91_mck_init_down(tmp);
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tmp = AT91_PMC_PLLAR_29 |
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AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
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AT91_PMC_PLLXR_MUL(82) |
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@ -61,7 +61,7 @@
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/* SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x200000
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#define CONFIG_SPL_MAX_SIZE 0x18000
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#define CONFIG_SPL_MAX_SIZE 0x10000
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#define CONFIG_SPL_BSS_START_ADDR 0x20000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
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