mirror of
https://github.com/Fishwaldo/u-boot.git
synced 2025-03-18 13:11:31 +00:00
- Kconfig dependency fix for USB_KEYBOARD - musb gadget fixes / enhancements
This commit is contained in:
commit
23ab54e093
13 changed files with 85 additions and 482 deletions
1
Makefile
1
Makefile
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@ -792,6 +792,7 @@ libs-y += drivers/usb/dwc3/
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libs-y += drivers/usb/common/
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libs-y += drivers/usb/emul/
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libs-y += drivers/usb/eth/
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libs-$(CONFIG_USB_DEVICE) += drivers/usb/gadget/
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libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/
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libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/udc/
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libs-y += drivers/usb/host/
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@ -179,6 +179,8 @@ void early_system_init(void)
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hw_data_init();
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}
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#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
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!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
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/******************************************************************************
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* Routine: s_init
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* Description: Does early system init of muxing and clocks.
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@ -207,6 +209,7 @@ void s_init(void)
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ehci_clocks_enable();
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#endif
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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@ -45,7 +45,7 @@ ENDPROC(do_omap3_emu_romcode_call)
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ENTRY(cpy_clk_code)
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/* Copy DPLL code into SRAM */
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adr r0, go_to_speed /* copy from start of go_to_speed... */
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adr r2, lowlevel_init /* ... up to start of low_level_init */
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adr r2, go_to_speed_end /* ... up to start of go_to_speed_end */
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next2:
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ldmia r0!, {r3 - r10} /* copy from source address [r0] */
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stmia r1!, {r3 - r10} /* copy to target address [r1] */
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@ -167,8 +167,11 @@ pll_div_add5:
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pll_div_val5:
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.word CLSEL1_EMU_VAL
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go_to_speed_end:
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#endif
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#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
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!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
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ENTRY(lowlevel_init)
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ldr sp, SRAM_STACK
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str ip, [sp] /* stash ip register */
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@ -187,6 +190,7 @@ ENTRY(lowlevel_init)
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b s_init
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ENDPROC(lowlevel_init)
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#endif
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/* the literal pools origin */
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.ltorg
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@ -40,9 +40,24 @@
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mmc_host_def.h>
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#include "rx51.h"
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#include "tag_omap.h"
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/* Needed for ROM SMC call */
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struct emu_hal_params_rx51 {
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u32 num_params;
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u32 param1;
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u32 param2;
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u32 param3;
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u32 param4;
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};
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#define ONENAND_GPMC_CONFIG1_RX51 0xfb001202
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#define ONENAND_GPMC_CONFIG2_RX51 0x00111100
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#define ONENAND_GPMC_CONFIG3_RX51 0x00020200
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#define ONENAND_GPMC_CONFIG4_RX51 0x11001102
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#define ONENAND_GPMC_CONFIG5_RX51 0x03101616
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#define ONENAND_GPMC_CONFIG6_RX51 0x90060000
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DECLARE_GLOBAL_DATA_PTR;
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GraphicDevice gdev;
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@ -468,17 +483,6 @@ int misc_init_r(void)
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_RX51();
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}
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static unsigned long int twl_wd_time; /* last time of watchdog reset */
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static unsigned long int twl_i2c_lock;
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@ -1,377 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2012
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* Ивайло Димитров <freemangordon@abv.bg>
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*
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* (C) Copyright 2011-2012
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* Pali Rohár <pali@kernel.org>
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*
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* (C) Copyright 2008
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* Dirk Behme <dirk.behme@gmail.com>
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*/
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#ifndef _RX51_H_
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#define _RX51_H_
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/* Needed for ROM SMC call */
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struct emu_hal_params_rx51 {
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u32 num_params;
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u32 param1;
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u32 param2;
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u32 param3;
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u32 param4;
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};
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/*
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* IEN - Input Enable
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* IDIS - Input Disable
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* PTD - Pull type Down
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* PTU - Pull type Up
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* DIS - Pull type selection is inactive
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* EN - Pull type selection is active
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* M0 - Mode 0
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* The commented string gives the final mux configuration for that pin
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*/
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#define MUX_RX51() \
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/* SDRC */\
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
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/* GPMC */\
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MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
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MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
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MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
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MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
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MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
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MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
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MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
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MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
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MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
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MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
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MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
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MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
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MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
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MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
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MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
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MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
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MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
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MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
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MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
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MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
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MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
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MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
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MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
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MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
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MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
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MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
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MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
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MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
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MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
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MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
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MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
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MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*nDMA_REQ2*/\
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MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*nDMA_REQ3*/\
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MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
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MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
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MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
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MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV*/\
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
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MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0*/\
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
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MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
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MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
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/* DSS */\
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MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
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MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
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MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
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MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
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MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
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MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
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MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
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MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
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MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
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MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
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MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
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MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
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MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
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MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
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MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
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MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
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MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
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MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
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MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
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MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
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MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
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MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
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MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
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MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
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MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
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MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
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MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
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MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
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/* CAMERA */\
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MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS*/\
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MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS*/\
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MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
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MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
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MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
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MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
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MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
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MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
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MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
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MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
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MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
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MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
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MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
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MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
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MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
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MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
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MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
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MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
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MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
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MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
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MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
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MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
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MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
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MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
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/* Audio Interface */\
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||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLK*/\
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
|
||||
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
|
||||
/* Expansion card */\
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
|
||||
/* Wireless LAN */\
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
|
||||
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
|
||||
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
|
||||
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
|
||||
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
|
||||
/* Bluetooth */\
|
||||
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
|
||||
MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144*/\
|
||||
MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
|
||||
MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
|
||||
/* Modem Interface */\
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\
|
||||
MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT*/\
|
||||
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG*/\
|
||||
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY*/\
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
|
||||
MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
|
||||
/* Serial Interface */\
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS*/\
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS*/\
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX*/\
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DA0*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DA1*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DA2*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DA3*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DA4*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DA5*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DA6*/\
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DA7*/\
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
|
||||
MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4)) /*GPIO_171*/\
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4)) /*GPIO_172*/\
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOM*/\
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
|
||||
/* USB EHCI (port 2) */\
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DA2*/\
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DA7*/\
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DA4*/\
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DA5*/\
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DA6*/\
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DA3*/\
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DA0*/\
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DA1*/\
|
||||
/* Control and debug */\
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*MMC1_WP*/\
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MD*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT*/\
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA0*/\
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA1*/\
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA2*/\
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA7*/\
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA4*/\
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA5*/\
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA6*/\
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DA3*/\
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
|
||||
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
|
||||
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
|
||||
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
|
||||
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
|
||||
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
|
||||
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
|
||||
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
|
||||
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
|
||||
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
|
||||
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
|
||||
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
|
||||
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
|
||||
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
|
||||
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
|
||||
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
|
||||
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
|
||||
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
|
||||
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
|
||||
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
|
||||
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
|
||||
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
|
||||
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
|
||||
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
|
||||
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
|
||||
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
|
||||
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
|
||||
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
|
||||
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
|
||||
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
|
||||
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
|
||||
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
|
||||
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
|
||||
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26m*/\
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespw*/\
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswa*/\
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9ni*/\
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6*/\
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmare0*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmare1*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmare2*/\
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmare3*/\
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrs*/\
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtc*/\
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeu*/\
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlere*/\
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleac*/\
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusfl*/\
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusfl*/\
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
|
||||
|
||||
#define MUX_RX51_C() \
|
||||
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M4)) /*GPIO_140*/\
|
||||
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M4)) /*GPIO_142*/\
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_141*/\
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
|
||||
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
|
||||
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/
|
||||
|
||||
#define ONENAND_GPMC_CONFIG1_RX51 0xfb001202
|
||||
#define ONENAND_GPMC_CONFIG2_RX51 0x00111100
|
||||
#define ONENAND_GPMC_CONFIG3_RX51 0x00020200
|
||||
#define ONENAND_GPMC_CONFIG4_RX51 0x11001102
|
||||
#define ONENAND_GPMC_CONFIG5_RX51 0x03101616
|
||||
#define ONENAND_GPMC_CONFIG6_RX51 0x90060000
|
||||
|
||||
#endif
|
|
@ -4,6 +4,7 @@ CONFIG_ARCH_OMAP2PLUS=y
|
|||
CONFIG_SYS_TEXT_BASE=0x80008000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_TARGET_NOKIA_RX51=y
|
||||
CONFIG_OPTIMIZE_INLINING=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
# CONFIG_FIT is not set
|
||||
CONFIG_BOOTDELAY=30
|
||||
|
@ -12,6 +13,7 @@ CONFIG_AUTOBOOT_MENU_SHOW=y
|
|||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_PREBOOT="run preboot"
|
||||
CONFIG_CONSOLE_MUX=y
|
||||
# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="Nokia RX-51 # "
|
||||
# CONFIG_CMD_BDI is not set
|
||||
|
@ -46,9 +48,11 @@ CONFIG_ENV_OVERWRITE=y
|
|||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
# CONFIG_NET is not set
|
||||
CONFIG_DM=y
|
||||
# CONFIG_DM_WARN is not set
|
||||
# CONFIG_DM_DEVICE_REMOVE is not set
|
||||
# CONFIG_DM_SEQ_ALIAS is not set
|
||||
# CONFIG_BLOCK_CACHE is not set
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_TWL4030_LED=y
|
||||
CONFIG_DM_MMC=y
|
||||
# CONFIG_MMC_HW_PARTITIONING is not set
|
||||
# CONFIG_MMC_VERBOSE is not set
|
||||
|
@ -58,10 +62,8 @@ CONFIG_CONS_INDEX=3
|
|||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MUSB_HCD=y
|
||||
CONFIG_USB_MUSB_UDC=y
|
||||
CONFIG_USB_OMAP3=y
|
||||
CONFIG_TWL4030_USB=y
|
||||
CONFIG_CFB_CONSOLE=y
|
||||
CONFIG_CFB_CONSOLE_ANSI=y
|
||||
# CONFIG_VGA_AS_SINGLE_DEVICE is not set
|
||||
|
|
|
@ -24,8 +24,7 @@ called u-boot-gen-combined. It is available in following repository:
|
|||
There is support for hardware watchdog. Hardware watchdog is started by
|
||||
NOLO so u-boot must kick watchdog to prevent reboot device (but not very
|
||||
often, max every 2 seconds). There is also support for framebuffer display
|
||||
output with ANSI escape codes and the N900 HW keyboard input. USB tty works
|
||||
but is disabled because it prevents the current Maemo kernel from booting.
|
||||
output with ANSI escape codes and the N900 HW keyboard input.
|
||||
|
||||
When U-Boot is starting it enable IBE bit in Auxiliary Control Register,
|
||||
which is needed for Thumb-2 ISA support. It is workaround for errata 430973.
|
||||
|
@ -49,10 +48,6 @@ Boot from SD or eMMC in this order:
|
|||
|
||||
Available additional commands/variables:
|
||||
|
||||
* run sercon - Use serial port for control
|
||||
* run usbcon - Use usbtty for control
|
||||
* run vgacon - Use framebuffer and HW keyboard for control (default)
|
||||
|
||||
* run sdboot - Boot from external SD card (see boot order)
|
||||
* run emmcboot - Boot from internal eMMC memory (see boot order)
|
||||
* run attachboot - Boot attached kernel image (attached to U-Boot binary)
|
||||
|
@ -87,14 +82,6 @@ Additional variables for booting kernel:
|
|||
and u-boot standard output is set to serial then setup_console_atag is
|
||||
automatically set to 1. So output from Maemo kernel would go to serial port.
|
||||
|
||||
USB TTY:
|
||||
|
||||
Maemo kernel 2.6.28 will crash if u-boot enable usb tty. So USB TTY is disabled.
|
||||
For enabling USB TTY just add this line to file include/configs/nokia_rx51.h
|
||||
|
||||
#define CONFIG_USB_TTY
|
||||
|
||||
|
||||
UBIFS support:
|
||||
|
||||
UBIFS support is disabled, because U-Boot image is too big and cannot be
|
||||
|
|
|
@ -500,8 +500,8 @@ void usbtty_puts(struct stdio_dev *dev, const char *str)
|
|||
n = next_nl_pos (str);
|
||||
|
||||
if (str[n] == '\n') {
|
||||
__usbtty_puts("\r", 1);
|
||||
__usbtty_puts(str, n + 1);
|
||||
__usbtty_puts(str, n);
|
||||
__usbtty_puts("\r\n", 2);
|
||||
str += (n + 1);
|
||||
len -= (n + 1);
|
||||
} else {
|
||||
|
@ -849,17 +849,9 @@ static int write_buffer (circbuf_t * buf)
|
|||
&endpoint_instance[tx_endpoint];
|
||||
struct urb *current_urb = NULL;
|
||||
|
||||
current_urb = next_urb (device_instance, endpoint);
|
||||
|
||||
if (!current_urb) {
|
||||
TTYERR ("current_urb is NULL, buf->size %d\n",
|
||||
buf->size);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* TX data still exists - send it now
|
||||
*/
|
||||
if(endpoint->sent < current_urb->actual_length){
|
||||
if(endpoint->sent < endpoint->tx_urb->actual_length){
|
||||
if(udc_endpoint_write (endpoint)){
|
||||
/* Write pre-empted by RX */
|
||||
return -1;
|
||||
|
@ -878,6 +870,8 @@ static int write_buffer (circbuf_t * buf)
|
|||
*/
|
||||
while (buf->size > 0) {
|
||||
|
||||
current_urb = next_urb (device_instance, endpoint);
|
||||
|
||||
dest = (char*)current_urb->buffer +
|
||||
current_urb->actual_length;
|
||||
|
||||
|
|
|
@ -95,6 +95,7 @@ config USB_STORAGE
|
|||
|
||||
config USB_KEYBOARD
|
||||
bool "USB Keyboard support"
|
||||
select DM_KEYBOARD if DM_USB
|
||||
select SYS_STDIO_DEREGISTER
|
||||
---help---
|
||||
Say Y here if you want to use a USB keyboard for U-Boot command line
|
||||
|
|
|
@ -294,7 +294,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device,
|
|||
{
|
||||
struct usb_string_descriptor *string_descriptor;
|
||||
if (!(string_descriptor = usbd_get_string (index))) {
|
||||
serial_printf("Invalid string index %d\n", index);
|
||||
dbg_ep0(0, "Invalid string index %d\n", index);
|
||||
return -1;
|
||||
}
|
||||
dbg_ep0(3, "string_descriptor: %p length %d", string_descriptor, string_descriptor->bLength);
|
||||
|
@ -302,14 +302,14 @@ static int ep0_get_descriptor (struct usb_device_instance *device,
|
|||
}
|
||||
break;
|
||||
case USB_DESCRIPTOR_TYPE_INTERFACE:
|
||||
serial_printf("USB_DESCRIPTOR_TYPE_INTERFACE - error not implemented\n");
|
||||
dbg_ep0(2, "USB_DESCRIPTOR_TYPE_INTERFACE - error not implemented\n");
|
||||
return -1;
|
||||
case USB_DESCRIPTOR_TYPE_ENDPOINT:
|
||||
serial_printf("USB_DESCRIPTOR_TYPE_ENDPOINT - error not implemented\n");
|
||||
dbg_ep0(2, "USB_DESCRIPTOR_TYPE_ENDPOINT - error not implemented\n");
|
||||
return -1;
|
||||
case USB_DESCRIPTOR_TYPE_HID:
|
||||
{
|
||||
serial_printf("USB_DESCRIPTOR_TYPE_HID - error not implemented\n");
|
||||
dbg_ep0(2, "USB_DESCRIPTOR_TYPE_HID - error not implemented\n");
|
||||
return -1; /* unsupported at this time */
|
||||
#if 0
|
||||
int bNumInterface =
|
||||
|
@ -338,7 +338,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device,
|
|||
break;
|
||||
case USB_DESCRIPTOR_TYPE_REPORT:
|
||||
{
|
||||
serial_printf("USB_DESCRIPTOR_TYPE_REPORT - error not implemented\n");
|
||||
dbg_ep0(2, "USB_DESCRIPTOR_TYPE_REPORT - error not implemented\n");
|
||||
return -1; /* unsupported at this time */
|
||||
#if 0
|
||||
int bNumInterface =
|
||||
|
@ -531,7 +531,7 @@ int ep0_recv_setup (struct urb *urb)
|
|||
le16_to_cpu (request->wValue) & 0xff);
|
||||
|
||||
case USB_REQ_GET_CONFIGURATION:
|
||||
serial_printf("get config %d\n", device->configuration);
|
||||
dbg_ep0(2, "get config %d\n", device->configuration);
|
||||
return ep0_get_one (device, urb,
|
||||
device->configuration);
|
||||
|
||||
|
@ -621,14 +621,14 @@ int ep0_recv_setup (struct urb *urb)
|
|||
device->interface = device->alternate = 0;
|
||||
|
||||
/*dbg_ep0(2, "set configuration: %d", device->configuration); */
|
||||
/*serial_printf("DEVICE_CONFIGURED.. event?\n"); */
|
||||
/*dbg_ep0(2, "DEVICE_CONFIGURED.. event?\n"); */
|
||||
return 0;
|
||||
|
||||
case USB_REQ_SET_INTERFACE:
|
||||
device->interface = le16_to_cpu (request->wIndex);
|
||||
device->alternate = le16_to_cpu (request->wValue);
|
||||
/*dbg_ep0(2, "set interface: %d alternate: %d", device->interface, device->alternate); */
|
||||
serial_printf("DEVICE_SET_INTERFACE.. event?\n");
|
||||
dbg_ep0(2, "DEVICE_SET_INTERFACE.. event?\n");
|
||||
return 0;
|
||||
|
||||
case USB_REQ_GET_STATUS:
|
||||
|
|
|
@ -50,7 +50,7 @@ void musb_start(void)
|
|||
# define config_fifo(dir, idx, addr) \
|
||||
do { \
|
||||
writeb(idx, &musbr->dir##fifosz); \
|
||||
writew(fifoaddr >> 3, &musbr->dir##fifoadd); \
|
||||
writew(addr, &musbr->dir##fifoadd); \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
|
@ -66,14 +66,14 @@ void musb_start(void)
|
|||
void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt)
|
||||
{
|
||||
u16 csr;
|
||||
u16 fifoaddr = 64; /* First 64 bytes of FIFO reserved for EP0 */
|
||||
u16 fifoaddr = 64 >> 3; /* First 64 bytes of FIFO reserved for EP0 */
|
||||
u32 fifosize;
|
||||
u8 idx;
|
||||
|
||||
while (cnt--) {
|
||||
/* prepare fifosize to write to register */
|
||||
fifosize = epinfo->epsize >> 3;
|
||||
idx = ffs(fifosize) - 1;
|
||||
idx = fifosize ? ((ffs(fifosize) - 1) & 0xF) : 0;
|
||||
|
||||
writeb(epinfo->epnum, &musbr->index);
|
||||
if (epinfo->epdir) {
|
||||
|
@ -81,10 +81,8 @@ void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt)
|
|||
config_fifo(tx, idx, fifoaddr);
|
||||
|
||||
csr = readw(&musbr->txcsr);
|
||||
#if defined(CONFIG_USB_MUSB_HCD)
|
||||
/* clear the data toggle bit */
|
||||
writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr);
|
||||
#endif
|
||||
/* Flush fifo if required */
|
||||
if (csr & MUSB_TXCSR_TXPKTRDY)
|
||||
writew(csr | MUSB_TXCSR_FLUSHFIFO,
|
||||
|
@ -94,16 +92,14 @@ void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt)
|
|||
config_fifo(rx, idx, fifoaddr);
|
||||
|
||||
csr = readw(&musbr->rxcsr);
|
||||
#if defined(CONFIG_USB_MUSB_HCD)
|
||||
/* clear the data toggle bit */
|
||||
writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr);
|
||||
#endif
|
||||
/* Flush fifo if required */
|
||||
if (csr & MUSB_RXCSR_RXPKTRDY)
|
||||
writew(csr | MUSB_RXCSR_FLUSHFIFO,
|
||||
&musbr->rxcsr);
|
||||
}
|
||||
fifoaddr += epinfo->epsize;
|
||||
fifoaddr += 1 << idx;
|
||||
epinfo++;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -104,6 +104,8 @@ struct usb_endpoint_instance *ep0_endpoint;
|
|||
static struct usb_device_instance *udc_device;
|
||||
static int enabled;
|
||||
|
||||
static u16 pending_intrrx;
|
||||
|
||||
#ifdef MUSB_DEBUG
|
||||
static void musb_db_regs(void)
|
||||
{
|
||||
|
@ -629,7 +631,7 @@ static void musb_peri_ep0(void)
|
|||
static void musb_peri_rx_ep(unsigned int ep)
|
||||
{
|
||||
u16 peri_rxcount;
|
||||
u8 peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr);
|
||||
u16 peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr);
|
||||
|
||||
if (!(peri_rxcsr & MUSB_RXCSR_RXPKTRDY)) {
|
||||
if (debug_level > 0)
|
||||
|
@ -664,7 +666,10 @@ static void musb_peri_rx_ep(unsigned int ep)
|
|||
/* The common musb fifo reader */
|
||||
read_fifo(ep, length, data);
|
||||
|
||||
musb_peri_rx_ack(ep);
|
||||
if (length == peri_rxcount)
|
||||
musb_peri_rx_ack(ep);
|
||||
else
|
||||
pending_intrrx |= (1 << ep);
|
||||
|
||||
/*
|
||||
* urb's actual_length is updated in
|
||||
|
@ -677,18 +682,24 @@ static void musb_peri_rx_ep(unsigned int ep)
|
|||
serial_printf("ERROR : %s %d no space "
|
||||
"in rcv buffer\n",
|
||||
__PRETTY_FUNCTION__, ep);
|
||||
|
||||
pending_intrrx |= (1 << ep);
|
||||
}
|
||||
} else {
|
||||
if (debug_level > 0)
|
||||
serial_printf("ERROR : %s %d problem with "
|
||||
"endpoint\n",
|
||||
__PRETTY_FUNCTION__, ep);
|
||||
|
||||
pending_intrrx |= (1 << ep);
|
||||
}
|
||||
|
||||
} else {
|
||||
if (debug_level > 0)
|
||||
serial_printf("ERROR : %s %d with nothing to do\n",
|
||||
__PRETTY_FUNCTION__, ep);
|
||||
|
||||
musb_peri_rx_ack(ep);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -696,9 +707,7 @@ static void musb_peri_rx(u16 intr)
|
|||
{
|
||||
unsigned int ep;
|
||||
|
||||
/* Check for EP0 */
|
||||
if (0x01 & intr)
|
||||
musb_peri_ep0();
|
||||
/* First bit is reserved and does not indicate interrupt for EP0 */
|
||||
|
||||
for (ep = 1; ep < 16; ep++) {
|
||||
if ((1 << ep) & intr)
|
||||
|
@ -708,21 +717,16 @@ static void musb_peri_rx(u16 intr)
|
|||
|
||||
static void musb_peri_tx(u16 intr)
|
||||
{
|
||||
/* Check for EP0 */
|
||||
if (0x01 & intr)
|
||||
musb_peri_ep0_tx();
|
||||
unsigned int ep;
|
||||
|
||||
/*
|
||||
* Use this in the future when handling epN tx
|
||||
*
|
||||
* u8 ep;
|
||||
*
|
||||
* for (ep = 1; ep < 16; ep++) {
|
||||
* if ((1 << ep) & intr) {
|
||||
* / * handle tx for this endpoint * /
|
||||
* }
|
||||
* }
|
||||
*/
|
||||
/* Check for EP0: first bit indicates interrupt for both RX and TX */
|
||||
if (0x01 & intr)
|
||||
musb_peri_ep0();
|
||||
|
||||
for (ep = 1; ep < 16; ep++) {
|
||||
if ((1 << ep) & intr)
|
||||
udc_endpoint_write(GET_ENDPOINT(udc_device, ep));
|
||||
}
|
||||
}
|
||||
|
||||
void udc_irq(void)
|
||||
|
@ -744,8 +748,6 @@ void udc_irq(void)
|
|||
musb_peri_resume();
|
||||
}
|
||||
|
||||
musb_peri_ep0();
|
||||
|
||||
if (MUSB_INTR_RESET & intrusb) {
|
||||
usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
|
||||
musb_peri_reset();
|
||||
|
@ -775,13 +777,16 @@ void udc_irq(void)
|
|||
intrrx = readw(&musbr->intrrx);
|
||||
intrtx = readw(&musbr->intrtx);
|
||||
|
||||
intrrx |= pending_intrrx;
|
||||
pending_intrrx = 0;
|
||||
|
||||
if (intrrx)
|
||||
musb_peri_rx(intrrx);
|
||||
|
||||
if (intrtx)
|
||||
musb_peri_tx(intrtx);
|
||||
} else {
|
||||
if (MUSB_INTR_SOF & intrusb) {
|
||||
if (readw(&musbr->intrtx) & 0x1) {
|
||||
u8 faddr;
|
||||
faddr = readb(&musbr->faddr);
|
||||
/*
|
||||
|
@ -870,18 +875,8 @@ void udc_setup_ep(struct usb_device_instance *device, unsigned int id,
|
|||
ep0_endpoint->endpoint_address = 0xff;
|
||||
ep0_urb = usbd_alloc_urb(device, endpoint);
|
||||
} else if (MAX_ENDPOINT >= id) {
|
||||
int ep_addr;
|
||||
|
||||
/* Check the direction */
|
||||
ep_addr = endpoint->endpoint_address;
|
||||
if (USB_DIR_IN == (ep_addr & USB_ENDPOINT_DIR_MASK)) {
|
||||
/* IN */
|
||||
epinfo[(id * 2) + 1].epsize = endpoint->tx_packetSize;
|
||||
} else {
|
||||
/* OUT */
|
||||
epinfo[id * 2].epsize = endpoint->rcv_packetSize;
|
||||
}
|
||||
|
||||
epinfo[(id * 2) + 0].epsize = endpoint->rcv_packetSize;
|
||||
epinfo[(id * 2) + 1].epsize = endpoint->tx_packetSize;
|
||||
musb_configure_ep(&epinfo[0], ARRAY_SIZE(epinfo));
|
||||
} else {
|
||||
if (debug_level > 0)
|
||||
|
|
|
@ -70,10 +70,12 @@
|
|||
|
||||
/* USB device configuration */
|
||||
#define CONFIG_USB_DEVICE
|
||||
#define CONFIG_USB_TTY
|
||||
#define CONFIG_USBD_VENDORID 0x0421
|
||||
#define CONFIG_USBD_PRODUCTID 0x01c8
|
||||
#define CONFIG_USBD_PRODUCTID_CDCACM 0x01c8
|
||||
#define CONFIG_USBD_PRODUCTID_GSERIAL 0x01c8
|
||||
#define CONFIG_USBD_MANUFACTURER "Nokia"
|
||||
#define CONFIG_USBD_PRODUCT_NAME "N900"
|
||||
#define CONFIG_USBD_PRODUCT_NAME "N900 (U-Boot)"
|
||||
|
||||
#define GPIO_SLIDE 71
|
||||
|
||||
|
@ -108,15 +110,9 @@ int rx51_kp_getc(struct stdio_dev *sdev);
|
|||
/* Environment information */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"usbtty=cdc_acm\0" \
|
||||
"stdin=serial,vga\0" \
|
||||
"stdout=serial,vga\0" \
|
||||
"stderr=serial,vga\0" \
|
||||
"setcon=setenv stdin ${con};" \
|
||||
"setenv stdout ${con};" \
|
||||
"setenv stderr ${con}\0" \
|
||||
"sercon=setenv con serial; run setcon\0" \
|
||||
"usbcon=setenv con usbtty; run setcon\0" \
|
||||
"vgacon=setenv con vga; run setcon\0" \
|
||||
"stdin=usbtty,serial,vga\0" \
|
||||
"stdout=usbtty,serial,vga\0" \
|
||||
"stderr=usbtty,serial,vga\0" \
|
||||
"slide=gpio input " __stringify(GPIO_SLIDE) "\0" \
|
||||
"switchmmc=mmc dev ${mmcnum}\0" \
|
||||
"kernaddr=0x82008000\0" \
|
||||
|
@ -198,9 +194,6 @@ int rx51_kp_getc(struct stdio_dev *sdev);
|
|||
#define CONFIG_POSTBOOTMENU \
|
||||
"echo;" \
|
||||
"echo Extra commands:;" \
|
||||
"echo run sercon - Use serial port for control.;" \
|
||||
"echo run usbcon - Use usbtty for control.;" \
|
||||
"echo run vgacon - Use framebuffer/keyboard.;" \
|
||||
"echo run sdboot - Boot from SD card slot.;" \
|
||||
"echo run emmcboot - Boot internal eMMC memory.;" \
|
||||
"echo run attachboot - Boot attached kernel image.;" \
|
||||
|
|
Loading…
Add table
Reference in a new issue