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arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-Boot
This patch adds SPL support to the db-mv784mp-gp eval board. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
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parent
e7778ec153
commit
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4 changed files with 54 additions and 3 deletions
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@ -236,6 +236,7 @@ config KIRKWOOD
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config TARGET_DB_MV784MP_GP
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bool "Support db-mv784mp-gp"
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_MAXBCM
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bool "Support maxbcm"
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@ -9,4 +9,4 @@ VERSION 1
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BOOT_FROM spi
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# Binary Header (bin_hdr) with DDR3 training code
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BINARY board/Marvell/db-mv784mp-gp/binary.0 0000005b 00000068
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BINARY spl/u-boot-spl.bin 0000005b 00000068
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@ -1,2 +1,3 @@
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CONFIG_ARM=y
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CONFIG_TARGET_DB_MV784MP_GP=y
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CONFIG_SPL=y
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+S:CONFIG_ARM=y
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+S:CONFIG_TARGET_DB_MV784MP_GP=y
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@ -11,6 +11,8 @@
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_ARMADA_XP /* SOC Family Name */
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#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
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#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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@ -65,4 +67,51 @@
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*/
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#include "mv-common.h"
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/*
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* Memory layout while starting into the bin_hdr via the
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* BootROM:
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*
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* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
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* 0x4000.4030 bin_hdr start address
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* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
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* 0x4007.fffc BootROM stack top
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*
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* The address space between 0x4007.fffc and 0x400f.fff is not locked in
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* L2 cache thus cannot be used.
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*/
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x40004030
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#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
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#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
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CONFIG_SPL_BSS_MAX_SIZE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds"
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/* SPL related SPI defines */
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_SYS_MVEBU_DDR
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#define CONFIG_SPD_EEPROM 0x4e
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#endif /* _CONFIG_DB_MV7846MP_GP_H */
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