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riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux

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This sync has changes required to use GPIO in U-Boot and
U-Boot SPL.

Sync dts from linux v5.7-rc2 commit:
"riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file"
(sha1: 0a91330b2af9f71ceeeed483f92774182b58f6d9)

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Pragnesh Patel 2020-05-29 11:33:33 +05:30 • committed by Andes
parent 329e023868
commit 25d0853fcb
2 changed files with 45 additions and 1 deletions
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37
arch/riscv/dts/fu540-c000.dtsi
View file

@ -54,6 +54,7 @@
reg = <1>; reg = <1>;
riscv,isa = "rv64imafdc"; riscv,isa = "rv64imafdc";
tlb-split; tlb-split;
next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller { cpu1_intc: interrupt-controller {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "riscv,cpu-intc"; compatible = "riscv,cpu-intc";
@ -77,6 +78,7 @@
reg = <2>; reg = <2>;
riscv,isa = "rv64imafdc"; riscv,isa = "rv64imafdc";
tlb-split; tlb-split;
next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller { cpu2_intc: interrupt-controller {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "riscv,cpu-intc"; compatible = "riscv,cpu-intc";
@ -100,6 +102,7 @@
reg = <3>; reg = <3>;
riscv,isa = "rv64imafdc"; riscv,isa = "rv64imafdc";
tlb-split; tlb-split;
next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller { cpu3_intc: interrupt-controller {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "riscv,cpu-intc"; compatible = "riscv,cpu-intc";
@ -123,6 +126,7 @@
reg = <4>; reg = <4>;
riscv,isa = "rv64imafdc"; riscv,isa = "rv64imafdc";
tlb-split; tlb-split;
next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller { cpu4_intc: interrupt-controller {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "riscv,cpu-intc"; compatible = "riscv,cpu-intc";
@ -162,6 +166,13 @@
clocks = <&prci PRCI_CLK_TLCLK>; clocks = <&prci PRCI_CLK_TLCLK>;
status = "disabled"; status = "disabled";
}; };
dma: dma@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic0>;
interrupts = <23 24 25 26 27 28 29 30>;
#dma-cells = <1>;
};
uart1: serial@10011000 { uart1: serial@10011000 {
compatible = "sifive,fu540-c000-uart", "sifive,uart0"; compatible = "sifive,fu540-c000-uart", "sifive,uart0";
reg = <0x0 0x10011000 0x0 0x1000>; reg = <0x0 0x10011000 0x0 0x1000>;
@ -246,6 +257,30 @@
#pwm-cells = <3>; #pwm-cells = <3>;
status = "disabled"; status = "disabled";
}; };
l2cache: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic0>;
interrupts = <1 2 3>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
gpio: gpio@10060000 {
compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
interrupt-parent = <&plic0>;
interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
<14>, <15>, <16>, <17>, <18>, <19>, <20>,
<21>, <22>;
reg = <0x0 0x10060000 0x0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&prci PRCI_CLK_TLCLK>;
status = "disabled";
};
}; };
}; };

9
arch/riscv/dts/hifive-unleashed-a00.dts
View file

@ -2,6 +2,7 @@
/* Copyright (c) 2018-2019 SiFive, Inc */ /* Copyright (c) 2018-2019 SiFive, Inc */
#include "fu540-c000.dtsi" #include "fu540-c000.dtsi"
#include <dt-bindings/gpio/gpio.h>
/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
#define RTCCLK_FREQ 1000000 #define RTCCLK_FREQ 1000000
@ -41,6 +42,10 @@
clock-frequency = <RTCCLK_FREQ>; clock-frequency = <RTCCLK_FREQ>;
clock-output-names = "rtcclk"; clock-output-names = "rtcclk";
}; };
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
};
}; };
&uart0 { &uart0 {
@ -94,3 +99,7 @@
&pwm1 { &pwm1 {
status = "okay"; status = "okay";
}; };
&gpio {
status = "okay";
};