GitHub-Mirror/u-boot
2
0
Fork 0
mirror of https://github.com/Fishwaldo/u-boot.git synced 2025-07-07 06:52:23 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

ARM: imx: vining2000: Convert to ethernet DM

Browse source 
Convert the board to ethernet DM support. Adjust board file accordingly,
as the board_eth_init() contains custom clock configuration required for
this board to work. Furthermore, enable FEC1 clock to make FEC1 work as
well.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Marek Vasut 2019-11-26 09:39:10 +01:00 • committed by Stefano Babic
parent 5b97abab55
commit 26822fd23c
3 changed files with 8 additions and 35 deletions
Download patch file Download diff file Expand all files Collapse all files

38
board/softing/vining_2000/vining_2000.c
View file

@ -72,42 +72,23 @@ int dram_init(void)
return 0; return 0;
} }
static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
MUX_MODE_SION,
/* LAN8720 PHY Reset */
MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const pwm_led_pads[] = { static iomux_v3_cfg_t const pwm_led_pads[] = {
MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */ MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */ MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */ MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
}; };
#define PHY_RESET IMX_GPIO_NR(5, 9) static int board_net_init(void)
int board_eth_init(bd_t *bis)
{ {
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
unsigned char eth1addr[6]; unsigned char eth1addr[6];
int ret;
/* just to get secound mac address */ /* just to get second mac address */
imx_get_mac_from_fuse(1, eth1addr); imx_get_mac_from_fuse(1, eth1addr);
if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr)) if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
eth_env_set_enetaddr("eth1addr", eth1addr); eth_env_set_enetaddr("eth1addr", eth1addr);
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
/* /*
* Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
* ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
@ -123,15 +104,7 @@ int board_eth_init(bd_t *bis)
if (ret) if (ret)
goto eth_fail; goto eth_fail;
/* reset phy */ ret = enable_fec_anatop_clock(1, ENET_50MHZ);
gpio_request(PHY_RESET, "PHY-reset");
gpio_direction_output(PHY_RESET, 0);
mdelay(16);
gpio_set_value(PHY_RESET, 1);
mdelay(1);
ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
IMX_FEC_BASE);
if (ret) if (ret)
goto eth_fail; goto eth_fail;
@ -139,7 +112,6 @@ int board_eth_init(bd_t *bis)
eth_fail: eth_fail:
printf("FEC MXC: %s:failed (%i)\n", __func__, ret); printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
gpio_set_value(PHY_RESET, 0);
return ret; return ret;
} }
@ -424,7 +396,7 @@ int board_init(void)
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif #endif
return 0; return board_net_init();
} }
int checkboard(void) int checkboard(void)

3
configs/vining_2000_defconfig
View file

@ -59,6 +59,9 @@ CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_PCI=y CONFIG_PCI=y
CONFIG_DM_PCI=y CONFIG_DM_PCI=y

2
include/configs/vining_2000.h
View file

@ -58,8 +58,6 @@
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
/* Network */ /* Network */
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR #define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0 #define CONFIG_FEC_MXC_PHYADDR 0x0