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x86: fdt: Create basic .dtsi file for coreboot
This contains just the minimum information for a coreboot-based board. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
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4 changed files with 59 additions and 12 deletions
16
arch/x86/dts/coreboot.dtsi
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16
arch/x86/dts/coreboot.dtsi
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/include/ "skeleton.dtsi"
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/ {
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aliases {
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console = "/serial";
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};
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serial {
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compatible = "ns16550";
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reg-shift = <1>;
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io-mapped = <1>;
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multiplier = <1>;
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baudrate = <115200>;
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status = "disabled";
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};
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};
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13
arch/x86/dts/skeleton.dtsi
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arch/x86/dts/skeleton.dtsi
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/*
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* Skeleton device tree; the bare minimum needed to boot; just include and
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* add a compatible value. The bootloader will typically populate the memory
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* node.
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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aliases { };
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memory { device_type = "memory"; reg = <0 0>; };
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};
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@ -1,5 +1,7 @@
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/dts-v1/;
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/include/ "coreboot.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -10,19 +12,11 @@
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silent_console = <0>;
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};
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aliases {
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console = "/serial@e0401000";
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};
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gpio: gpio {};
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serial@e0401000 {
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compatible = "ns16550";
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reg = <0xe0401000 0x40>;
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id = <1>;
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reg-shift = <1>;
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baudrate = <115200>;
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clock-frequency = <4000000>;
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multiplier = <1>;
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status = "ok";
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serial {
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reg = <0x3f8 8>;
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clock-frequency = <115200>;
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};
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chosen { };
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24
board/chromebook-x86/dts/link.dts
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board/chromebook-x86/dts/link.dts
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/dts-v1/;
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/include/ "coreboot.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Google Link";
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compatible = "google,link", "intel,celeron-ivybridge";
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config {
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silent_console = <0>;
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};
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gpio: gpio {};
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serial {
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reg = <0x3f8 8>;
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clock-frequency = <115200>;
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};
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chosen { };
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memory { device_type = "memory"; reg = <0 0>; };
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};
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